clk-cdce925.c 21 KB

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  1. /*
  2. * Driver for TI Multi PLL CDCE913/925/937/949 clock synthesizer
  3. *
  4. * This driver always connects the Y1 to the input clock, Y2/Y3 to PLL1,
  5. * Y4/Y5 to PLL2, and so on. PLL frequency is set on a first-come-first-serve
  6. * basis. Clients can directly request any frequency that the chip can
  7. * deliver using the standard clk framework. In addition, the device can
  8. * be configured and activated via the devicetree.
  9. *
  10. * Copyright (C) 2014, Topic Embedded Products
  11. * Licenced under GPL
  12. */
  13. #include <linux/clk.h>
  14. #include <linux/clk-provider.h>
  15. #include <linux/delay.h>
  16. #include <linux/module.h>
  17. #include <linux/i2c.h>
  18. #include <linux/regmap.h>
  19. #include <linux/regulator/consumer.h>
  20. #include <linux/slab.h>
  21. #include <linux/gcd.h>
  22. /* Each chip has different number of PLLs and outputs, for example:
  23. * The CECE925 has 2 PLLs which can be routed through dividers to 5 outputs.
  24. * Model this as 2 PLL clocks which are parents to the outputs.
  25. */
  26. enum {
  27. CDCE913,
  28. CDCE925,
  29. CDCE937,
  30. CDCE949,
  31. };
  32. struct clk_cdce925_chip_info {
  33. int num_plls;
  34. int num_outputs;
  35. };
  36. static const struct clk_cdce925_chip_info clk_cdce925_chip_info_tbl[] = {
  37. [CDCE913] = { .num_plls = 1, .num_outputs = 3 },
  38. [CDCE925] = { .num_plls = 2, .num_outputs = 5 },
  39. [CDCE937] = { .num_plls = 3, .num_outputs = 7 },
  40. [CDCE949] = { .num_plls = 4, .num_outputs = 9 },
  41. };
  42. #define MAX_NUMBER_OF_PLLS 4
  43. #define MAX_NUMBER_OF_OUTPUTS 9
  44. #define CDCE925_REG_GLOBAL1 0x01
  45. #define CDCE925_REG_Y1SPIPDIVH 0x02
  46. #define CDCE925_REG_PDIVL 0x03
  47. #define CDCE925_REG_XCSEL 0x05
  48. /* PLL parameters start at 0x10, steps of 0x10 */
  49. #define CDCE925_OFFSET_PLL 0x10
  50. /* Add CDCE925_OFFSET_PLL * (pll) to these registers before sending */
  51. #define CDCE925_PLL_MUX_OUTPUTS 0x14
  52. #define CDCE925_PLL_MULDIV 0x18
  53. #define CDCE925_PLL_FREQUENCY_MIN 80000000ul
  54. #define CDCE925_PLL_FREQUENCY_MAX 230000000ul
  55. struct clk_cdce925_chip;
  56. struct clk_cdce925_output {
  57. struct clk_hw hw;
  58. struct clk_cdce925_chip *chip;
  59. u8 index;
  60. u16 pdiv; /* 1..127 for Y2-Y9; 1..1023 for Y1 */
  61. };
  62. #define to_clk_cdce925_output(_hw) \
  63. container_of(_hw, struct clk_cdce925_output, hw)
  64. struct clk_cdce925_pll {
  65. struct clk_hw hw;
  66. struct clk_cdce925_chip *chip;
  67. u8 index;
  68. u16 m; /* 1..511 */
  69. u16 n; /* 1..4095 */
  70. };
  71. #define to_clk_cdce925_pll(_hw) container_of(_hw, struct clk_cdce925_pll, hw)
  72. struct clk_cdce925_chip {
  73. struct regmap *regmap;
  74. struct i2c_client *i2c_client;
  75. const struct clk_cdce925_chip_info *chip_info;
  76. struct clk_cdce925_pll pll[MAX_NUMBER_OF_PLLS];
  77. struct clk_cdce925_output clk[MAX_NUMBER_OF_OUTPUTS];
  78. };
  79. /* ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** */
  80. static unsigned long cdce925_pll_calculate_rate(unsigned long parent_rate,
  81. u16 n, u16 m)
  82. {
  83. if ((!m || !n) || (m == n))
  84. return parent_rate; /* In bypass mode runs at same frequency */
  85. return mult_frac(parent_rate, (unsigned long)n, (unsigned long)m);
  86. }
  87. static unsigned long cdce925_pll_recalc_rate(struct clk_hw *hw,
  88. unsigned long parent_rate)
  89. {
  90. /* Output frequency of PLL is Fout = (Fin/Pdiv)*(N/M) */
  91. struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw);
  92. return cdce925_pll_calculate_rate(parent_rate, data->n, data->m);
  93. }
  94. static void cdce925_pll_find_rate(unsigned long rate,
  95. unsigned long parent_rate, u16 *n, u16 *m)
  96. {
  97. unsigned long un;
  98. unsigned long um;
  99. unsigned long g;
  100. if (rate <= parent_rate) {
  101. /* Can always deliver parent_rate in bypass mode */
  102. rate = parent_rate;
  103. *n = 0;
  104. *m = 0;
  105. } else {
  106. /* In PLL mode, need to apply min/max range */
  107. if (rate < CDCE925_PLL_FREQUENCY_MIN)
  108. rate = CDCE925_PLL_FREQUENCY_MIN;
  109. else if (rate > CDCE925_PLL_FREQUENCY_MAX)
  110. rate = CDCE925_PLL_FREQUENCY_MAX;
  111. g = gcd(rate, parent_rate);
  112. um = parent_rate / g;
  113. un = rate / g;
  114. /* When outside hw range, reduce to fit (rounding errors) */
  115. while ((un > 4095) || (um > 511)) {
  116. un >>= 1;
  117. um >>= 1;
  118. }
  119. if (un == 0)
  120. un = 1;
  121. if (um == 0)
  122. um = 1;
  123. *n = un;
  124. *m = um;
  125. }
  126. }
  127. static long cdce925_pll_round_rate(struct clk_hw *hw, unsigned long rate,
  128. unsigned long *parent_rate)
  129. {
  130. u16 n, m;
  131. cdce925_pll_find_rate(rate, *parent_rate, &n, &m);
  132. return (long)cdce925_pll_calculate_rate(*parent_rate, n, m);
  133. }
  134. static int cdce925_pll_set_rate(struct clk_hw *hw, unsigned long rate,
  135. unsigned long parent_rate)
  136. {
  137. struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw);
  138. if (!rate || (rate == parent_rate)) {
  139. data->m = 0; /* Bypass mode */
  140. data->n = 0;
  141. return 0;
  142. }
  143. if ((rate < CDCE925_PLL_FREQUENCY_MIN) ||
  144. (rate > CDCE925_PLL_FREQUENCY_MAX)) {
  145. pr_debug("%s: rate %lu outside PLL range.\n", __func__, rate);
  146. return -EINVAL;
  147. }
  148. if (rate < parent_rate) {
  149. pr_debug("%s: rate %lu less than parent rate %lu.\n", __func__,
  150. rate, parent_rate);
  151. return -EINVAL;
  152. }
  153. cdce925_pll_find_rate(rate, parent_rate, &data->n, &data->m);
  154. return 0;
  155. }
  156. /* calculate p = max(0, 4 - int(log2 (n/m))) */
  157. static u8 cdce925_pll_calc_p(u16 n, u16 m)
  158. {
  159. u8 p;
  160. u16 r = n / m;
  161. if (r >= 16)
  162. return 0;
  163. p = 4;
  164. while (r > 1) {
  165. r >>= 1;
  166. --p;
  167. }
  168. return p;
  169. }
  170. /* Returns VCO range bits for VCO1_0_RANGE */
  171. static u8 cdce925_pll_calc_range_bits(struct clk_hw *hw, u16 n, u16 m)
  172. {
  173. struct clk *parent = clk_get_parent(hw->clk);
  174. unsigned long rate = clk_get_rate(parent);
  175. rate = mult_frac(rate, (unsigned long)n, (unsigned long)m);
  176. if (rate >= 175000000)
  177. return 0x3;
  178. if (rate >= 150000000)
  179. return 0x02;
  180. if (rate >= 125000000)
  181. return 0x01;
  182. return 0x00;
  183. }
  184. /* I2C clock, hence everything must happen in (un)prepare because this
  185. * may sleep */
  186. static int cdce925_pll_prepare(struct clk_hw *hw)
  187. {
  188. struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw);
  189. u16 n = data->n;
  190. u16 m = data->m;
  191. u16 r;
  192. u8 q;
  193. u8 p;
  194. u16 nn;
  195. u8 pll[4]; /* Bits are spread out over 4 byte registers */
  196. u8 reg_ofs = data->index * CDCE925_OFFSET_PLL;
  197. unsigned i;
  198. if ((!m || !n) || (m == n)) {
  199. /* Set PLL mux to bypass mode, leave the rest as is */
  200. regmap_update_bits(data->chip->regmap,
  201. reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x80);
  202. } else {
  203. /* According to data sheet: */
  204. /* p = max(0, 4 - int(log2 (n/m))) */
  205. p = cdce925_pll_calc_p(n, m);
  206. /* nn = n * 2^p */
  207. nn = n * BIT(p);
  208. /* q = int(nn/m) */
  209. q = nn / m;
  210. if ((q < 16) || (q > 63)) {
  211. pr_debug("%s invalid q=%d\n", __func__, q);
  212. return -EINVAL;
  213. }
  214. r = nn - (m*q);
  215. if (r > 511) {
  216. pr_debug("%s invalid r=%d\n", __func__, r);
  217. return -EINVAL;
  218. }
  219. pr_debug("%s n=%d m=%d p=%d q=%d r=%d\n", __func__,
  220. n, m, p, q, r);
  221. /* encode into register bits */
  222. pll[0] = n >> 4;
  223. pll[1] = ((n & 0x0F) << 4) | ((r >> 5) & 0x0F);
  224. pll[2] = ((r & 0x1F) << 3) | ((q >> 3) & 0x07);
  225. pll[3] = ((q & 0x07) << 5) | (p << 2) |
  226. cdce925_pll_calc_range_bits(hw, n, m);
  227. /* Write to registers */
  228. for (i = 0; i < ARRAY_SIZE(pll); ++i)
  229. regmap_write(data->chip->regmap,
  230. reg_ofs + CDCE925_PLL_MULDIV + i, pll[i]);
  231. /* Enable PLL */
  232. regmap_update_bits(data->chip->regmap,
  233. reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x00);
  234. }
  235. return 0;
  236. }
  237. static void cdce925_pll_unprepare(struct clk_hw *hw)
  238. {
  239. struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw);
  240. u8 reg_ofs = data->index * CDCE925_OFFSET_PLL;
  241. regmap_update_bits(data->chip->regmap,
  242. reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x80);
  243. }
  244. static const struct clk_ops cdce925_pll_ops = {
  245. .prepare = cdce925_pll_prepare,
  246. .unprepare = cdce925_pll_unprepare,
  247. .recalc_rate = cdce925_pll_recalc_rate,
  248. .round_rate = cdce925_pll_round_rate,
  249. .set_rate = cdce925_pll_set_rate,
  250. };
  251. static void cdce925_clk_set_pdiv(struct clk_cdce925_output *data, u16 pdiv)
  252. {
  253. switch (data->index) {
  254. case 0:
  255. regmap_update_bits(data->chip->regmap,
  256. CDCE925_REG_Y1SPIPDIVH,
  257. 0x03, (pdiv >> 8) & 0x03);
  258. regmap_write(data->chip->regmap, 0x03, pdiv & 0xFF);
  259. break;
  260. case 1:
  261. regmap_update_bits(data->chip->regmap, 0x16, 0x7F, pdiv);
  262. break;
  263. case 2:
  264. regmap_update_bits(data->chip->regmap, 0x17, 0x7F, pdiv);
  265. break;
  266. case 3:
  267. regmap_update_bits(data->chip->regmap, 0x26, 0x7F, pdiv);
  268. break;
  269. case 4:
  270. regmap_update_bits(data->chip->regmap, 0x27, 0x7F, pdiv);
  271. break;
  272. case 5:
  273. regmap_update_bits(data->chip->regmap, 0x36, 0x7F, pdiv);
  274. break;
  275. case 6:
  276. regmap_update_bits(data->chip->regmap, 0x37, 0x7F, pdiv);
  277. break;
  278. case 7:
  279. regmap_update_bits(data->chip->regmap, 0x46, 0x7F, pdiv);
  280. break;
  281. case 8:
  282. regmap_update_bits(data->chip->regmap, 0x47, 0x7F, pdiv);
  283. break;
  284. }
  285. }
  286. static void cdce925_clk_activate(struct clk_cdce925_output *data)
  287. {
  288. switch (data->index) {
  289. case 0:
  290. regmap_update_bits(data->chip->regmap,
  291. CDCE925_REG_Y1SPIPDIVH, 0x0c, 0x0c);
  292. break;
  293. case 1:
  294. case 2:
  295. regmap_update_bits(data->chip->regmap, 0x14, 0x03, 0x03);
  296. break;
  297. case 3:
  298. case 4:
  299. regmap_update_bits(data->chip->regmap, 0x24, 0x03, 0x03);
  300. break;
  301. case 5:
  302. case 6:
  303. regmap_update_bits(data->chip->regmap, 0x34, 0x03, 0x03);
  304. break;
  305. case 7:
  306. case 8:
  307. regmap_update_bits(data->chip->regmap, 0x44, 0x03, 0x03);
  308. break;
  309. }
  310. }
  311. static int cdce925_clk_prepare(struct clk_hw *hw)
  312. {
  313. struct clk_cdce925_output *data = to_clk_cdce925_output(hw);
  314. cdce925_clk_set_pdiv(data, data->pdiv);
  315. cdce925_clk_activate(data);
  316. return 0;
  317. }
  318. static void cdce925_clk_unprepare(struct clk_hw *hw)
  319. {
  320. struct clk_cdce925_output *data = to_clk_cdce925_output(hw);
  321. /* Disable clock by setting divider to "0" */
  322. cdce925_clk_set_pdiv(data, 0);
  323. }
  324. static unsigned long cdce925_clk_recalc_rate(struct clk_hw *hw,
  325. unsigned long parent_rate)
  326. {
  327. struct clk_cdce925_output *data = to_clk_cdce925_output(hw);
  328. if (data->pdiv)
  329. return parent_rate / data->pdiv;
  330. return 0;
  331. }
  332. static u16 cdce925_calc_divider(unsigned long rate,
  333. unsigned long parent_rate)
  334. {
  335. unsigned long divider;
  336. if (!rate)
  337. return 0;
  338. if (rate >= parent_rate)
  339. return 1;
  340. divider = DIV_ROUND_CLOSEST(parent_rate, rate);
  341. if (divider > 0x7F)
  342. divider = 0x7F;
  343. return (u16)divider;
  344. }
  345. static unsigned long cdce925_clk_best_parent_rate(
  346. struct clk_hw *hw, unsigned long rate)
  347. {
  348. struct clk *pll = clk_get_parent(hw->clk);
  349. struct clk *root = clk_get_parent(pll);
  350. unsigned long root_rate = clk_get_rate(root);
  351. unsigned long best_rate_error = rate;
  352. u16 pdiv_min;
  353. u16 pdiv_max;
  354. u16 pdiv_best;
  355. u16 pdiv_now;
  356. if (root_rate % rate == 0)
  357. return root_rate; /* Don't need the PLL, use bypass */
  358. pdiv_min = (u16)max(1ul, DIV_ROUND_UP(CDCE925_PLL_FREQUENCY_MIN, rate));
  359. pdiv_max = (u16)min(127ul, CDCE925_PLL_FREQUENCY_MAX / rate);
  360. if (pdiv_min > pdiv_max)
  361. return 0; /* No can do? */
  362. pdiv_best = pdiv_min;
  363. for (pdiv_now = pdiv_min; pdiv_now < pdiv_max; ++pdiv_now) {
  364. unsigned long target_rate = rate * pdiv_now;
  365. long pll_rate = clk_round_rate(pll, target_rate);
  366. unsigned long actual_rate;
  367. unsigned long rate_error;
  368. if (pll_rate <= 0)
  369. continue;
  370. actual_rate = pll_rate / pdiv_now;
  371. rate_error = abs((long)actual_rate - (long)rate);
  372. if (rate_error < best_rate_error) {
  373. pdiv_best = pdiv_now;
  374. best_rate_error = rate_error;
  375. }
  376. /* TODO: Consider PLL frequency based on smaller n/m values
  377. * and pick the better one if the error is equal */
  378. }
  379. return rate * pdiv_best;
  380. }
  381. static long cdce925_clk_round_rate(struct clk_hw *hw, unsigned long rate,
  382. unsigned long *parent_rate)
  383. {
  384. unsigned long l_parent_rate = *parent_rate;
  385. u16 divider = cdce925_calc_divider(rate, l_parent_rate);
  386. if (l_parent_rate / divider != rate) {
  387. l_parent_rate = cdce925_clk_best_parent_rate(hw, rate);
  388. divider = cdce925_calc_divider(rate, l_parent_rate);
  389. *parent_rate = l_parent_rate;
  390. }
  391. if (divider)
  392. return (long)(l_parent_rate / divider);
  393. return 0;
  394. }
  395. static int cdce925_clk_set_rate(struct clk_hw *hw, unsigned long rate,
  396. unsigned long parent_rate)
  397. {
  398. struct clk_cdce925_output *data = to_clk_cdce925_output(hw);
  399. data->pdiv = cdce925_calc_divider(rate, parent_rate);
  400. return 0;
  401. }
  402. static const struct clk_ops cdce925_clk_ops = {
  403. .prepare = cdce925_clk_prepare,
  404. .unprepare = cdce925_clk_unprepare,
  405. .recalc_rate = cdce925_clk_recalc_rate,
  406. .round_rate = cdce925_clk_round_rate,
  407. .set_rate = cdce925_clk_set_rate,
  408. };
  409. static u16 cdce925_y1_calc_divider(unsigned long rate,
  410. unsigned long parent_rate)
  411. {
  412. unsigned long divider;
  413. if (!rate)
  414. return 0;
  415. if (rate >= parent_rate)
  416. return 1;
  417. divider = DIV_ROUND_CLOSEST(parent_rate, rate);
  418. if (divider > 0x3FF) /* Y1 has 10-bit divider */
  419. divider = 0x3FF;
  420. return (u16)divider;
  421. }
  422. static long cdce925_clk_y1_round_rate(struct clk_hw *hw, unsigned long rate,
  423. unsigned long *parent_rate)
  424. {
  425. unsigned long l_parent_rate = *parent_rate;
  426. u16 divider = cdce925_y1_calc_divider(rate, l_parent_rate);
  427. if (divider)
  428. return (long)(l_parent_rate / divider);
  429. return 0;
  430. }
  431. static int cdce925_clk_y1_set_rate(struct clk_hw *hw, unsigned long rate,
  432. unsigned long parent_rate)
  433. {
  434. struct clk_cdce925_output *data = to_clk_cdce925_output(hw);
  435. data->pdiv = cdce925_y1_calc_divider(rate, parent_rate);
  436. return 0;
  437. }
  438. static const struct clk_ops cdce925_clk_y1_ops = {
  439. .prepare = cdce925_clk_prepare,
  440. .unprepare = cdce925_clk_unprepare,
  441. .recalc_rate = cdce925_clk_recalc_rate,
  442. .round_rate = cdce925_clk_y1_round_rate,
  443. .set_rate = cdce925_clk_y1_set_rate,
  444. };
  445. #define CDCE925_I2C_COMMAND_BLOCK_TRANSFER 0x00
  446. #define CDCE925_I2C_COMMAND_BYTE_TRANSFER 0x80
  447. static int cdce925_regmap_i2c_write(
  448. void *context, const void *data, size_t count)
  449. {
  450. struct device *dev = context;
  451. struct i2c_client *i2c = to_i2c_client(dev);
  452. int ret;
  453. u8 reg_data[2];
  454. if (count != 2)
  455. return -ENOTSUPP;
  456. /* First byte is command code */
  457. reg_data[0] = CDCE925_I2C_COMMAND_BYTE_TRANSFER | ((u8 *)data)[0];
  458. reg_data[1] = ((u8 *)data)[1];
  459. dev_dbg(&i2c->dev, "%s(%zu) %#x %#x\n", __func__, count,
  460. reg_data[0], reg_data[1]);
  461. ret = i2c_master_send(i2c, reg_data, count);
  462. if (likely(ret == count))
  463. return 0;
  464. else if (ret < 0)
  465. return ret;
  466. else
  467. return -EIO;
  468. }
  469. static int cdce925_regmap_i2c_read(void *context,
  470. const void *reg, size_t reg_size, void *val, size_t val_size)
  471. {
  472. struct device *dev = context;
  473. struct i2c_client *i2c = to_i2c_client(dev);
  474. struct i2c_msg xfer[2];
  475. int ret;
  476. u8 reg_data[2];
  477. if (reg_size != 1)
  478. return -ENOTSUPP;
  479. xfer[0].addr = i2c->addr;
  480. xfer[0].flags = 0;
  481. xfer[0].buf = reg_data;
  482. if (val_size == 1) {
  483. reg_data[0] =
  484. CDCE925_I2C_COMMAND_BYTE_TRANSFER | ((u8 *)reg)[0];
  485. xfer[0].len = 1;
  486. } else {
  487. reg_data[0] =
  488. CDCE925_I2C_COMMAND_BLOCK_TRANSFER | ((u8 *)reg)[0];
  489. reg_data[1] = val_size;
  490. xfer[0].len = 2;
  491. }
  492. xfer[1].addr = i2c->addr;
  493. xfer[1].flags = I2C_M_RD;
  494. xfer[1].len = val_size;
  495. xfer[1].buf = val;
  496. ret = i2c_transfer(i2c->adapter, xfer, 2);
  497. if (likely(ret == 2)) {
  498. dev_dbg(&i2c->dev, "%s(%zu, %zu) %#x %#x\n", __func__,
  499. reg_size, val_size, reg_data[0], *((u8 *)val));
  500. return 0;
  501. } else if (ret < 0)
  502. return ret;
  503. else
  504. return -EIO;
  505. }
  506. static struct clk_hw *
  507. of_clk_cdce925_get(struct of_phandle_args *clkspec, void *_data)
  508. {
  509. struct clk_cdce925_chip *data = _data;
  510. unsigned int idx = clkspec->args[0];
  511. if (idx >= ARRAY_SIZE(data->clk)) {
  512. pr_err("%s: invalid index %u\n", __func__, idx);
  513. return ERR_PTR(-EINVAL);
  514. }
  515. return &data->clk[idx].hw;
  516. }
  517. static void cdce925_regulator_disable(void *regulator)
  518. {
  519. regulator_disable(regulator);
  520. }
  521. static int cdce925_regulator_enable(struct device *dev, const char *name)
  522. {
  523. struct regulator *regulator;
  524. int err;
  525. regulator = devm_regulator_get(dev, name);
  526. if (IS_ERR(regulator))
  527. return PTR_ERR(regulator);
  528. err = regulator_enable(regulator);
  529. if (err) {
  530. dev_err(dev, "Failed to enable %s: %d\n", name, err);
  531. return err;
  532. }
  533. return devm_add_action_or_reset(dev, cdce925_regulator_disable,
  534. regulator);
  535. }
  536. /* The CDCE925 uses a funky way to read/write registers. Bulk mode is
  537. * just weird, so just use the single byte mode exclusively. */
  538. static struct regmap_bus regmap_cdce925_bus = {
  539. .write = cdce925_regmap_i2c_write,
  540. .read = cdce925_regmap_i2c_read,
  541. };
  542. static int cdce925_probe(struct i2c_client *client,
  543. const struct i2c_device_id *id)
  544. {
  545. struct clk_cdce925_chip *data;
  546. struct device_node *node = client->dev.of_node;
  547. const char *parent_name;
  548. const char *pll_clk_name[MAX_NUMBER_OF_PLLS] = {NULL,};
  549. struct clk_init_data init;
  550. u32 value;
  551. int i;
  552. int err;
  553. struct device_node *np_output;
  554. char child_name[6];
  555. struct regmap_config config = {
  556. .name = "configuration0",
  557. .reg_bits = 8,
  558. .val_bits = 8,
  559. .cache_type = REGCACHE_RBTREE,
  560. };
  561. dev_dbg(&client->dev, "%s\n", __func__);
  562. err = cdce925_regulator_enable(&client->dev, "vdd");
  563. if (err)
  564. return err;
  565. err = cdce925_regulator_enable(&client->dev, "vddout");
  566. if (err)
  567. return err;
  568. data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL);
  569. if (!data)
  570. return -ENOMEM;
  571. data->i2c_client = client;
  572. data->chip_info = &clk_cdce925_chip_info_tbl[id->driver_data];
  573. config.max_register = CDCE925_OFFSET_PLL +
  574. data->chip_info->num_plls * 0x10 - 1;
  575. data->regmap = devm_regmap_init(&client->dev, &regmap_cdce925_bus,
  576. &client->dev, &config);
  577. if (IS_ERR(data->regmap)) {
  578. dev_err(&client->dev, "failed to allocate register map\n");
  579. return PTR_ERR(data->regmap);
  580. }
  581. i2c_set_clientdata(client, data);
  582. parent_name = of_clk_get_parent_name(node, 0);
  583. if (!parent_name) {
  584. dev_err(&client->dev, "missing parent clock\n");
  585. return -ENODEV;
  586. }
  587. dev_dbg(&client->dev, "parent is: %s\n", parent_name);
  588. if (of_property_read_u32(node, "xtal-load-pf", &value) == 0)
  589. regmap_write(data->regmap,
  590. CDCE925_REG_XCSEL, (value << 3) & 0xF8);
  591. /* PWDN bit */
  592. regmap_update_bits(data->regmap, CDCE925_REG_GLOBAL1, BIT(4), 0);
  593. /* Set input source for Y1 to be the XTAL */
  594. regmap_update_bits(data->regmap, 0x02, BIT(7), 0);
  595. init.ops = &cdce925_pll_ops;
  596. init.flags = 0;
  597. init.parent_names = &parent_name;
  598. init.num_parents = 1;
  599. /* Register PLL clocks */
  600. for (i = 0; i < data->chip_info->num_plls; ++i) {
  601. pll_clk_name[i] = kasprintf(GFP_KERNEL, "%pOFn.pll%d",
  602. client->dev.of_node, i);
  603. init.name = pll_clk_name[i];
  604. data->pll[i].chip = data;
  605. data->pll[i].hw.init = &init;
  606. data->pll[i].index = i;
  607. err = devm_clk_hw_register(&client->dev, &data->pll[i].hw);
  608. if (err) {
  609. dev_err(&client->dev, "Failed register PLL %d\n", i);
  610. goto error;
  611. }
  612. sprintf(child_name, "PLL%d", i+1);
  613. np_output = of_get_child_by_name(node, child_name);
  614. if (!np_output)
  615. continue;
  616. if (!of_property_read_u32(np_output,
  617. "clock-frequency", &value)) {
  618. err = clk_set_rate(data->pll[i].hw.clk, value);
  619. if (err)
  620. dev_err(&client->dev,
  621. "unable to set PLL frequency %ud\n",
  622. value);
  623. }
  624. if (!of_property_read_u32(np_output,
  625. "spread-spectrum", &value)) {
  626. u8 flag = of_property_read_bool(np_output,
  627. "spread-spectrum-center") ? 0x80 : 0x00;
  628. regmap_update_bits(data->regmap,
  629. 0x16 + (i*CDCE925_OFFSET_PLL),
  630. 0x80, flag);
  631. regmap_update_bits(data->regmap,
  632. 0x12 + (i*CDCE925_OFFSET_PLL),
  633. 0x07, value & 0x07);
  634. }
  635. of_node_put(np_output);
  636. }
  637. /* Register output clock Y1 */
  638. init.ops = &cdce925_clk_y1_ops;
  639. init.flags = 0;
  640. init.num_parents = 1;
  641. init.parent_names = &parent_name; /* Mux Y1 to input */
  642. init.name = kasprintf(GFP_KERNEL, "%pOFn.Y1", client->dev.of_node);
  643. data->clk[0].chip = data;
  644. data->clk[0].hw.init = &init;
  645. data->clk[0].index = 0;
  646. data->clk[0].pdiv = 1;
  647. err = devm_clk_hw_register(&client->dev, &data->clk[0].hw);
  648. kfree(init.name); /* clock framework made a copy of the name */
  649. if (err) {
  650. dev_err(&client->dev, "clock registration Y1 failed\n");
  651. goto error;
  652. }
  653. /* Register output clocks Y2 .. Y5*/
  654. init.ops = &cdce925_clk_ops;
  655. init.flags = CLK_SET_RATE_PARENT;
  656. init.num_parents = 1;
  657. for (i = 1; i < data->chip_info->num_outputs; ++i) {
  658. init.name = kasprintf(GFP_KERNEL, "%pOFn.Y%d",
  659. client->dev.of_node, i+1);
  660. data->clk[i].chip = data;
  661. data->clk[i].hw.init = &init;
  662. data->clk[i].index = i;
  663. data->clk[i].pdiv = 1;
  664. switch (i) {
  665. case 1:
  666. case 2:
  667. /* Mux Y2/3 to PLL1 */
  668. init.parent_names = &pll_clk_name[0];
  669. break;
  670. case 3:
  671. case 4:
  672. /* Mux Y4/5 to PLL2 */
  673. init.parent_names = &pll_clk_name[1];
  674. break;
  675. case 5:
  676. case 6:
  677. /* Mux Y6/7 to PLL3 */
  678. init.parent_names = &pll_clk_name[2];
  679. break;
  680. case 7:
  681. case 8:
  682. /* Mux Y8/9 to PLL4 */
  683. init.parent_names = &pll_clk_name[3];
  684. break;
  685. }
  686. err = devm_clk_hw_register(&client->dev, &data->clk[i].hw);
  687. kfree(init.name); /* clock framework made a copy of the name */
  688. if (err) {
  689. dev_err(&client->dev, "clock registration failed\n");
  690. goto error;
  691. }
  692. }
  693. /* Register the output clocks */
  694. err = of_clk_add_hw_provider(client->dev.of_node, of_clk_cdce925_get,
  695. data);
  696. if (err)
  697. dev_err(&client->dev, "unable to add OF clock provider\n");
  698. err = 0;
  699. error:
  700. for (i = 0; i < data->chip_info->num_plls; ++i)
  701. /* clock framework made a copy of the name */
  702. kfree(pll_clk_name[i]);
  703. return err;
  704. }
  705. static const struct i2c_device_id cdce925_id[] = {
  706. { "cdce913", CDCE913 },
  707. { "cdce925", CDCE925 },
  708. { "cdce937", CDCE937 },
  709. { "cdce949", CDCE949 },
  710. { }
  711. };
  712. MODULE_DEVICE_TABLE(i2c, cdce925_id);
  713. static const struct of_device_id clk_cdce925_of_match[] = {
  714. { .compatible = "ti,cdce913" },
  715. { .compatible = "ti,cdce925" },
  716. { .compatible = "ti,cdce937" },
  717. { .compatible = "ti,cdce949" },
  718. { },
  719. };
  720. MODULE_DEVICE_TABLE(of, clk_cdce925_of_match);
  721. static struct i2c_driver cdce925_driver = {
  722. .driver = {
  723. .name = "cdce925",
  724. .of_match_table = of_match_ptr(clk_cdce925_of_match),
  725. },
  726. .probe = cdce925_probe,
  727. .id_table = cdce925_id,
  728. };
  729. module_i2c_driver(cdce925_driver);
  730. MODULE_AUTHOR("Mike Looijmans <mike.looijmans@topic.nl>");
  731. MODULE_DESCRIPTION("TI CDCE913/925/937/949 driver");
  732. MODULE_LICENSE("GPL");