clk-axi-clkgen.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * AXI clkgen driver
  4. *
  5. * Copyright 2012-2013 Analog Devices Inc.
  6. * Author: Lars-Peter Clausen <lars@metafoo.de>
  7. */
  8. #include <linux/platform_device.h>
  9. #include <linux/clk-provider.h>
  10. #include <linux/slab.h>
  11. #include <linux/io.h>
  12. #include <linux/of.h>
  13. #include <linux/module.h>
  14. #include <linux/err.h>
  15. #define AXI_CLKGEN_V2_REG_RESET 0x40
  16. #define AXI_CLKGEN_V2_REG_CLKSEL 0x44
  17. #define AXI_CLKGEN_V2_REG_DRP_CNTRL 0x70
  18. #define AXI_CLKGEN_V2_REG_DRP_STATUS 0x74
  19. #define AXI_CLKGEN_V2_RESET_MMCM_ENABLE BIT(1)
  20. #define AXI_CLKGEN_V2_RESET_ENABLE BIT(0)
  21. #define AXI_CLKGEN_V2_DRP_CNTRL_SEL BIT(29)
  22. #define AXI_CLKGEN_V2_DRP_CNTRL_READ BIT(28)
  23. #define AXI_CLKGEN_V2_DRP_STATUS_BUSY BIT(16)
  24. #define MMCM_REG_CLKOUT5_2 0x07
  25. #define MMCM_REG_CLKOUT0_1 0x08
  26. #define MMCM_REG_CLKOUT0_2 0x09
  27. #define MMCM_REG_CLKOUT6_2 0x13
  28. #define MMCM_REG_CLK_FB1 0x14
  29. #define MMCM_REG_CLK_FB2 0x15
  30. #define MMCM_REG_CLK_DIV 0x16
  31. #define MMCM_REG_LOCK1 0x18
  32. #define MMCM_REG_LOCK2 0x19
  33. #define MMCM_REG_LOCK3 0x1a
  34. #define MMCM_REG_POWER 0x28
  35. #define MMCM_REG_FILTER1 0x4e
  36. #define MMCM_REG_FILTER2 0x4f
  37. #define MMCM_CLKOUT_NOCOUNT BIT(6)
  38. #define MMCM_CLK_DIV_DIVIDE BIT(11)
  39. #define MMCM_CLK_DIV_NOCOUNT BIT(12)
  40. struct axi_clkgen {
  41. void __iomem *base;
  42. struct clk_hw clk_hw;
  43. };
  44. static uint32_t axi_clkgen_lookup_filter(unsigned int m)
  45. {
  46. switch (m) {
  47. case 0:
  48. return 0x01001990;
  49. case 1:
  50. return 0x01001190;
  51. case 2:
  52. return 0x01009890;
  53. case 3:
  54. return 0x01001890;
  55. case 4:
  56. return 0x01008890;
  57. case 5 ... 8:
  58. return 0x01009090;
  59. case 9 ... 11:
  60. return 0x01000890;
  61. case 12:
  62. return 0x08009090;
  63. case 13 ... 22:
  64. return 0x01001090;
  65. case 23 ... 36:
  66. return 0x01008090;
  67. case 37 ... 46:
  68. return 0x08001090;
  69. default:
  70. return 0x08008090;
  71. }
  72. }
  73. static const uint32_t axi_clkgen_lock_table[] = {
  74. 0x060603e8, 0x060603e8, 0x080803e8, 0x0b0b03e8,
  75. 0x0e0e03e8, 0x111103e8, 0x131303e8, 0x161603e8,
  76. 0x191903e8, 0x1c1c03e8, 0x1f1f0384, 0x1f1f0339,
  77. 0x1f1f02ee, 0x1f1f02bc, 0x1f1f028a, 0x1f1f0271,
  78. 0x1f1f023f, 0x1f1f0226, 0x1f1f020d, 0x1f1f01f4,
  79. 0x1f1f01db, 0x1f1f01c2, 0x1f1f01a9, 0x1f1f0190,
  80. 0x1f1f0190, 0x1f1f0177, 0x1f1f015e, 0x1f1f015e,
  81. 0x1f1f0145, 0x1f1f0145, 0x1f1f012c, 0x1f1f012c,
  82. 0x1f1f012c, 0x1f1f0113, 0x1f1f0113, 0x1f1f0113,
  83. };
  84. static uint32_t axi_clkgen_lookup_lock(unsigned int m)
  85. {
  86. if (m < ARRAY_SIZE(axi_clkgen_lock_table))
  87. return axi_clkgen_lock_table[m];
  88. return 0x1f1f00fa;
  89. }
  90. static const unsigned int fpfd_min = 10000;
  91. static const unsigned int fpfd_max = 300000;
  92. static const unsigned int fvco_min = 600000;
  93. static const unsigned int fvco_max = 1200000;
  94. static void axi_clkgen_calc_params(unsigned long fin, unsigned long fout,
  95. unsigned int *best_d, unsigned int *best_m, unsigned int *best_dout)
  96. {
  97. unsigned long d, d_min, d_max, _d_min, _d_max;
  98. unsigned long m, m_min, m_max;
  99. unsigned long f, dout, best_f, fvco;
  100. unsigned long fract_shift = 0;
  101. unsigned long fvco_min_fract, fvco_max_fract;
  102. fin /= 1000;
  103. fout /= 1000;
  104. best_f = ULONG_MAX;
  105. *best_d = 0;
  106. *best_m = 0;
  107. *best_dout = 0;
  108. d_min = max_t(unsigned long, DIV_ROUND_UP(fin, fpfd_max), 1);
  109. d_max = min_t(unsigned long, fin / fpfd_min, 80);
  110. again:
  111. fvco_min_fract = fvco_min << fract_shift;
  112. fvco_max_fract = fvco_max << fract_shift;
  113. m_min = max_t(unsigned long, DIV_ROUND_UP(fvco_min_fract, fin) * d_min, 1);
  114. m_max = min_t(unsigned long, fvco_max_fract * d_max / fin, 64 << fract_shift);
  115. for (m = m_min; m <= m_max; m++) {
  116. _d_min = max(d_min, DIV_ROUND_UP(fin * m, fvco_max_fract));
  117. _d_max = min(d_max, fin * m / fvco_min_fract);
  118. for (d = _d_min; d <= _d_max; d++) {
  119. fvco = fin * m / d;
  120. dout = DIV_ROUND_CLOSEST(fvco, fout);
  121. dout = clamp_t(unsigned long, dout, 1, 128 << fract_shift);
  122. f = fvco / dout;
  123. if (abs(f - fout) < abs(best_f - fout)) {
  124. best_f = f;
  125. *best_d = d;
  126. *best_m = m << (3 - fract_shift);
  127. *best_dout = dout << (3 - fract_shift);
  128. if (best_f == fout)
  129. return;
  130. }
  131. }
  132. }
  133. /* Lets see if we find a better setting in fractional mode */
  134. if (fract_shift == 0) {
  135. fract_shift = 3;
  136. goto again;
  137. }
  138. }
  139. struct axi_clkgen_div_params {
  140. unsigned int low;
  141. unsigned int high;
  142. unsigned int edge;
  143. unsigned int nocount;
  144. unsigned int frac_en;
  145. unsigned int frac;
  146. unsigned int frac_wf_f;
  147. unsigned int frac_wf_r;
  148. unsigned int frac_phase;
  149. };
  150. static void axi_clkgen_calc_clk_params(unsigned int divider,
  151. unsigned int frac_divider, struct axi_clkgen_div_params *params)
  152. {
  153. memset(params, 0x0, sizeof(*params));
  154. if (divider == 1) {
  155. params->nocount = 1;
  156. return;
  157. }
  158. if (frac_divider == 0) {
  159. params->high = divider / 2;
  160. params->edge = divider % 2;
  161. params->low = divider - params->high;
  162. } else {
  163. params->frac_en = 1;
  164. params->frac = frac_divider;
  165. params->high = divider / 2;
  166. params->edge = divider % 2;
  167. params->low = params->high;
  168. if (params->edge == 0) {
  169. params->high--;
  170. params->frac_wf_r = 1;
  171. }
  172. if (params->edge == 0 || frac_divider == 1)
  173. params->low--;
  174. if (((params->edge == 0) ^ (frac_divider == 1)) ||
  175. (divider == 2 && frac_divider == 1))
  176. params->frac_wf_f = 1;
  177. params->frac_phase = params->edge * 4 + frac_divider / 2;
  178. }
  179. }
  180. static void axi_clkgen_write(struct axi_clkgen *axi_clkgen,
  181. unsigned int reg, unsigned int val)
  182. {
  183. writel(val, axi_clkgen->base + reg);
  184. }
  185. static void axi_clkgen_read(struct axi_clkgen *axi_clkgen,
  186. unsigned int reg, unsigned int *val)
  187. {
  188. *val = readl(axi_clkgen->base + reg);
  189. }
  190. static int axi_clkgen_wait_non_busy(struct axi_clkgen *axi_clkgen)
  191. {
  192. unsigned int timeout = 10000;
  193. unsigned int val;
  194. do {
  195. axi_clkgen_read(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_STATUS, &val);
  196. } while ((val & AXI_CLKGEN_V2_DRP_STATUS_BUSY) && --timeout);
  197. if (val & AXI_CLKGEN_V2_DRP_STATUS_BUSY)
  198. return -EIO;
  199. return val & 0xffff;
  200. }
  201. static int axi_clkgen_mmcm_read(struct axi_clkgen *axi_clkgen,
  202. unsigned int reg, unsigned int *val)
  203. {
  204. unsigned int reg_val;
  205. int ret;
  206. ret = axi_clkgen_wait_non_busy(axi_clkgen);
  207. if (ret < 0)
  208. return ret;
  209. reg_val = AXI_CLKGEN_V2_DRP_CNTRL_SEL | AXI_CLKGEN_V2_DRP_CNTRL_READ;
  210. reg_val |= (reg << 16);
  211. axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_CNTRL, reg_val);
  212. ret = axi_clkgen_wait_non_busy(axi_clkgen);
  213. if (ret < 0)
  214. return ret;
  215. *val = ret;
  216. return 0;
  217. }
  218. static int axi_clkgen_mmcm_write(struct axi_clkgen *axi_clkgen,
  219. unsigned int reg, unsigned int val, unsigned int mask)
  220. {
  221. unsigned int reg_val = 0;
  222. int ret;
  223. ret = axi_clkgen_wait_non_busy(axi_clkgen);
  224. if (ret < 0)
  225. return ret;
  226. if (mask != 0xffff) {
  227. axi_clkgen_mmcm_read(axi_clkgen, reg, &reg_val);
  228. reg_val &= ~mask;
  229. }
  230. reg_val |= AXI_CLKGEN_V2_DRP_CNTRL_SEL | (reg << 16) | (val & mask);
  231. axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_CNTRL, reg_val);
  232. return 0;
  233. }
  234. static void axi_clkgen_mmcm_enable(struct axi_clkgen *axi_clkgen,
  235. bool enable)
  236. {
  237. unsigned int val = AXI_CLKGEN_V2_RESET_ENABLE;
  238. if (enable)
  239. val |= AXI_CLKGEN_V2_RESET_MMCM_ENABLE;
  240. axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_RESET, val);
  241. }
  242. static struct axi_clkgen *clk_hw_to_axi_clkgen(struct clk_hw *clk_hw)
  243. {
  244. return container_of(clk_hw, struct axi_clkgen, clk_hw);
  245. }
  246. static void axi_clkgen_set_div(struct axi_clkgen *axi_clkgen,
  247. unsigned int reg1, unsigned int reg2, unsigned int reg3,
  248. struct axi_clkgen_div_params *params)
  249. {
  250. axi_clkgen_mmcm_write(axi_clkgen, reg1,
  251. (params->high << 6) | params->low, 0xefff);
  252. axi_clkgen_mmcm_write(axi_clkgen, reg2,
  253. (params->frac << 12) | (params->frac_en << 11) |
  254. (params->frac_wf_r << 10) | (params->edge << 7) |
  255. (params->nocount << 6), 0x7fff);
  256. if (reg3 != 0) {
  257. axi_clkgen_mmcm_write(axi_clkgen, reg3,
  258. (params->frac_phase << 11) | (params->frac_wf_f << 10), 0x3c00);
  259. }
  260. }
  261. static int axi_clkgen_set_rate(struct clk_hw *clk_hw,
  262. unsigned long rate, unsigned long parent_rate)
  263. {
  264. struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
  265. unsigned int d, m, dout;
  266. struct axi_clkgen_div_params params;
  267. uint32_t power = 0;
  268. uint32_t filter;
  269. uint32_t lock;
  270. if (parent_rate == 0 || rate == 0)
  271. return -EINVAL;
  272. axi_clkgen_calc_params(parent_rate, rate, &d, &m, &dout);
  273. if (d == 0 || dout == 0 || m == 0)
  274. return -EINVAL;
  275. if ((dout & 0x7) != 0 || (m & 0x7) != 0)
  276. power |= 0x9800;
  277. axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_POWER, power, 0x9800);
  278. filter = axi_clkgen_lookup_filter(m - 1);
  279. lock = axi_clkgen_lookup_lock(m - 1);
  280. axi_clkgen_calc_clk_params(dout >> 3, dout & 0x7, &params);
  281. axi_clkgen_set_div(axi_clkgen, MMCM_REG_CLKOUT0_1, MMCM_REG_CLKOUT0_2,
  282. MMCM_REG_CLKOUT5_2, &params);
  283. axi_clkgen_calc_clk_params(d, 0, &params);
  284. axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_CLK_DIV,
  285. (params.edge << 13) | (params.nocount << 12) |
  286. (params.high << 6) | params.low, 0x3fff);
  287. axi_clkgen_calc_clk_params(m >> 3, m & 0x7, &params);
  288. axi_clkgen_set_div(axi_clkgen, MMCM_REG_CLK_FB1, MMCM_REG_CLK_FB2,
  289. MMCM_REG_CLKOUT6_2, &params);
  290. axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK1, lock & 0x3ff, 0x3ff);
  291. axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK2,
  292. (((lock >> 16) & 0x1f) << 10) | 0x1, 0x7fff);
  293. axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK3,
  294. (((lock >> 24) & 0x1f) << 10) | 0x3e9, 0x7fff);
  295. axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_FILTER1, filter >> 16, 0x9900);
  296. axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_FILTER2, filter, 0x9900);
  297. return 0;
  298. }
  299. static long axi_clkgen_round_rate(struct clk_hw *hw, unsigned long rate,
  300. unsigned long *parent_rate)
  301. {
  302. unsigned int d, m, dout;
  303. unsigned long long tmp;
  304. axi_clkgen_calc_params(*parent_rate, rate, &d, &m, &dout);
  305. if (d == 0 || dout == 0 || m == 0)
  306. return -EINVAL;
  307. tmp = (unsigned long long)*parent_rate * m;
  308. tmp = DIV_ROUND_CLOSEST_ULL(tmp, dout * d);
  309. return min_t(unsigned long long, tmp, LONG_MAX);
  310. }
  311. static unsigned int axi_clkgen_get_div(struct axi_clkgen *axi_clkgen,
  312. unsigned int reg1, unsigned int reg2)
  313. {
  314. unsigned int val1, val2;
  315. unsigned int div;
  316. axi_clkgen_mmcm_read(axi_clkgen, reg2, &val2);
  317. if (val2 & MMCM_CLKOUT_NOCOUNT)
  318. return 8;
  319. axi_clkgen_mmcm_read(axi_clkgen, reg1, &val1);
  320. div = (val1 & 0x3f) + ((val1 >> 6) & 0x3f);
  321. div <<= 3;
  322. if (val2 & MMCM_CLK_DIV_DIVIDE) {
  323. if ((val2 & BIT(7)) && (val2 & 0x7000) != 0x1000)
  324. div += 8;
  325. else
  326. div += 16;
  327. div += (val2 >> 12) & 0x7;
  328. }
  329. return div;
  330. }
  331. static unsigned long axi_clkgen_recalc_rate(struct clk_hw *clk_hw,
  332. unsigned long parent_rate)
  333. {
  334. struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
  335. unsigned int d, m, dout;
  336. unsigned long long tmp;
  337. unsigned int val;
  338. dout = axi_clkgen_get_div(axi_clkgen, MMCM_REG_CLKOUT0_1,
  339. MMCM_REG_CLKOUT0_2);
  340. m = axi_clkgen_get_div(axi_clkgen, MMCM_REG_CLK_FB1,
  341. MMCM_REG_CLK_FB2);
  342. axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLK_DIV, &val);
  343. if (val & MMCM_CLK_DIV_NOCOUNT)
  344. d = 1;
  345. else
  346. d = (val & 0x3f) + ((val >> 6) & 0x3f);
  347. if (d == 0 || dout == 0)
  348. return 0;
  349. tmp = (unsigned long long)parent_rate * m;
  350. tmp = DIV_ROUND_CLOSEST_ULL(tmp, dout * d);
  351. return min_t(unsigned long long, tmp, ULONG_MAX);
  352. }
  353. static int axi_clkgen_enable(struct clk_hw *clk_hw)
  354. {
  355. struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
  356. axi_clkgen_mmcm_enable(axi_clkgen, true);
  357. return 0;
  358. }
  359. static void axi_clkgen_disable(struct clk_hw *clk_hw)
  360. {
  361. struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
  362. axi_clkgen_mmcm_enable(axi_clkgen, false);
  363. }
  364. static int axi_clkgen_set_parent(struct clk_hw *clk_hw, u8 index)
  365. {
  366. struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
  367. axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_CLKSEL, index);
  368. return 0;
  369. }
  370. static u8 axi_clkgen_get_parent(struct clk_hw *clk_hw)
  371. {
  372. struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
  373. unsigned int parent;
  374. axi_clkgen_read(axi_clkgen, AXI_CLKGEN_V2_REG_CLKSEL, &parent);
  375. return parent;
  376. }
  377. static const struct clk_ops axi_clkgen_ops = {
  378. .recalc_rate = axi_clkgen_recalc_rate,
  379. .round_rate = axi_clkgen_round_rate,
  380. .set_rate = axi_clkgen_set_rate,
  381. .enable = axi_clkgen_enable,
  382. .disable = axi_clkgen_disable,
  383. .set_parent = axi_clkgen_set_parent,
  384. .get_parent = axi_clkgen_get_parent,
  385. };
  386. static const struct of_device_id axi_clkgen_ids[] = {
  387. {
  388. .compatible = "adi,axi-clkgen-2.00.a",
  389. },
  390. { },
  391. };
  392. MODULE_DEVICE_TABLE(of, axi_clkgen_ids);
  393. static int axi_clkgen_probe(struct platform_device *pdev)
  394. {
  395. const struct of_device_id *id;
  396. struct axi_clkgen *axi_clkgen;
  397. struct clk_init_data init;
  398. const char *parent_names[2];
  399. const char *clk_name;
  400. struct resource *mem;
  401. unsigned int i;
  402. int ret;
  403. if (!pdev->dev.of_node)
  404. return -ENODEV;
  405. id = of_match_node(axi_clkgen_ids, pdev->dev.of_node);
  406. if (!id)
  407. return -ENODEV;
  408. axi_clkgen = devm_kzalloc(&pdev->dev, sizeof(*axi_clkgen), GFP_KERNEL);
  409. if (!axi_clkgen)
  410. return -ENOMEM;
  411. mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  412. axi_clkgen->base = devm_ioremap_resource(&pdev->dev, mem);
  413. if (IS_ERR(axi_clkgen->base))
  414. return PTR_ERR(axi_clkgen->base);
  415. init.num_parents = of_clk_get_parent_count(pdev->dev.of_node);
  416. if (init.num_parents < 1 || init.num_parents > 2)
  417. return -EINVAL;
  418. for (i = 0; i < init.num_parents; i++) {
  419. parent_names[i] = of_clk_get_parent_name(pdev->dev.of_node, i);
  420. if (!parent_names[i])
  421. return -EINVAL;
  422. }
  423. clk_name = pdev->dev.of_node->name;
  424. of_property_read_string(pdev->dev.of_node, "clock-output-names",
  425. &clk_name);
  426. init.name = clk_name;
  427. init.ops = &axi_clkgen_ops;
  428. init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
  429. init.parent_names = parent_names;
  430. axi_clkgen_mmcm_enable(axi_clkgen, false);
  431. axi_clkgen->clk_hw.init = &init;
  432. ret = devm_clk_hw_register(&pdev->dev, &axi_clkgen->clk_hw);
  433. if (ret)
  434. return ret;
  435. return of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_simple_get,
  436. &axi_clkgen->clk_hw);
  437. }
  438. static int axi_clkgen_remove(struct platform_device *pdev)
  439. {
  440. of_clk_del_provider(pdev->dev.of_node);
  441. return 0;
  442. }
  443. static struct platform_driver axi_clkgen_driver = {
  444. .driver = {
  445. .name = "adi-axi-clkgen",
  446. .of_match_table = axi_clkgen_ids,
  447. },
  448. .probe = axi_clkgen_probe,
  449. .remove = axi_clkgen_remove,
  450. };
  451. module_platform_driver(axi_clkgen_driver);
  452. MODULE_LICENSE("GPL v2");
  453. MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
  454. MODULE_DESCRIPTION("Driver for the Analog Devices' AXI clkgen pcore clock generator");