clk-aspeed.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. // Copyright IBM Corp
  3. #define pr_fmt(fmt) "clk-aspeed: " fmt
  4. #include <linux/mfd/syscon.h>
  5. #include <linux/of_address.h>
  6. #include <linux/of_device.h>
  7. #include <linux/platform_device.h>
  8. #include <linux/regmap.h>
  9. #include <linux/slab.h>
  10. #include <dt-bindings/clock/aspeed-clock.h>
  11. #include "clk-aspeed.h"
  12. #define ASPEED_NUM_CLKS 38
  13. #define ASPEED_RESET2_OFFSET 32
  14. #define ASPEED_RESET_CTRL 0x04
  15. #define ASPEED_CLK_SELECTION 0x08
  16. #define ASPEED_CLK_STOP_CTRL 0x0c
  17. #define ASPEED_MPLL_PARAM 0x20
  18. #define ASPEED_HPLL_PARAM 0x24
  19. #define AST2500_HPLL_BYPASS_EN BIT(20)
  20. #define AST2400_HPLL_PROGRAMMED BIT(18)
  21. #define AST2400_HPLL_BYPASS_EN BIT(17)
  22. #define ASPEED_MISC_CTRL 0x2c
  23. #define UART_DIV13_EN BIT(12)
  24. #define ASPEED_MAC_CLK_DLY 0x48
  25. #define ASPEED_STRAP 0x70
  26. #define CLKIN_25MHZ_EN BIT(23)
  27. #define AST2400_CLK_SOURCE_SEL BIT(18)
  28. #define ASPEED_CLK_SELECTION_2 0xd8
  29. #define ASPEED_RESET_CTRL2 0xd4
  30. /* Globally visible clocks */
  31. static DEFINE_SPINLOCK(aspeed_clk_lock);
  32. /* Keeps track of all clocks */
  33. static struct clk_hw_onecell_data *aspeed_clk_data;
  34. static void __iomem *scu_base;
  35. /* TODO: ask Aspeed about the actual parent data */
  36. static const struct aspeed_gate_data aspeed_gates[] = {
  37. /* clk rst name parent flags */
  38. [ASPEED_CLK_GATE_ECLK] = { 0, 6, "eclk-gate", "eclk", 0 }, /* Video Engine */
  39. [ASPEED_CLK_GATE_GCLK] = { 1, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
  40. [ASPEED_CLK_GATE_MCLK] = { 2, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
  41. [ASPEED_CLK_GATE_VCLK] = { 3, -1, "vclk-gate", NULL, 0 }, /* Video Capture */
  42. [ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", CLK_IS_CRITICAL }, /* PCIe/PCI */
  43. [ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, CLK_IS_CRITICAL }, /* DAC */
  44. [ASPEED_CLK_GATE_REFCLK] = { 6, -1, "refclk-gate", "clkin", CLK_IS_CRITICAL },
  45. [ASPEED_CLK_GATE_USBPORT2CLK] = { 7, 3, "usb-port2-gate", NULL, 0 }, /* USB2.0 Host port 2 */
  46. [ASPEED_CLK_GATE_LCLK] = { 8, 5, "lclk-gate", NULL, 0 }, /* LPC */
  47. [ASPEED_CLK_GATE_USBUHCICLK] = { 9, 15, "usb-uhci-gate", NULL, 0 }, /* USB1.1 (requires port 2 enabled) */
  48. [ASPEED_CLK_GATE_D1CLK] = { 10, 13, "d1clk-gate", NULL, 0 }, /* GFX CRT */
  49. [ASPEED_CLK_GATE_YCLK] = { 13, 4, "yclk-gate", NULL, 0 }, /* HAC */
  50. [ASPEED_CLK_GATE_USBPORT1CLK] = { 14, 14, "usb-port1-gate", NULL, 0 }, /* USB2 hub/USB2 host port 1/USB1.1 dev */
  51. [ASPEED_CLK_GATE_UART1CLK] = { 15, -1, "uart1clk-gate", "uart", 0 }, /* UART1 */
  52. [ASPEED_CLK_GATE_UART2CLK] = { 16, -1, "uart2clk-gate", "uart", 0 }, /* UART2 */
  53. [ASPEED_CLK_GATE_UART5CLK] = { 17, -1, "uart5clk-gate", "uart", 0 }, /* UART5 */
  54. [ASPEED_CLK_GATE_ESPICLK] = { 19, -1, "espiclk-gate", NULL, 0 }, /* eSPI */
  55. [ASPEED_CLK_GATE_MAC1CLK] = { 20, 11, "mac1clk-gate", "mac", 0 }, /* MAC1 */
  56. [ASPEED_CLK_GATE_MAC2CLK] = { 21, 12, "mac2clk-gate", "mac", 0 }, /* MAC2 */
  57. [ASPEED_CLK_GATE_RSACLK] = { 24, -1, "rsaclk-gate", NULL, 0 }, /* RSA */
  58. [ASPEED_CLK_GATE_UART3CLK] = { 25, -1, "uart3clk-gate", "uart", 0 }, /* UART3 */
  59. [ASPEED_CLK_GATE_UART4CLK] = { 26, -1, "uart4clk-gate", "uart", 0 }, /* UART4 */
  60. [ASPEED_CLK_GATE_SDCLK] = { 27, 16, "sdclk-gate", NULL, 0 }, /* SDIO/SD */
  61. [ASPEED_CLK_GATE_LHCCLK] = { 28, -1, "lhclk-gate", "lhclk", 0 }, /* LPC master/LPC+ */
  62. };
  63. static const char * const eclk_parent_names[] = {
  64. "mpll",
  65. "hpll",
  66. "dpll",
  67. };
  68. static const struct clk_div_table ast2500_eclk_div_table[] = {
  69. { 0x0, 2 },
  70. { 0x1, 2 },
  71. { 0x2, 3 },
  72. { 0x3, 4 },
  73. { 0x4, 5 },
  74. { 0x5, 6 },
  75. { 0x6, 7 },
  76. { 0x7, 8 },
  77. { 0 }
  78. };
  79. static const struct clk_div_table ast2500_mac_div_table[] = {
  80. { 0x0, 4 }, /* Yep, really. Aspeed confirmed this is correct */
  81. { 0x1, 4 },
  82. { 0x2, 6 },
  83. { 0x3, 8 },
  84. { 0x4, 10 },
  85. { 0x5, 12 },
  86. { 0x6, 14 },
  87. { 0x7, 16 },
  88. { 0 }
  89. };
  90. static const struct clk_div_table ast2400_div_table[] = {
  91. { 0x0, 2 },
  92. { 0x1, 4 },
  93. { 0x2, 6 },
  94. { 0x3, 8 },
  95. { 0x4, 10 },
  96. { 0x5, 12 },
  97. { 0x6, 14 },
  98. { 0x7, 16 },
  99. { 0 }
  100. };
  101. static const struct clk_div_table ast2500_div_table[] = {
  102. { 0x0, 4 },
  103. { 0x1, 8 },
  104. { 0x2, 12 },
  105. { 0x3, 16 },
  106. { 0x4, 20 },
  107. { 0x5, 24 },
  108. { 0x6, 28 },
  109. { 0x7, 32 },
  110. { 0 }
  111. };
  112. static struct clk_hw *aspeed_ast2400_calc_pll(const char *name, u32 val)
  113. {
  114. unsigned int mult, div;
  115. if (val & AST2400_HPLL_BYPASS_EN) {
  116. /* Pass through mode */
  117. mult = div = 1;
  118. } else {
  119. /* F = 24Mhz * (2-OD) * [(N + 2) / (D + 1)] */
  120. u32 n = (val >> 5) & 0x3f;
  121. u32 od = (val >> 4) & 0x1;
  122. u32 d = val & 0xf;
  123. mult = (2 - od) * (n + 2);
  124. div = d + 1;
  125. }
  126. return clk_hw_register_fixed_factor(NULL, name, "clkin", 0,
  127. mult, div);
  128. };
  129. static struct clk_hw *aspeed_ast2500_calc_pll(const char *name, u32 val)
  130. {
  131. unsigned int mult, div;
  132. if (val & AST2500_HPLL_BYPASS_EN) {
  133. /* Pass through mode */
  134. mult = div = 1;
  135. } else {
  136. /* F = clkin * [(M+1) / (N+1)] / (P + 1) */
  137. u32 p = (val >> 13) & 0x3f;
  138. u32 m = (val >> 5) & 0xff;
  139. u32 n = val & 0x1f;
  140. mult = (m + 1) / (n + 1);
  141. div = p + 1;
  142. }
  143. return clk_hw_register_fixed_factor(NULL, name, "clkin", 0,
  144. mult, div);
  145. }
  146. static const struct aspeed_clk_soc_data ast2500_data = {
  147. .div_table = ast2500_div_table,
  148. .eclk_div_table = ast2500_eclk_div_table,
  149. .mac_div_table = ast2500_mac_div_table,
  150. .calc_pll = aspeed_ast2500_calc_pll,
  151. };
  152. static const struct aspeed_clk_soc_data ast2400_data = {
  153. .div_table = ast2400_div_table,
  154. .eclk_div_table = ast2400_div_table,
  155. .mac_div_table = ast2400_div_table,
  156. .calc_pll = aspeed_ast2400_calc_pll,
  157. };
  158. static int aspeed_clk_is_enabled(struct clk_hw *hw)
  159. {
  160. struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
  161. u32 clk = BIT(gate->clock_idx);
  162. u32 rst = BIT(gate->reset_idx);
  163. u32 enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : clk;
  164. u32 reg;
  165. /*
  166. * If the IP is in reset, treat the clock as not enabled,
  167. * this happens with some clocks such as the USB one when
  168. * coming from cold reset. Without this, aspeed_clk_enable()
  169. * will fail to lift the reset.
  170. */
  171. if (gate->reset_idx >= 0) {
  172. regmap_read(gate->map, ASPEED_RESET_CTRL, &reg);
  173. if (reg & rst)
  174. return 0;
  175. }
  176. regmap_read(gate->map, ASPEED_CLK_STOP_CTRL, &reg);
  177. return ((reg & clk) == enval) ? 1 : 0;
  178. }
  179. static int aspeed_clk_enable(struct clk_hw *hw)
  180. {
  181. struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
  182. unsigned long flags;
  183. u32 clk = BIT(gate->clock_idx);
  184. u32 rst = BIT(gate->reset_idx);
  185. u32 enval;
  186. spin_lock_irqsave(gate->lock, flags);
  187. if (aspeed_clk_is_enabled(hw)) {
  188. spin_unlock_irqrestore(gate->lock, flags);
  189. return 0;
  190. }
  191. if (gate->reset_idx >= 0) {
  192. /* Put IP in reset */
  193. regmap_update_bits(gate->map, ASPEED_RESET_CTRL, rst, rst);
  194. /* Delay 100us */
  195. udelay(100);
  196. }
  197. /* Enable clock */
  198. enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : clk;
  199. regmap_update_bits(gate->map, ASPEED_CLK_STOP_CTRL, clk, enval);
  200. if (gate->reset_idx >= 0) {
  201. /* A delay of 10ms is specified by the ASPEED docs */
  202. mdelay(10);
  203. /* Take IP out of reset */
  204. regmap_update_bits(gate->map, ASPEED_RESET_CTRL, rst, 0);
  205. }
  206. spin_unlock_irqrestore(gate->lock, flags);
  207. return 0;
  208. }
  209. static void aspeed_clk_disable(struct clk_hw *hw)
  210. {
  211. struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
  212. unsigned long flags;
  213. u32 clk = BIT(gate->clock_idx);
  214. u32 enval;
  215. spin_lock_irqsave(gate->lock, flags);
  216. enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? clk : 0;
  217. regmap_update_bits(gate->map, ASPEED_CLK_STOP_CTRL, clk, enval);
  218. spin_unlock_irqrestore(gate->lock, flags);
  219. }
  220. static const struct clk_ops aspeed_clk_gate_ops = {
  221. .enable = aspeed_clk_enable,
  222. .disable = aspeed_clk_disable,
  223. .is_enabled = aspeed_clk_is_enabled,
  224. };
  225. static const u8 aspeed_resets[] = {
  226. /* SCU04 resets */
  227. [ASPEED_RESET_XDMA] = 25,
  228. [ASPEED_RESET_MCTP] = 24,
  229. [ASPEED_RESET_ADC] = 23,
  230. [ASPEED_RESET_JTAG_MASTER] = 22,
  231. [ASPEED_RESET_MIC] = 18,
  232. [ASPEED_RESET_PWM] = 9,
  233. [ASPEED_RESET_PECI] = 10,
  234. [ASPEED_RESET_I2C] = 2,
  235. [ASPEED_RESET_AHB] = 1,
  236. /*
  237. * SCUD4 resets start at an offset to separate them from
  238. * the SCU04 resets.
  239. */
  240. [ASPEED_RESET_CRT1] = ASPEED_RESET2_OFFSET + 5,
  241. };
  242. static int aspeed_reset_deassert(struct reset_controller_dev *rcdev,
  243. unsigned long id)
  244. {
  245. struct aspeed_reset *ar = to_aspeed_reset(rcdev);
  246. u32 reg = ASPEED_RESET_CTRL;
  247. u32 bit = aspeed_resets[id];
  248. if (bit >= ASPEED_RESET2_OFFSET) {
  249. bit -= ASPEED_RESET2_OFFSET;
  250. reg = ASPEED_RESET_CTRL2;
  251. }
  252. return regmap_update_bits(ar->map, reg, BIT(bit), 0);
  253. }
  254. static int aspeed_reset_assert(struct reset_controller_dev *rcdev,
  255. unsigned long id)
  256. {
  257. struct aspeed_reset *ar = to_aspeed_reset(rcdev);
  258. u32 reg = ASPEED_RESET_CTRL;
  259. u32 bit = aspeed_resets[id];
  260. if (bit >= ASPEED_RESET2_OFFSET) {
  261. bit -= ASPEED_RESET2_OFFSET;
  262. reg = ASPEED_RESET_CTRL2;
  263. }
  264. return regmap_update_bits(ar->map, reg, BIT(bit), BIT(bit));
  265. }
  266. static int aspeed_reset_status(struct reset_controller_dev *rcdev,
  267. unsigned long id)
  268. {
  269. struct aspeed_reset *ar = to_aspeed_reset(rcdev);
  270. u32 reg = ASPEED_RESET_CTRL;
  271. u32 bit = aspeed_resets[id];
  272. int ret, val;
  273. if (bit >= ASPEED_RESET2_OFFSET) {
  274. bit -= ASPEED_RESET2_OFFSET;
  275. reg = ASPEED_RESET_CTRL2;
  276. }
  277. ret = regmap_read(ar->map, reg, &val);
  278. if (ret)
  279. return ret;
  280. return !!(val & BIT(bit));
  281. }
  282. static const struct reset_control_ops aspeed_reset_ops = {
  283. .assert = aspeed_reset_assert,
  284. .deassert = aspeed_reset_deassert,
  285. .status = aspeed_reset_status,
  286. };
  287. static struct clk_hw *aspeed_clk_hw_register_gate(struct device *dev,
  288. const char *name, const char *parent_name, unsigned long flags,
  289. struct regmap *map, u8 clock_idx, u8 reset_idx,
  290. u8 clk_gate_flags, spinlock_t *lock)
  291. {
  292. struct aspeed_clk_gate *gate;
  293. struct clk_init_data init;
  294. struct clk_hw *hw;
  295. int ret;
  296. gate = kzalloc(sizeof(*gate), GFP_KERNEL);
  297. if (!gate)
  298. return ERR_PTR(-ENOMEM);
  299. init.name = name;
  300. init.ops = &aspeed_clk_gate_ops;
  301. init.flags = flags;
  302. init.parent_names = parent_name ? &parent_name : NULL;
  303. init.num_parents = parent_name ? 1 : 0;
  304. gate->map = map;
  305. gate->clock_idx = clock_idx;
  306. gate->reset_idx = reset_idx;
  307. gate->flags = clk_gate_flags;
  308. gate->lock = lock;
  309. gate->hw.init = &init;
  310. hw = &gate->hw;
  311. ret = clk_hw_register(dev, hw);
  312. if (ret) {
  313. kfree(gate);
  314. hw = ERR_PTR(ret);
  315. }
  316. return hw;
  317. }
  318. static int aspeed_clk_probe(struct platform_device *pdev)
  319. {
  320. const struct aspeed_clk_soc_data *soc_data;
  321. struct device *dev = &pdev->dev;
  322. struct aspeed_reset *ar;
  323. struct regmap *map;
  324. struct clk_hw *hw;
  325. u32 val, rate;
  326. int i, ret;
  327. map = syscon_node_to_regmap(dev->of_node);
  328. if (IS_ERR(map)) {
  329. dev_err(dev, "no syscon regmap\n");
  330. return PTR_ERR(map);
  331. }
  332. ar = devm_kzalloc(dev, sizeof(*ar), GFP_KERNEL);
  333. if (!ar)
  334. return -ENOMEM;
  335. ar->map = map;
  336. ar->rcdev.owner = THIS_MODULE;
  337. ar->rcdev.nr_resets = ARRAY_SIZE(aspeed_resets);
  338. ar->rcdev.ops = &aspeed_reset_ops;
  339. ar->rcdev.of_node = dev->of_node;
  340. ret = devm_reset_controller_register(dev, &ar->rcdev);
  341. if (ret) {
  342. dev_err(dev, "could not register reset controller\n");
  343. return ret;
  344. }
  345. /* SoC generations share common layouts but have different divisors */
  346. soc_data = of_device_get_match_data(dev);
  347. if (!soc_data) {
  348. dev_err(dev, "no match data for platform\n");
  349. return -EINVAL;
  350. }
  351. /* UART clock div13 setting */
  352. regmap_read(map, ASPEED_MISC_CTRL, &val);
  353. if (val & UART_DIV13_EN)
  354. rate = 24000000 / 13;
  355. else
  356. rate = 24000000;
  357. /* TODO: Find the parent data for the uart clock */
  358. hw = clk_hw_register_fixed_rate(dev, "uart", NULL, 0, rate);
  359. if (IS_ERR(hw))
  360. return PTR_ERR(hw);
  361. aspeed_clk_data->hws[ASPEED_CLK_UART] = hw;
  362. /*
  363. * Memory controller (M-PLL) PLL. This clock is configured by the
  364. * bootloader, and is exposed to Linux as a read-only clock rate.
  365. */
  366. regmap_read(map, ASPEED_MPLL_PARAM, &val);
  367. hw = soc_data->calc_pll("mpll", val);
  368. if (IS_ERR(hw))
  369. return PTR_ERR(hw);
  370. aspeed_clk_data->hws[ASPEED_CLK_MPLL] = hw;
  371. /* SD/SDIO clock divider and gate */
  372. hw = clk_hw_register_gate(dev, "sd_extclk_gate", "hpll", 0,
  373. scu_base + ASPEED_CLK_SELECTION, 15, 0,
  374. &aspeed_clk_lock);
  375. if (IS_ERR(hw))
  376. return PTR_ERR(hw);
  377. hw = clk_hw_register_divider_table(dev, "sd_extclk", "sd_extclk_gate",
  378. 0, scu_base + ASPEED_CLK_SELECTION, 12, 3, 0,
  379. soc_data->div_table,
  380. &aspeed_clk_lock);
  381. if (IS_ERR(hw))
  382. return PTR_ERR(hw);
  383. aspeed_clk_data->hws[ASPEED_CLK_SDIO] = hw;
  384. /* MAC AHB bus clock divider */
  385. hw = clk_hw_register_divider_table(dev, "mac", "hpll", 0,
  386. scu_base + ASPEED_CLK_SELECTION, 16, 3, 0,
  387. soc_data->mac_div_table,
  388. &aspeed_clk_lock);
  389. if (IS_ERR(hw))
  390. return PTR_ERR(hw);
  391. aspeed_clk_data->hws[ASPEED_CLK_MAC] = hw;
  392. if (of_device_is_compatible(pdev->dev.of_node, "aspeed,ast2500-scu")) {
  393. /* RMII 50MHz RCLK */
  394. hw = clk_hw_register_fixed_rate(dev, "mac12rclk", "hpll", 0,
  395. 50000000);
  396. if (IS_ERR(hw))
  397. return PTR_ERR(hw);
  398. /* RMII1 50MHz (RCLK) output enable */
  399. hw = clk_hw_register_gate(dev, "mac1rclk", "mac12rclk", 0,
  400. scu_base + ASPEED_MAC_CLK_DLY, 29, 0,
  401. &aspeed_clk_lock);
  402. if (IS_ERR(hw))
  403. return PTR_ERR(hw);
  404. aspeed_clk_data->hws[ASPEED_CLK_MAC1RCLK] = hw;
  405. /* RMII2 50MHz (RCLK) output enable */
  406. hw = clk_hw_register_gate(dev, "mac2rclk", "mac12rclk", 0,
  407. scu_base + ASPEED_MAC_CLK_DLY, 30, 0,
  408. &aspeed_clk_lock);
  409. if (IS_ERR(hw))
  410. return PTR_ERR(hw);
  411. aspeed_clk_data->hws[ASPEED_CLK_MAC2RCLK] = hw;
  412. }
  413. /* LPC Host (LHCLK) clock divider */
  414. hw = clk_hw_register_divider_table(dev, "lhclk", "hpll", 0,
  415. scu_base + ASPEED_CLK_SELECTION, 20, 3, 0,
  416. soc_data->div_table,
  417. &aspeed_clk_lock);
  418. if (IS_ERR(hw))
  419. return PTR_ERR(hw);
  420. aspeed_clk_data->hws[ASPEED_CLK_LHCLK] = hw;
  421. /* P-Bus (BCLK) clock divider */
  422. hw = clk_hw_register_divider_table(dev, "bclk", "hpll", 0,
  423. scu_base + ASPEED_CLK_SELECTION_2, 0, 2, 0,
  424. soc_data->div_table,
  425. &aspeed_clk_lock);
  426. if (IS_ERR(hw))
  427. return PTR_ERR(hw);
  428. aspeed_clk_data->hws[ASPEED_CLK_BCLK] = hw;
  429. /* Fixed 24MHz clock */
  430. hw = clk_hw_register_fixed_rate(NULL, "fixed-24m", "clkin",
  431. 0, 24000000);
  432. if (IS_ERR(hw))
  433. return PTR_ERR(hw);
  434. aspeed_clk_data->hws[ASPEED_CLK_24M] = hw;
  435. hw = clk_hw_register_mux(dev, "eclk-mux", eclk_parent_names,
  436. ARRAY_SIZE(eclk_parent_names), 0,
  437. scu_base + ASPEED_CLK_SELECTION, 2, 0x3, 0,
  438. &aspeed_clk_lock);
  439. if (IS_ERR(hw))
  440. return PTR_ERR(hw);
  441. aspeed_clk_data->hws[ASPEED_CLK_ECLK_MUX] = hw;
  442. hw = clk_hw_register_divider_table(dev, "eclk", "eclk-mux", 0,
  443. scu_base + ASPEED_CLK_SELECTION, 28,
  444. 3, 0, soc_data->eclk_div_table,
  445. &aspeed_clk_lock);
  446. if (IS_ERR(hw))
  447. return PTR_ERR(hw);
  448. aspeed_clk_data->hws[ASPEED_CLK_ECLK] = hw;
  449. /*
  450. * TODO: There are a number of clocks that not included in this driver
  451. * as more information is required:
  452. * D2-PLL
  453. * D-PLL
  454. * YCLK
  455. * RGMII
  456. * RMII
  457. * UART[1..5] clock source mux
  458. */
  459. for (i = 0; i < ARRAY_SIZE(aspeed_gates); i++) {
  460. const struct aspeed_gate_data *gd = &aspeed_gates[i];
  461. u32 gate_flags;
  462. /* Special case: the USB port 1 clock (bit 14) is always
  463. * working the opposite way from the other ones.
  464. */
  465. gate_flags = (gd->clock_idx == 14) ? 0 : CLK_GATE_SET_TO_DISABLE;
  466. hw = aspeed_clk_hw_register_gate(dev,
  467. gd->name,
  468. gd->parent_name,
  469. gd->flags,
  470. map,
  471. gd->clock_idx,
  472. gd->reset_idx,
  473. gate_flags,
  474. &aspeed_clk_lock);
  475. if (IS_ERR(hw))
  476. return PTR_ERR(hw);
  477. aspeed_clk_data->hws[i] = hw;
  478. }
  479. return 0;
  480. };
  481. static const struct of_device_id aspeed_clk_dt_ids[] = {
  482. { .compatible = "aspeed,ast2400-scu", .data = &ast2400_data },
  483. { .compatible = "aspeed,ast2500-scu", .data = &ast2500_data },
  484. { }
  485. };
  486. static struct platform_driver aspeed_clk_driver = {
  487. .probe = aspeed_clk_probe,
  488. .driver = {
  489. .name = "aspeed-clk",
  490. .of_match_table = aspeed_clk_dt_ids,
  491. .suppress_bind_attrs = true,
  492. },
  493. };
  494. builtin_platform_driver(aspeed_clk_driver);
  495. static void __init aspeed_ast2400_cc(struct regmap *map)
  496. {
  497. struct clk_hw *hw;
  498. u32 val, div, clkin, hpll;
  499. const u16 hpll_rates[][4] = {
  500. {384, 360, 336, 408},
  501. {400, 375, 350, 425},
  502. };
  503. int rate;
  504. /*
  505. * CLKIN is the crystal oscillator, 24, 48 or 25MHz selected by
  506. * strapping
  507. */
  508. regmap_read(map, ASPEED_STRAP, &val);
  509. rate = (val >> 8) & 3;
  510. if (val & CLKIN_25MHZ_EN) {
  511. clkin = 25000000;
  512. hpll = hpll_rates[1][rate];
  513. } else if (val & AST2400_CLK_SOURCE_SEL) {
  514. clkin = 48000000;
  515. hpll = hpll_rates[0][rate];
  516. } else {
  517. clkin = 24000000;
  518. hpll = hpll_rates[0][rate];
  519. }
  520. hw = clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, clkin);
  521. pr_debug("clkin @%u MHz\n", clkin / 1000000);
  522. /*
  523. * High-speed PLL clock derived from the crystal. This the CPU clock,
  524. * and we assume that it is enabled. It can be configured through the
  525. * HPLL_PARAM register, or set to a specified frequency by strapping.
  526. */
  527. regmap_read(map, ASPEED_HPLL_PARAM, &val);
  528. if (val & AST2400_HPLL_PROGRAMMED)
  529. hw = aspeed_ast2400_calc_pll("hpll", val);
  530. else
  531. hw = clk_hw_register_fixed_rate(NULL, "hpll", "clkin", 0,
  532. hpll * 1000000);
  533. aspeed_clk_data->hws[ASPEED_CLK_HPLL] = hw;
  534. /*
  535. * Strap bits 11:10 define the CPU/AHB clock frequency ratio (aka HCLK)
  536. * 00: Select CPU:AHB = 1:1
  537. * 01: Select CPU:AHB = 2:1
  538. * 10: Select CPU:AHB = 4:1
  539. * 11: Select CPU:AHB = 3:1
  540. */
  541. regmap_read(map, ASPEED_STRAP, &val);
  542. val = (val >> 10) & 0x3;
  543. div = val + 1;
  544. if (div == 3)
  545. div = 4;
  546. else if (div == 4)
  547. div = 3;
  548. hw = clk_hw_register_fixed_factor(NULL, "ahb", "hpll", 0, 1, div);
  549. aspeed_clk_data->hws[ASPEED_CLK_AHB] = hw;
  550. /* APB clock clock selection register SCU08 (aka PCLK) */
  551. hw = clk_hw_register_divider_table(NULL, "apb", "hpll", 0,
  552. scu_base + ASPEED_CLK_SELECTION, 23, 3, 0,
  553. ast2400_div_table,
  554. &aspeed_clk_lock);
  555. aspeed_clk_data->hws[ASPEED_CLK_APB] = hw;
  556. }
  557. static void __init aspeed_ast2500_cc(struct regmap *map)
  558. {
  559. struct clk_hw *hw;
  560. u32 val, freq, div;
  561. /* CLKIN is the crystal oscillator, 24 or 25MHz selected by strapping */
  562. regmap_read(map, ASPEED_STRAP, &val);
  563. if (val & CLKIN_25MHZ_EN)
  564. freq = 25000000;
  565. else
  566. freq = 24000000;
  567. hw = clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, freq);
  568. pr_debug("clkin @%u MHz\n", freq / 1000000);
  569. /*
  570. * High-speed PLL clock derived from the crystal. This the CPU clock,
  571. * and we assume that it is enabled
  572. */
  573. regmap_read(map, ASPEED_HPLL_PARAM, &val);
  574. aspeed_clk_data->hws[ASPEED_CLK_HPLL] = aspeed_ast2500_calc_pll("hpll", val);
  575. /* Strap bits 11:9 define the AXI/AHB clock frequency ratio (aka HCLK)*/
  576. regmap_read(map, ASPEED_STRAP, &val);
  577. val = (val >> 9) & 0x7;
  578. WARN(val == 0, "strapping is zero: cannot determine ahb clock");
  579. div = 2 * (val + 1);
  580. hw = clk_hw_register_fixed_factor(NULL, "ahb", "hpll", 0, 1, div);
  581. aspeed_clk_data->hws[ASPEED_CLK_AHB] = hw;
  582. /* APB clock clock selection register SCU08 (aka PCLK) */
  583. regmap_read(map, ASPEED_CLK_SELECTION, &val);
  584. val = (val >> 23) & 0x7;
  585. div = 4 * (val + 1);
  586. hw = clk_hw_register_fixed_factor(NULL, "apb", "hpll", 0, 1, div);
  587. aspeed_clk_data->hws[ASPEED_CLK_APB] = hw;
  588. };
  589. static void __init aspeed_cc_init(struct device_node *np)
  590. {
  591. struct regmap *map;
  592. u32 val;
  593. int ret;
  594. int i;
  595. scu_base = of_iomap(np, 0);
  596. if (!scu_base)
  597. return;
  598. aspeed_clk_data = kzalloc(struct_size(aspeed_clk_data, hws,
  599. ASPEED_NUM_CLKS),
  600. GFP_KERNEL);
  601. if (!aspeed_clk_data)
  602. return;
  603. /*
  604. * This way all clocks fetched before the platform device probes,
  605. * except those we assign here for early use, will be deferred.
  606. */
  607. for (i = 0; i < ASPEED_NUM_CLKS; i++)
  608. aspeed_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
  609. map = syscon_node_to_regmap(np);
  610. if (IS_ERR(map)) {
  611. pr_err("no syscon regmap\n");
  612. return;
  613. }
  614. /*
  615. * We check that the regmap works on this very first access,
  616. * but as this is an MMIO-backed regmap, subsequent regmap
  617. * access is not going to fail and we skip error checks from
  618. * this point.
  619. */
  620. ret = regmap_read(map, ASPEED_STRAP, &val);
  621. if (ret) {
  622. pr_err("failed to read strapping register\n");
  623. return;
  624. }
  625. if (of_device_is_compatible(np, "aspeed,ast2400-scu"))
  626. aspeed_ast2400_cc(map);
  627. else if (of_device_is_compatible(np, "aspeed,ast2500-scu"))
  628. aspeed_ast2500_cc(map);
  629. else
  630. pr_err("unknown platform, failed to add clocks\n");
  631. aspeed_clk_data->num = ASPEED_NUM_CLKS;
  632. ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_clk_data);
  633. if (ret)
  634. pr_err("failed to add DT provider: %d\n", ret);
  635. };
  636. CLK_OF_DECLARE_DRIVER(aspeed_cc_g5, "aspeed,ast2500-scu", aspeed_cc_init);
  637. CLK_OF_DECLARE_DRIVER(aspeed_cc_g4, "aspeed,ast2400-scu", aspeed_cc_init);