clk-asm9260.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2014 Oleksij Rempel <linux@rempel-privat.de>.
  4. */
  5. #include <linux/clk.h>
  6. #include <linux/clkdev.h>
  7. #include <linux/err.h>
  8. #include <linux/io.h>
  9. #include <linux/clk-provider.h>
  10. #include <linux/spinlock.h>
  11. #include <linux/of.h>
  12. #include <linux/of_address.h>
  13. #include <dt-bindings/clock/alphascale,asm9260.h>
  14. #define HW_AHBCLKCTRL0 0x0020
  15. #define HW_AHBCLKCTRL1 0x0030
  16. #define HW_SYSPLLCTRL 0x0100
  17. #define HW_MAINCLKSEL 0x0120
  18. #define HW_MAINCLKUEN 0x0124
  19. #define HW_UARTCLKSEL 0x0128
  20. #define HW_UARTCLKUEN 0x012c
  21. #define HW_I2S0CLKSEL 0x0130
  22. #define HW_I2S0CLKUEN 0x0134
  23. #define HW_I2S1CLKSEL 0x0138
  24. #define HW_I2S1CLKUEN 0x013c
  25. #define HW_WDTCLKSEL 0x0160
  26. #define HW_WDTCLKUEN 0x0164
  27. #define HW_CLKOUTCLKSEL 0x0170
  28. #define HW_CLKOUTCLKUEN 0x0174
  29. #define HW_CPUCLKDIV 0x017c
  30. #define HW_SYSAHBCLKDIV 0x0180
  31. #define HW_I2S0MCLKDIV 0x0190
  32. #define HW_I2S0SCLKDIV 0x0194
  33. #define HW_I2S1MCLKDIV 0x0188
  34. #define HW_I2S1SCLKDIV 0x018c
  35. #define HW_UART0CLKDIV 0x0198
  36. #define HW_UART1CLKDIV 0x019c
  37. #define HW_UART2CLKDIV 0x01a0
  38. #define HW_UART3CLKDIV 0x01a4
  39. #define HW_UART4CLKDIV 0x01a8
  40. #define HW_UART5CLKDIV 0x01ac
  41. #define HW_UART6CLKDIV 0x01b0
  42. #define HW_UART7CLKDIV 0x01b4
  43. #define HW_UART8CLKDIV 0x01b8
  44. #define HW_UART9CLKDIV 0x01bc
  45. #define HW_SPI0CLKDIV 0x01c0
  46. #define HW_SPI1CLKDIV 0x01c4
  47. #define HW_QUADSPICLKDIV 0x01c8
  48. #define HW_SSP0CLKDIV 0x01d0
  49. #define HW_NANDCLKDIV 0x01d4
  50. #define HW_TRACECLKDIV 0x01e0
  51. #define HW_CAMMCLKDIV 0x01e8
  52. #define HW_WDTCLKDIV 0x01ec
  53. #define HW_CLKOUTCLKDIV 0x01f4
  54. #define HW_MACCLKDIV 0x01f8
  55. #define HW_LCDCLKDIV 0x01fc
  56. #define HW_ADCANACLKDIV 0x0200
  57. static struct clk_hw_onecell_data *clk_data;
  58. static DEFINE_SPINLOCK(asm9260_clk_lock);
  59. struct asm9260_div_clk {
  60. unsigned int idx;
  61. const char *name;
  62. const char *parent_name;
  63. u32 reg;
  64. };
  65. struct asm9260_gate_data {
  66. unsigned int idx;
  67. const char *name;
  68. const char *parent_name;
  69. u32 reg;
  70. u8 bit_idx;
  71. unsigned long flags;
  72. };
  73. struct asm9260_mux_clock {
  74. u8 mask;
  75. u32 *table;
  76. const char *name;
  77. const char **parent_names;
  78. u8 num_parents;
  79. unsigned long offset;
  80. unsigned long flags;
  81. };
  82. static void __iomem *base;
  83. static const struct asm9260_div_clk asm9260_div_clks[] __initconst = {
  84. { CLKID_SYS_CPU, "cpu_div", "main_gate", HW_CPUCLKDIV },
  85. { CLKID_SYS_AHB, "ahb_div", "cpu_div", HW_SYSAHBCLKDIV },
  86. /* i2s has two deviders: one for only external mclk and internal
  87. * devider for all clks. */
  88. { CLKID_SYS_I2S0M, "i2s0m_div", "i2s0_mclk", HW_I2S0MCLKDIV },
  89. { CLKID_SYS_I2S1M, "i2s1m_div", "i2s1_mclk", HW_I2S1MCLKDIV },
  90. { CLKID_SYS_I2S0S, "i2s0s_div", "i2s0_gate", HW_I2S0SCLKDIV },
  91. { CLKID_SYS_I2S1S, "i2s1s_div", "i2s0_gate", HW_I2S1SCLKDIV },
  92. { CLKID_SYS_UART0, "uart0_div", "uart_gate", HW_UART0CLKDIV },
  93. { CLKID_SYS_UART1, "uart1_div", "uart_gate", HW_UART1CLKDIV },
  94. { CLKID_SYS_UART2, "uart2_div", "uart_gate", HW_UART2CLKDIV },
  95. { CLKID_SYS_UART3, "uart3_div", "uart_gate", HW_UART3CLKDIV },
  96. { CLKID_SYS_UART4, "uart4_div", "uart_gate", HW_UART4CLKDIV },
  97. { CLKID_SYS_UART5, "uart5_div", "uart_gate", HW_UART5CLKDIV },
  98. { CLKID_SYS_UART6, "uart6_div", "uart_gate", HW_UART6CLKDIV },
  99. { CLKID_SYS_UART7, "uart7_div", "uart_gate", HW_UART7CLKDIV },
  100. { CLKID_SYS_UART8, "uart8_div", "uart_gate", HW_UART8CLKDIV },
  101. { CLKID_SYS_UART9, "uart9_div", "uart_gate", HW_UART9CLKDIV },
  102. { CLKID_SYS_SPI0, "spi0_div", "main_gate", HW_SPI0CLKDIV },
  103. { CLKID_SYS_SPI1, "spi1_div", "main_gate", HW_SPI1CLKDIV },
  104. { CLKID_SYS_QUADSPI, "quadspi_div", "main_gate", HW_QUADSPICLKDIV },
  105. { CLKID_SYS_SSP0, "ssp0_div", "main_gate", HW_SSP0CLKDIV },
  106. { CLKID_SYS_NAND, "nand_div", "main_gate", HW_NANDCLKDIV },
  107. { CLKID_SYS_TRACE, "trace_div", "main_gate", HW_TRACECLKDIV },
  108. { CLKID_SYS_CAMM, "camm_div", "main_gate", HW_CAMMCLKDIV },
  109. { CLKID_SYS_MAC, "mac_div", "main_gate", HW_MACCLKDIV },
  110. { CLKID_SYS_LCD, "lcd_div", "main_gate", HW_LCDCLKDIV },
  111. { CLKID_SYS_ADCANA, "adcana_div", "main_gate", HW_ADCANACLKDIV },
  112. { CLKID_SYS_WDT, "wdt_div", "wdt_gate", HW_WDTCLKDIV },
  113. { CLKID_SYS_CLKOUT, "clkout_div", "clkout_gate", HW_CLKOUTCLKDIV },
  114. };
  115. static const struct asm9260_gate_data asm9260_mux_gates[] __initconst = {
  116. { 0, "main_gate", "main_mux", HW_MAINCLKUEN, 0 },
  117. { 0, "uart_gate", "uart_mux", HW_UARTCLKUEN, 0 },
  118. { 0, "i2s0_gate", "i2s0_mux", HW_I2S0CLKUEN, 0 },
  119. { 0, "i2s1_gate", "i2s1_mux", HW_I2S1CLKUEN, 0 },
  120. { 0, "wdt_gate", "wdt_mux", HW_WDTCLKUEN, 0 },
  121. { 0, "clkout_gate", "clkout_mux", HW_CLKOUTCLKUEN, 0 },
  122. };
  123. static const struct asm9260_gate_data asm9260_ahb_gates[] __initconst = {
  124. /* ahb gates */
  125. { CLKID_AHB_ROM, "rom", "ahb_div",
  126. HW_AHBCLKCTRL0, 1, CLK_IGNORE_UNUSED},
  127. { CLKID_AHB_RAM, "ram", "ahb_div",
  128. HW_AHBCLKCTRL0, 2, CLK_IGNORE_UNUSED},
  129. { CLKID_AHB_GPIO, "gpio", "ahb_div",
  130. HW_AHBCLKCTRL0, 4 },
  131. { CLKID_AHB_MAC, "mac", "ahb_div",
  132. HW_AHBCLKCTRL0, 5 },
  133. { CLKID_AHB_EMI, "emi", "ahb_div",
  134. HW_AHBCLKCTRL0, 6, CLK_IGNORE_UNUSED},
  135. { CLKID_AHB_USB0, "usb0", "ahb_div",
  136. HW_AHBCLKCTRL0, 7 },
  137. { CLKID_AHB_USB1, "usb1", "ahb_div",
  138. HW_AHBCLKCTRL0, 8 },
  139. { CLKID_AHB_DMA0, "dma0", "ahb_div",
  140. HW_AHBCLKCTRL0, 9 },
  141. { CLKID_AHB_DMA1, "dma1", "ahb_div",
  142. HW_AHBCLKCTRL0, 10 },
  143. { CLKID_AHB_UART0, "uart0", "ahb_div",
  144. HW_AHBCLKCTRL0, 11 },
  145. { CLKID_AHB_UART1, "uart1", "ahb_div",
  146. HW_AHBCLKCTRL0, 12 },
  147. { CLKID_AHB_UART2, "uart2", "ahb_div",
  148. HW_AHBCLKCTRL0, 13 },
  149. { CLKID_AHB_UART3, "uart3", "ahb_div",
  150. HW_AHBCLKCTRL0, 14 },
  151. { CLKID_AHB_UART4, "uart4", "ahb_div",
  152. HW_AHBCLKCTRL0, 15 },
  153. { CLKID_AHB_UART5, "uart5", "ahb_div",
  154. HW_AHBCLKCTRL0, 16 },
  155. { CLKID_AHB_UART6, "uart6", "ahb_div",
  156. HW_AHBCLKCTRL0, 17 },
  157. { CLKID_AHB_UART7, "uart7", "ahb_div",
  158. HW_AHBCLKCTRL0, 18 },
  159. { CLKID_AHB_UART8, "uart8", "ahb_div",
  160. HW_AHBCLKCTRL0, 19 },
  161. { CLKID_AHB_UART9, "uart9", "ahb_div",
  162. HW_AHBCLKCTRL0, 20 },
  163. { CLKID_AHB_I2S0, "i2s0", "ahb_div",
  164. HW_AHBCLKCTRL0, 21 },
  165. { CLKID_AHB_I2C0, "i2c0", "ahb_div",
  166. HW_AHBCLKCTRL0, 22 },
  167. { CLKID_AHB_I2C1, "i2c1", "ahb_div",
  168. HW_AHBCLKCTRL0, 23 },
  169. { CLKID_AHB_SSP0, "ssp0", "ahb_div",
  170. HW_AHBCLKCTRL0, 24 },
  171. { CLKID_AHB_IOCONFIG, "ioconf", "ahb_div",
  172. HW_AHBCLKCTRL0, 25 },
  173. { CLKID_AHB_WDT, "wdt", "ahb_div",
  174. HW_AHBCLKCTRL0, 26 },
  175. { CLKID_AHB_CAN0, "can0", "ahb_div",
  176. HW_AHBCLKCTRL0, 27 },
  177. { CLKID_AHB_CAN1, "can1", "ahb_div",
  178. HW_AHBCLKCTRL0, 28 },
  179. { CLKID_AHB_MPWM, "mpwm", "ahb_div",
  180. HW_AHBCLKCTRL0, 29 },
  181. { CLKID_AHB_SPI0, "spi0", "ahb_div",
  182. HW_AHBCLKCTRL0, 30 },
  183. { CLKID_AHB_SPI1, "spi1", "ahb_div",
  184. HW_AHBCLKCTRL0, 31 },
  185. { CLKID_AHB_QEI, "qei", "ahb_div",
  186. HW_AHBCLKCTRL1, 0 },
  187. { CLKID_AHB_QUADSPI0, "quadspi0", "ahb_div",
  188. HW_AHBCLKCTRL1, 1 },
  189. { CLKID_AHB_CAMIF, "capmif", "ahb_div",
  190. HW_AHBCLKCTRL1, 2 },
  191. { CLKID_AHB_LCDIF, "lcdif", "ahb_div",
  192. HW_AHBCLKCTRL1, 3 },
  193. { CLKID_AHB_TIMER0, "timer0", "ahb_div",
  194. HW_AHBCLKCTRL1, 4 },
  195. { CLKID_AHB_TIMER1, "timer1", "ahb_div",
  196. HW_AHBCLKCTRL1, 5 },
  197. { CLKID_AHB_TIMER2, "timer2", "ahb_div",
  198. HW_AHBCLKCTRL1, 6 },
  199. { CLKID_AHB_TIMER3, "timer3", "ahb_div",
  200. HW_AHBCLKCTRL1, 7 },
  201. { CLKID_AHB_IRQ, "irq", "ahb_div",
  202. HW_AHBCLKCTRL1, 8, CLK_IGNORE_UNUSED},
  203. { CLKID_AHB_RTC, "rtc", "ahb_div",
  204. HW_AHBCLKCTRL1, 9 },
  205. { CLKID_AHB_NAND, "nand", "ahb_div",
  206. HW_AHBCLKCTRL1, 10 },
  207. { CLKID_AHB_ADC0, "adc0", "ahb_div",
  208. HW_AHBCLKCTRL1, 11 },
  209. { CLKID_AHB_LED, "led", "ahb_div",
  210. HW_AHBCLKCTRL1, 12 },
  211. { CLKID_AHB_DAC0, "dac0", "ahb_div",
  212. HW_AHBCLKCTRL1, 13 },
  213. { CLKID_AHB_LCD, "lcd", "ahb_div",
  214. HW_AHBCLKCTRL1, 14 },
  215. { CLKID_AHB_I2S1, "i2s1", "ahb_div",
  216. HW_AHBCLKCTRL1, 15 },
  217. { CLKID_AHB_MAC1, "mac1", "ahb_div",
  218. HW_AHBCLKCTRL1, 16 },
  219. };
  220. static const char __initdata *main_mux_p[] = { NULL, NULL };
  221. static const char __initdata *i2s0_mux_p[] = { NULL, NULL, "i2s0m_div"};
  222. static const char __initdata *i2s1_mux_p[] = { NULL, NULL, "i2s1m_div"};
  223. static const char __initdata *clkout_mux_p[] = { NULL, NULL, "rtc"};
  224. static u32 three_mux_table[] = {0, 1, 3};
  225. static struct asm9260_mux_clock asm9260_mux_clks[] __initdata = {
  226. { 1, three_mux_table, "main_mux", main_mux_p,
  227. ARRAY_SIZE(main_mux_p), HW_MAINCLKSEL, },
  228. { 1, three_mux_table, "uart_mux", main_mux_p,
  229. ARRAY_SIZE(main_mux_p), HW_UARTCLKSEL, },
  230. { 1, three_mux_table, "wdt_mux", main_mux_p,
  231. ARRAY_SIZE(main_mux_p), HW_WDTCLKSEL, },
  232. { 3, three_mux_table, "i2s0_mux", i2s0_mux_p,
  233. ARRAY_SIZE(i2s0_mux_p), HW_I2S0CLKSEL, },
  234. { 3, three_mux_table, "i2s1_mux", i2s1_mux_p,
  235. ARRAY_SIZE(i2s1_mux_p), HW_I2S1CLKSEL, },
  236. { 3, three_mux_table, "clkout_mux", clkout_mux_p,
  237. ARRAY_SIZE(clkout_mux_p), HW_CLKOUTCLKSEL, },
  238. };
  239. static void __init asm9260_acc_init(struct device_node *np)
  240. {
  241. struct clk_hw *hw;
  242. struct clk_hw **hws;
  243. const char *ref_clk, *pll_clk = "pll";
  244. u32 rate;
  245. int n;
  246. clk_data = kzalloc(struct_size(clk_data, hws, MAX_CLKS), GFP_KERNEL);
  247. if (!clk_data)
  248. return;
  249. clk_data->num = MAX_CLKS;
  250. hws = clk_data->hws;
  251. base = of_io_request_and_map(np, 0, np->name);
  252. if (IS_ERR(base))
  253. panic("%pOFn: unable to map resource", np);
  254. /* register pll */
  255. rate = (ioread32(base + HW_SYSPLLCTRL) & 0xffff) * 1000000;
  256. /* TODO: Convert to DT parent scheme */
  257. ref_clk = of_clk_get_parent_name(np, 0);
  258. hw = __clk_hw_register_fixed_rate(NULL, NULL, pll_clk,
  259. ref_clk, NULL, NULL, 0, rate, 0,
  260. CLK_FIXED_RATE_PARENT_ACCURACY);
  261. if (IS_ERR(hw))
  262. panic("%pOFn: can't register REFCLK. Check DT!", np);
  263. for (n = 0; n < ARRAY_SIZE(asm9260_mux_clks); n++) {
  264. const struct asm9260_mux_clock *mc = &asm9260_mux_clks[n];
  265. mc->parent_names[0] = ref_clk;
  266. mc->parent_names[1] = pll_clk;
  267. hw = clk_hw_register_mux_table(NULL, mc->name, mc->parent_names,
  268. mc->num_parents, mc->flags, base + mc->offset,
  269. 0, mc->mask, 0, mc->table, &asm9260_clk_lock);
  270. }
  271. /* clock mux gate cells */
  272. for (n = 0; n < ARRAY_SIZE(asm9260_mux_gates); n++) {
  273. const struct asm9260_gate_data *gd = &asm9260_mux_gates[n];
  274. hw = clk_hw_register_gate(NULL, gd->name,
  275. gd->parent_name, gd->flags | CLK_SET_RATE_PARENT,
  276. base + gd->reg, gd->bit_idx, 0, &asm9260_clk_lock);
  277. }
  278. /* clock div cells */
  279. for (n = 0; n < ARRAY_SIZE(asm9260_div_clks); n++) {
  280. const struct asm9260_div_clk *dc = &asm9260_div_clks[n];
  281. hws[dc->idx] = clk_hw_register_divider(NULL, dc->name,
  282. dc->parent_name, CLK_SET_RATE_PARENT,
  283. base + dc->reg, 0, 8, CLK_DIVIDER_ONE_BASED,
  284. &asm9260_clk_lock);
  285. }
  286. /* clock ahb gate cells */
  287. for (n = 0; n < ARRAY_SIZE(asm9260_ahb_gates); n++) {
  288. const struct asm9260_gate_data *gd = &asm9260_ahb_gates[n];
  289. hws[gd->idx] = clk_hw_register_gate(NULL, gd->name,
  290. gd->parent_name, gd->flags, base + gd->reg,
  291. gd->bit_idx, 0, &asm9260_clk_lock);
  292. }
  293. /* check for errors on leaf clocks */
  294. for (n = 0; n < MAX_CLKS; n++) {
  295. if (!IS_ERR(hws[n]))
  296. continue;
  297. pr_err("%pOF: Unable to register leaf clock %d\n",
  298. np, n);
  299. goto fail;
  300. }
  301. /* register clk-provider */
  302. of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
  303. return;
  304. fail:
  305. iounmap(base);
  306. }
  307. CLK_OF_DECLARE(asm9260_acc, "alphascale,asm9260-clock-controller",
  308. asm9260_acc_init);