owl-s700.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Actions Semi S700 clock driver
  4. *
  5. * Copyright (c) 2014 Actions Semi Inc.
  6. * Author: David Liu <liuwei@actions-semi.com>
  7. *
  8. * Author: Pathiban Nallathambi <pn@denx.de>
  9. * Author: Saravanan Sekar <sravanhome@gmail.com>
  10. */
  11. #include <linux/clk-provider.h>
  12. #include <linux/platform_device.h>
  13. #include "owl-common.h"
  14. #include "owl-composite.h"
  15. #include "owl-divider.h"
  16. #include "owl-factor.h"
  17. #include "owl-fixed-factor.h"
  18. #include "owl-gate.h"
  19. #include "owl-mux.h"
  20. #include "owl-pll.h"
  21. #include "owl-reset.h"
  22. #include <dt-bindings/clock/actions,s700-cmu.h>
  23. #include <dt-bindings/reset/actions,s700-reset.h>
  24. #define CMU_COREPLL (0x0000)
  25. #define CMU_DEVPLL (0x0004)
  26. #define CMU_DDRPLL (0x0008)
  27. #define CMU_NANDPLL (0x000C)
  28. #define CMU_DISPLAYPLL (0x0010)
  29. #define CMU_AUDIOPLL (0x0014)
  30. #define CMU_TVOUTPLL (0x0018)
  31. #define CMU_BUSCLK (0x001C)
  32. #define CMU_SENSORCLK (0x0020)
  33. #define CMU_LCDCLK (0x0024)
  34. #define CMU_DSIPLLCLK (0x0028)
  35. #define CMU_CSICLK (0x002C)
  36. #define CMU_DECLK (0x0030)
  37. #define CMU_SICLK (0x0034)
  38. #define CMU_BUSCLK1 (0x0038)
  39. #define CMU_HDECLK (0x003C)
  40. #define CMU_VDECLK (0x0040)
  41. #define CMU_VCECLK (0x0044)
  42. #define CMU_NANDCCLK (0x004C)
  43. #define CMU_SD0CLK (0x0050)
  44. #define CMU_SD1CLK (0x0054)
  45. #define CMU_SD2CLK (0x0058)
  46. #define CMU_UART0CLK (0x005C)
  47. #define CMU_UART1CLK (0x0060)
  48. #define CMU_UART2CLK (0x0064)
  49. #define CMU_UART3CLK (0x0068)
  50. #define CMU_UART4CLK (0x006C)
  51. #define CMU_UART5CLK (0x0070)
  52. #define CMU_UART6CLK (0x0074)
  53. #define CMU_PWM0CLK (0x0078)
  54. #define CMU_PWM1CLK (0x007C)
  55. #define CMU_PWM2CLK (0x0080)
  56. #define CMU_PWM3CLK (0x0084)
  57. #define CMU_PWM4CLK (0x0088)
  58. #define CMU_PWM5CLK (0x008C)
  59. #define CMU_GPU3DCLK (0x0090)
  60. #define CMU_CORECTL (0x009C)
  61. #define CMU_DEVCLKEN0 (0x00A0)
  62. #define CMU_DEVCLKEN1 (0x00A4)
  63. #define CMU_DEVRST0 (0x00A8)
  64. #define CMU_DEVRST1 (0x00AC)
  65. #define CMU_USBPLL (0x00B0)
  66. #define CMU_ETHERNETPLL (0x00B4)
  67. #define CMU_CVBSPLL (0x00B8)
  68. #define CMU_SSTSCLK (0x00C0)
  69. static struct clk_pll_table clk_audio_pll_table[] = {
  70. {0, 45158400}, {1, 49152000},
  71. {0, 0},
  72. };
  73. static struct clk_pll_table clk_cvbs_pll_table[] = {
  74. {27, 29 * 12000000}, {28, 30 * 12000000}, {29, 31 * 12000000},
  75. {30, 32 * 12000000}, {31, 33 * 12000000}, {32, 34 * 12000000},
  76. {33, 35 * 12000000}, {34, 36 * 12000000}, {35, 37 * 12000000},
  77. {36, 38 * 12000000}, {37, 39 * 12000000}, {38, 40 * 12000000},
  78. {39, 41 * 12000000}, {40, 42 * 12000000}, {41, 43 * 12000000},
  79. {42, 44 * 12000000}, {43, 45 * 12000000}, {0, 0},
  80. };
  81. /* pll clocks */
  82. static OWL_PLL_NO_PARENT(clk_core_pll, "core_pll", CMU_COREPLL, 12000000, 9, 0, 8, 4, 174, NULL, CLK_IGNORE_UNUSED);
  83. static OWL_PLL_NO_PARENT(clk_dev_pll, "dev_pll", CMU_DEVPLL, 6000000, 8, 0, 8, 8, 126, NULL, CLK_IGNORE_UNUSED);
  84. static OWL_PLL_NO_PARENT(clk_ddr_pll, "ddr_pll", CMU_DDRPLL, 6000000, 8, 0, 8, 2, 180, NULL, CLK_IGNORE_UNUSED);
  85. static OWL_PLL_NO_PARENT(clk_nand_pll, "nand_pll", CMU_NANDPLL, 6000000, 8, 0, 8, 2, 86, NULL, CLK_IGNORE_UNUSED);
  86. static OWL_PLL_NO_PARENT(clk_display_pll, "display_pll", CMU_DISPLAYPLL, 6000000, 8, 0, 8, 2, 140, NULL, CLK_IGNORE_UNUSED);
  87. static OWL_PLL_NO_PARENT(clk_cvbs_pll, "cvbs_pll", CMU_CVBSPLL, 0, 8, 0, 8, 27, 43, clk_cvbs_pll_table, CLK_IGNORE_UNUSED);
  88. static OWL_PLL_NO_PARENT(clk_audio_pll, "audio_pll", CMU_AUDIOPLL, 0, 4, 0, 1, 0, 0, clk_audio_pll_table, CLK_IGNORE_UNUSED);
  89. static OWL_PLL_NO_PARENT(clk_ethernet_pll, "ethernet_pll", CMU_ETHERNETPLL, 500000000, 0, 0, 0, 0, 0, NULL, CLK_IGNORE_UNUSED);
  90. static const char *cpu_clk_mux_p[] = {"losc", "hosc", "core_pll", "noc1_clk_div"};
  91. static const char *dev_clk_p[] = { "hosc", "dev_pll"};
  92. static const char *noc_clk_mux_p[] = { "dev_clk", "display_pll", "nand_pll", "ddr_pll", "cvbs_pll"};
  93. static const char *csi_clk_mux_p[] = { "display_pll", "dev_clk"};
  94. static const char *de_clk_mux_p[] = { "display_pll", "dev_clk"};
  95. static const char *hde_clk_mux_p[] = { "dev_clk", "display_pll", "nand_pll", "ddr_pll"};
  96. static const char *nand_clk_mux_p[] = { "nand_pll", "display_pll", "dev_clk", "ddr_pll"};
  97. static const char *sd_clk_mux_p[] = { "dev_clk", "nand_pll", };
  98. static const char *uart_clk_mux_p[] = { "hosc", "dev_pll"};
  99. static const char *pwm_clk_mux_p[] = { "losc", "hosc"};
  100. static const char *gpu_clk_mux_p[] = { "dev_clk", "display_pll", "nand_pll", "ddr_clk", "cvbs_pll"};
  101. static const char *lcd_clk_mux_p[] = { "display_pll", "dev_clk" };
  102. static const char *i2s_clk_mux_p[] = { "audio_pll" };
  103. static const char *sensor_clk_mux_p[] = { "hosc", "si"};
  104. /* mux clocks */
  105. static OWL_MUX(clk_cpu, "cpu_clk", cpu_clk_mux_p, CMU_BUSCLK, 0, 2, CLK_SET_RATE_PARENT);
  106. static OWL_MUX(clk_dev, "dev_clk", dev_clk_p, CMU_DEVPLL, 12, 1, CLK_SET_RATE_PARENT);
  107. static OWL_MUX(clk_noc0_clk_mux, "noc0_clk_mux", noc_clk_mux_p, CMU_BUSCLK, 4, 3, CLK_SET_RATE_PARENT);
  108. static OWL_MUX(clk_noc1_clk_mux, "noc1_clk_mux", noc_clk_mux_p, CMU_BUSCLK1, 4, 3, CLK_SET_RATE_PARENT);
  109. static OWL_MUX(clk_hp_clk_mux, "hp_clk_mux", noc_clk_mux_p, CMU_BUSCLK1, 8, 3, CLK_SET_RATE_PARENT);
  110. static struct clk_factor_table sd_factor_table[] = {
  111. /* bit0 ~ 4 */
  112. {0, 1, 1}, {1, 1, 2}, {2, 1, 3}, {3, 1, 4},
  113. {4, 1, 5}, {5, 1, 6}, {6, 1, 7}, {7, 1, 8},
  114. {8, 1, 9}, {9, 1, 10}, {10, 1, 11}, {11, 1, 12},
  115. {12, 1, 13}, {13, 1, 14}, {14, 1, 15}, {15, 1, 16},
  116. {16, 1, 17}, {17, 1, 18}, {18, 1, 19}, {19, 1, 20},
  117. {20, 1, 21}, {21, 1, 22}, {22, 1, 23}, {23, 1, 24},
  118. {24, 1, 25}, {25, 1, 26},
  119. /* bit8: /128 */
  120. {256, 1, 1 * 128}, {257, 1, 2 * 128}, {258, 1, 3 * 128}, {259, 1, 4 * 128},
  121. {260, 1, 5 * 128}, {261, 1, 6 * 128}, {262, 1, 7 * 128}, {263, 1, 8 * 128},
  122. {264, 1, 9 * 128}, {265, 1, 10 * 128}, {266, 1, 11 * 128}, {267, 1, 12 * 128},
  123. {268, 1, 13 * 128}, {269, 1, 14 * 128}, {270, 1, 15 * 128}, {271, 1, 16 * 128},
  124. {272, 1, 17 * 128}, {273, 1, 18 * 128}, {274, 1, 19 * 128}, {275, 1, 20 * 128},
  125. {276, 1, 21 * 128}, {277, 1, 22 * 128}, {278, 1, 23 * 128}, {279, 1, 24 * 128},
  126. {280, 1, 25 * 128}, {281, 1, 26 * 128},
  127. {0, 0},
  128. };
  129. static struct clk_factor_table lcd_factor_table[] = {
  130. /* bit0 ~ 3 */
  131. {0, 1, 1}, {1, 1, 2}, {2, 1, 3}, {3, 1, 4},
  132. {4, 1, 5}, {5, 1, 6}, {6, 1, 7}, {7, 1, 8},
  133. {8, 1, 9}, {9, 1, 10}, {10, 1, 11}, {11, 1, 12},
  134. /* bit8: /7 */
  135. {256, 1, 1 * 7}, {257, 1, 2 * 7}, {258, 1, 3 * 7}, {259, 1, 4 * 7},
  136. {260, 1, 5 * 7}, {261, 1, 6 * 7}, {262, 1, 7 * 7}, {263, 1, 8 * 7},
  137. {264, 1, 9 * 7}, {265, 1, 10 * 7}, {266, 1, 11 * 7}, {267, 1, 12 * 7},
  138. {0, 0},
  139. };
  140. static struct clk_div_table hdmia_div_table[] = {
  141. {0, 1}, {1, 2}, {2, 3}, {3, 4},
  142. {4, 6}, {5, 8}, {6, 12}, {7, 16},
  143. {8, 24},
  144. {0, 0},
  145. };
  146. static struct clk_div_table rmii_div_table[] = {
  147. {0, 4}, {1, 10},
  148. {0, 0}
  149. };
  150. /* divider clocks */
  151. static OWL_DIVIDER(clk_noc0, "noc0_clk", "noc0_clk_mux", CMU_BUSCLK, 16, 2, NULL, 0, 0);
  152. static OWL_DIVIDER(clk_noc1, "noc1_clk", "noc1_clk_mux", CMU_BUSCLK1, 16, 2, NULL, 0, 0);
  153. static OWL_DIVIDER(clk_noc1_clk_div, "noc1_clk_div", "noc1_clk", CMU_BUSCLK1, 20, 1, NULL, 0, 0);
  154. static OWL_DIVIDER(clk_hp_clk_div, "hp_clk_div", "hp_clk_mux", CMU_BUSCLK1, 12, 2, NULL, 0, 0);
  155. static OWL_DIVIDER(clk_ahb, "ahb_clk", "hp_clk_div", CMU_BUSCLK1, 2, 2, NULL, 0, 0);
  156. static OWL_DIVIDER(clk_apb, "apb_clk", "ahb_clk", CMU_BUSCLK1, 14, 2, NULL, 0, 0);
  157. static OWL_DIVIDER(clk_sensor0, "sensor0", "sensor_src", CMU_SENSORCLK, 0, 4, NULL, 0, 0);
  158. static OWL_DIVIDER(clk_sensor1, "sensor1", "sensor_src", CMU_SENSORCLK, 8, 4, NULL, 0, 0);
  159. static OWL_DIVIDER(clk_rmii_ref, "rmii_ref", "ethernet_pll", CMU_ETHERNETPLL, 2, 1, rmii_div_table, 0, 0);
  160. static struct clk_factor_table de_factor_table[] = {
  161. {0, 1, 1}, {1, 2, 3}, {2, 1, 2}, {3, 2, 5},
  162. {4, 1, 3}, {5, 1, 4}, {6, 1, 6}, {7, 1, 8},
  163. {8, 1, 12}, {0, 0, 0},
  164. };
  165. static struct clk_factor_table hde_factor_table[] = {
  166. {0, 1, 1}, {1, 2, 3}, {2, 1, 2}, {3, 2, 5},
  167. {4, 1, 3}, {5, 1, 4}, {6, 1, 6}, {7, 1, 8},
  168. {0, 0, 0},
  169. };
  170. /* gate clocks */
  171. static OWL_GATE(clk_gpio, "gpio", "apb_clk", CMU_DEVCLKEN1, 25, 0, 0);
  172. static OWL_GATE(clk_dmac, "dmac", "hp_clk_div", CMU_DEVCLKEN0, 17, 0, 0);
  173. static OWL_GATE(clk_timer, "timer", "hosc", CMU_DEVCLKEN1, 22, 0, 0);
  174. static OWL_GATE_NO_PARENT(clk_dsi, "dsi_clk", CMU_DEVCLKEN0, 2, 0, 0);
  175. static OWL_GATE_NO_PARENT(clk_tvout, "tvout_clk", CMU_DEVCLKEN0, 3, 0, 0);
  176. static OWL_GATE_NO_PARENT(clk_hdmi_dev, "hdmi_dev", CMU_DEVCLKEN0, 5, 0, 0);
  177. static OWL_GATE_NO_PARENT(clk_usb3_480mpll0, "usb3_480mpll0", CMU_USBPLL, 3, 0, 0);
  178. static OWL_GATE_NO_PARENT(clk_usb3_480mphy0, "usb3_480mphy0", CMU_USBPLL, 2, 0, 0);
  179. static OWL_GATE_NO_PARENT(clk_usb3_5gphy, "usb3_5gphy", CMU_USBPLL, 1, 0, 0);
  180. static OWL_GATE_NO_PARENT(clk_usb3_cce, "usb3_cce", CMU_DEVCLKEN0, 25, 0, 0);
  181. static OWL_GATE(clk_i2c0, "i2c0", "hosc", CMU_DEVCLKEN1, 0, 0, 0);
  182. static OWL_GATE(clk_i2c1, "i2c1", "hosc", CMU_DEVCLKEN1, 1, 0, 0);
  183. static OWL_GATE(clk_i2c2, "i2c2", "hosc", CMU_DEVCLKEN1, 2, 0, 0);
  184. static OWL_GATE(clk_i2c3, "i2c3", "hosc", CMU_DEVCLKEN1, 3, 0, 0);
  185. static OWL_GATE(clk_spi0, "spi0", "ahb_clk", CMU_DEVCLKEN1, 4, 0, 0);
  186. static OWL_GATE(clk_spi1, "spi1", "ahb_clk", CMU_DEVCLKEN1, 5, 0, 0);
  187. static OWL_GATE(clk_spi2, "spi2", "ahb_clk", CMU_DEVCLKEN1, 6, 0, 0);
  188. static OWL_GATE(clk_spi3, "spi3", "ahb_clk", CMU_DEVCLKEN1, 7, 0, 0);
  189. static OWL_GATE_NO_PARENT(clk_usb2h0_pllen, "usbh0_pllen", CMU_USBPLL, 12, 0, 0);
  190. static OWL_GATE_NO_PARENT(clk_usb2h0_phy, "usbh0_phy", CMU_USBPLL, 10, 0, 0);
  191. static OWL_GATE_NO_PARENT(clk_usb2h0_cce, "usbh0_cce", CMU_DEVCLKEN0, 26, 0, 0);
  192. static OWL_GATE_NO_PARENT(clk_usb2h1_pllen, "usbh1_pllen", CMU_USBPLL, 13, 0, 0);
  193. static OWL_GATE_NO_PARENT(clk_usb2h1_phy, "usbh1_phy", CMU_USBPLL, 11, 0, 0);
  194. static OWL_GATE_NO_PARENT(clk_usb2h1_cce, "usbh1_cce", CMU_DEVCLKEN0, 27, 0, 0);
  195. static OWL_GATE_NO_PARENT(clk_irc_switch, "irc_switch", CMU_DEVCLKEN1, 15, 0, 0);
  196. /* composite clocks */
  197. static OWL_COMP_DIV(clk_csi, "csi", csi_clk_mux_p,
  198. OWL_MUX_HW(CMU_CSICLK, 4, 1),
  199. OWL_GATE_HW(CMU_DEVCLKEN0, 13, 0),
  200. OWL_DIVIDER_HW(CMU_CSICLK, 0, 4, 0, NULL),
  201. 0);
  202. static OWL_COMP_DIV(clk_si, "si", csi_clk_mux_p,
  203. OWL_MUX_HW(CMU_SICLK, 4, 1),
  204. OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0),
  205. OWL_DIVIDER_HW(CMU_SICLK, 0, 4, 0, NULL),
  206. 0);
  207. static OWL_COMP_FACTOR(clk_de, "de", de_clk_mux_p,
  208. OWL_MUX_HW(CMU_DECLK, 12, 1),
  209. OWL_GATE_HW(CMU_DEVCLKEN0, 0, 0),
  210. OWL_FACTOR_HW(CMU_DECLK, 0, 3, 0, de_factor_table),
  211. 0);
  212. static OWL_COMP_FACTOR(clk_hde, "hde", hde_clk_mux_p,
  213. OWL_MUX_HW(CMU_HDECLK, 4, 2),
  214. OWL_GATE_HW(CMU_DEVCLKEN0, 9, 0),
  215. OWL_FACTOR_HW(CMU_HDECLK, 0, 3, 0, hde_factor_table),
  216. 0);
  217. static OWL_COMP_FACTOR(clk_vde, "vde", hde_clk_mux_p,
  218. OWL_MUX_HW(CMU_VDECLK, 4, 2),
  219. OWL_GATE_HW(CMU_DEVCLKEN0, 10, 0),
  220. OWL_FACTOR_HW(CMU_VDECLK, 0, 3, 0, hde_factor_table),
  221. 0);
  222. static OWL_COMP_FACTOR(clk_vce, "vce", hde_clk_mux_p,
  223. OWL_MUX_HW(CMU_VCECLK, 4, 2),
  224. OWL_GATE_HW(CMU_DEVCLKEN0, 11, 0),
  225. OWL_FACTOR_HW(CMU_VCECLK, 0, 3, 0, hde_factor_table),
  226. 0);
  227. static OWL_COMP_DIV(clk_nand, "nand", nand_clk_mux_p,
  228. OWL_MUX_HW(CMU_NANDCCLK, 8, 2),
  229. OWL_GATE_HW(CMU_DEVCLKEN0, 21, 0),
  230. OWL_DIVIDER_HW(CMU_NANDCCLK, 0, 3, 0, NULL),
  231. CLK_SET_RATE_PARENT);
  232. static OWL_COMP_FACTOR(clk_sd0, "sd0", sd_clk_mux_p,
  233. OWL_MUX_HW(CMU_SD0CLK, 9, 1),
  234. OWL_GATE_HW(CMU_DEVCLKEN0, 22, 0),
  235. OWL_FACTOR_HW(CMU_SD0CLK, 0, 9, 0, sd_factor_table),
  236. 0);
  237. static OWL_COMP_FACTOR(clk_sd1, "sd1", sd_clk_mux_p,
  238. OWL_MUX_HW(CMU_SD1CLK, 9, 1),
  239. OWL_GATE_HW(CMU_DEVCLKEN0, 23, 0),
  240. OWL_FACTOR_HW(CMU_SD1CLK, 0, 9, 0, sd_factor_table),
  241. 0);
  242. static OWL_COMP_FACTOR(clk_sd2, "sd2", sd_clk_mux_p,
  243. OWL_MUX_HW(CMU_SD2CLK, 9, 1),
  244. OWL_GATE_HW(CMU_DEVCLKEN0, 24, 0),
  245. OWL_FACTOR_HW(CMU_SD2CLK, 0, 9, 0, sd_factor_table),
  246. 0);
  247. static OWL_COMP_DIV(clk_uart0, "uart0", uart_clk_mux_p,
  248. OWL_MUX_HW(CMU_UART0CLK, 16, 1),
  249. OWL_GATE_HW(CMU_DEVCLKEN1, 8, 0),
  250. OWL_DIVIDER_HW(CMU_UART0CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
  251. 0);
  252. static OWL_COMP_DIV(clk_uart1, "uart1", uart_clk_mux_p,
  253. OWL_MUX_HW(CMU_UART1CLK, 16, 1),
  254. OWL_GATE_HW(CMU_DEVCLKEN1, 9, 0),
  255. OWL_DIVIDER_HW(CMU_UART1CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
  256. 0);
  257. static OWL_COMP_DIV(clk_uart2, "uart2", uart_clk_mux_p,
  258. OWL_MUX_HW(CMU_UART2CLK, 16, 1),
  259. OWL_GATE_HW(CMU_DEVCLKEN1, 10, 0),
  260. OWL_DIVIDER_HW(CMU_UART2CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
  261. 0);
  262. static OWL_COMP_DIV(clk_uart3, "uart3", uart_clk_mux_p,
  263. OWL_MUX_HW(CMU_UART3CLK, 16, 1),
  264. OWL_GATE_HW(CMU_DEVCLKEN1, 11, 0),
  265. OWL_DIVIDER_HW(CMU_UART3CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
  266. 0);
  267. static OWL_COMP_DIV(clk_uart4, "uart4", uart_clk_mux_p,
  268. OWL_MUX_HW(CMU_UART4CLK, 16, 1),
  269. OWL_GATE_HW(CMU_DEVCLKEN1, 12, 0),
  270. OWL_DIVIDER_HW(CMU_UART4CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
  271. 0);
  272. static OWL_COMP_DIV(clk_uart5, "uart5", uart_clk_mux_p,
  273. OWL_MUX_HW(CMU_UART5CLK, 16, 1),
  274. OWL_GATE_HW(CMU_DEVCLKEN1, 13, 0),
  275. OWL_DIVIDER_HW(CMU_UART5CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
  276. 0);
  277. static OWL_COMP_DIV(clk_uart6, "uart6", uart_clk_mux_p,
  278. OWL_MUX_HW(CMU_UART6CLK, 16, 1),
  279. OWL_GATE_HW(CMU_DEVCLKEN1, 14, 0),
  280. OWL_DIVIDER_HW(CMU_UART6CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
  281. 0);
  282. static OWL_COMP_DIV(clk_pwm0, "pwm0", pwm_clk_mux_p,
  283. OWL_MUX_HW(CMU_PWM0CLK, 12, 1),
  284. OWL_GATE_HW(CMU_DEVCLKEN1, 16, 0),
  285. OWL_DIVIDER_HW(CMU_PWM0CLK, 0, 10, 0, NULL),
  286. CLK_IGNORE_UNUSED);
  287. static OWL_COMP_DIV(clk_pwm1, "pwm1", pwm_clk_mux_p,
  288. OWL_MUX_HW(CMU_PWM1CLK, 12, 1),
  289. OWL_GATE_HW(CMU_DEVCLKEN1, 17, 0),
  290. OWL_DIVIDER_HW(CMU_PWM1CLK, 0, 10, 0, NULL),
  291. 0);
  292. static OWL_COMP_DIV(clk_pwm2, "pwm2", pwm_clk_mux_p,
  293. OWL_MUX_HW(CMU_PWM2CLK, 12, 1),
  294. OWL_GATE_HW(CMU_DEVCLKEN1, 18, 0),
  295. OWL_DIVIDER_HW(CMU_PWM2CLK, 0, 10, 0, NULL),
  296. 0);
  297. static OWL_COMP_DIV(clk_pwm3, "pwm3", pwm_clk_mux_p,
  298. OWL_MUX_HW(CMU_PWM3CLK, 12, 1),
  299. OWL_GATE_HW(CMU_DEVCLKEN1, 19, 0),
  300. OWL_DIVIDER_HW(CMU_PWM3CLK, 0, 10, 0, NULL),
  301. 0);
  302. static OWL_COMP_DIV(clk_pwm4, "pwm4", pwm_clk_mux_p,
  303. OWL_MUX_HW(CMU_PWM4CLK, 12, 1),
  304. OWL_GATE_HW(CMU_DEVCLKEN1, 20, 0),
  305. OWL_DIVIDER_HW(CMU_PWM4CLK, 0, 10, 0, NULL),
  306. 0);
  307. static OWL_COMP_DIV(clk_pwm5, "pwm5", pwm_clk_mux_p,
  308. OWL_MUX_HW(CMU_PWM5CLK, 12, 1),
  309. OWL_GATE_HW(CMU_DEVCLKEN1, 21, 0),
  310. OWL_DIVIDER_HW(CMU_PWM5CLK, 0, 10, 0, NULL),
  311. 0);
  312. static OWL_COMP_FACTOR(clk_gpu3d, "gpu3d", gpu_clk_mux_p,
  313. OWL_MUX_HW(CMU_GPU3DCLK, 4, 3),
  314. OWL_GATE_HW(CMU_DEVCLKEN0, 8, 0),
  315. OWL_FACTOR_HW(CMU_GPU3DCLK, 0, 3, 0, hde_factor_table),
  316. 0);
  317. static OWL_COMP_FACTOR(clk_lcd, "lcd", lcd_clk_mux_p,
  318. OWL_MUX_HW(CMU_LCDCLK, 12, 2),
  319. OWL_GATE_HW(CMU_DEVCLKEN0, 1, 0),
  320. OWL_FACTOR_HW(CMU_LCDCLK, 0, 9, 0, lcd_factor_table),
  321. 0);
  322. static OWL_COMP_DIV(clk_hdmi_audio, "hdmia", i2s_clk_mux_p,
  323. OWL_MUX_HW(CMU_AUDIOPLL, 24, 1), /*CMU_AUDIOPLL 24,1 unused*/
  324. OWL_GATE_HW(CMU_DEVCLKEN1, 28, 0),
  325. OWL_DIVIDER_HW(CMU_AUDIOPLL, 24, 4, 0, hdmia_div_table),
  326. 0);
  327. static OWL_COMP_DIV(clk_i2srx, "i2srx", i2s_clk_mux_p,
  328. OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
  329. OWL_GATE_HW(CMU_DEVCLKEN1, 27, 0),
  330. OWL_DIVIDER_HW(CMU_AUDIOPLL, 20, 4, 0, hdmia_div_table),
  331. 0);
  332. static OWL_COMP_DIV(clk_i2stx, "i2stx", i2s_clk_mux_p,
  333. OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
  334. OWL_GATE_HW(CMU_DEVCLKEN1, 26, 0),
  335. OWL_DIVIDER_HW(CMU_AUDIOPLL, 16, 4, 0, hdmia_div_table),
  336. 0);
  337. /* for bluetooth pcm communication */
  338. static OWL_COMP_FIXED_FACTOR(clk_pcm1, "pcm1", "audio_pll",
  339. OWL_GATE_HW(CMU_DEVCLKEN1, 31, 0),
  340. 1, 2, 0);
  341. static OWL_COMP_DIV(clk_sensor_src, "sensor_src", sensor_clk_mux_p,
  342. OWL_MUX_HW(CMU_SENSORCLK, 4, 1),
  343. {0},
  344. OWL_DIVIDER_HW(CMU_SENSORCLK, 5, 2, 0, NULL),
  345. 0);
  346. static OWL_COMP_FIXED_FACTOR(clk_ethernet, "ethernet", "ethernet_pll",
  347. OWL_GATE_HW(CMU_DEVCLKEN1, 23, 0),
  348. 1, 20, 0);
  349. static OWL_COMP_DIV_FIXED(clk_thermal_sensor, "thermal_sensor", "hosc",
  350. OWL_GATE_HW(CMU_DEVCLKEN0, 31, 0),
  351. OWL_DIVIDER_HW(CMU_SSTSCLK, 20, 10, 0, NULL),
  352. 0);
  353. static struct owl_clk_common *s700_clks[] = {
  354. &clk_core_pll.common,
  355. &clk_dev_pll.common,
  356. &clk_ddr_pll.common,
  357. &clk_nand_pll.common,
  358. &clk_display_pll.common,
  359. &clk_cvbs_pll .common,
  360. &clk_audio_pll.common,
  361. &clk_ethernet_pll.common,
  362. &clk_cpu.common,
  363. &clk_dev.common,
  364. &clk_ahb.common,
  365. &clk_apb.common,
  366. &clk_dmac.common,
  367. &clk_noc0_clk_mux.common,
  368. &clk_noc1_clk_mux.common,
  369. &clk_hp_clk_mux.common,
  370. &clk_hp_clk_div.common,
  371. &clk_noc1_clk_div.common,
  372. &clk_noc0.common,
  373. &clk_noc1.common,
  374. &clk_sensor_src.common,
  375. &clk_gpio.common,
  376. &clk_timer.common,
  377. &clk_dsi.common,
  378. &clk_csi.common,
  379. &clk_si.common,
  380. &clk_de.common,
  381. &clk_hde.common,
  382. &clk_vde.common,
  383. &clk_vce.common,
  384. &clk_nand.common,
  385. &clk_sd0.common,
  386. &clk_sd1.common,
  387. &clk_sd2.common,
  388. &clk_uart0.common,
  389. &clk_uart1.common,
  390. &clk_uart2.common,
  391. &clk_uart3.common,
  392. &clk_uart4.common,
  393. &clk_uart5.common,
  394. &clk_uart6.common,
  395. &clk_pwm0.common,
  396. &clk_pwm1.common,
  397. &clk_pwm2.common,
  398. &clk_pwm3.common,
  399. &clk_pwm4.common,
  400. &clk_pwm5.common,
  401. &clk_gpu3d.common,
  402. &clk_i2c0.common,
  403. &clk_i2c1.common,
  404. &clk_i2c2.common,
  405. &clk_i2c3.common,
  406. &clk_spi0.common,
  407. &clk_spi1.common,
  408. &clk_spi2.common,
  409. &clk_spi3.common,
  410. &clk_usb3_480mpll0.common,
  411. &clk_usb3_480mphy0.common,
  412. &clk_usb3_5gphy.common,
  413. &clk_usb3_cce.common,
  414. &clk_lcd.common,
  415. &clk_hdmi_audio.common,
  416. &clk_i2srx.common,
  417. &clk_i2stx.common,
  418. &clk_sensor0.common,
  419. &clk_sensor1.common,
  420. &clk_hdmi_dev.common,
  421. &clk_ethernet.common,
  422. &clk_rmii_ref.common,
  423. &clk_usb2h0_pllen.common,
  424. &clk_usb2h0_phy.common,
  425. &clk_usb2h0_cce.common,
  426. &clk_usb2h1_pllen.common,
  427. &clk_usb2h1_phy.common,
  428. &clk_usb2h1_cce.common,
  429. &clk_tvout.common,
  430. &clk_thermal_sensor.common,
  431. &clk_irc_switch.common,
  432. &clk_pcm1.common,
  433. };
  434. static struct clk_hw_onecell_data s700_hw_clks = {
  435. .hws = {
  436. [CLK_CORE_PLL] = &clk_core_pll.common.hw,
  437. [CLK_DEV_PLL] = &clk_dev_pll.common.hw,
  438. [CLK_DDR_PLL] = &clk_ddr_pll.common.hw,
  439. [CLK_NAND_PLL] = &clk_nand_pll.common.hw,
  440. [CLK_DISPLAY_PLL] = &clk_display_pll.common.hw,
  441. [CLK_CVBS_PLL] = &clk_cvbs_pll .common.hw,
  442. [CLK_AUDIO_PLL] = &clk_audio_pll.common.hw,
  443. [CLK_ETHERNET_PLL] = &clk_ethernet_pll.common.hw,
  444. [CLK_CPU] = &clk_cpu.common.hw,
  445. [CLK_DEV] = &clk_dev.common.hw,
  446. [CLK_AHB] = &clk_ahb.common.hw,
  447. [CLK_APB] = &clk_apb.common.hw,
  448. [CLK_DMAC] = &clk_dmac.common.hw,
  449. [CLK_NOC0_CLK_MUX] = &clk_noc0_clk_mux.common.hw,
  450. [CLK_NOC1_CLK_MUX] = &clk_noc1_clk_mux.common.hw,
  451. [CLK_HP_CLK_MUX] = &clk_hp_clk_mux.common.hw,
  452. [CLK_HP_CLK_DIV] = &clk_hp_clk_div.common.hw,
  453. [CLK_NOC1_CLK_DIV] = &clk_noc1_clk_div.common.hw,
  454. [CLK_NOC0] = &clk_noc0.common.hw,
  455. [CLK_NOC1] = &clk_noc1.common.hw,
  456. [CLK_SENOR_SRC] = &clk_sensor_src.common.hw,
  457. [CLK_GPIO] = &clk_gpio.common.hw,
  458. [CLK_TIMER] = &clk_timer.common.hw,
  459. [CLK_DSI] = &clk_dsi.common.hw,
  460. [CLK_CSI] = &clk_csi.common.hw,
  461. [CLK_SI] = &clk_si.common.hw,
  462. [CLK_DE] = &clk_de.common.hw,
  463. [CLK_HDE] = &clk_hde.common.hw,
  464. [CLK_VDE] = &clk_vde.common.hw,
  465. [CLK_VCE] = &clk_vce.common.hw,
  466. [CLK_NAND] = &clk_nand.common.hw,
  467. [CLK_SD0] = &clk_sd0.common.hw,
  468. [CLK_SD1] = &clk_sd1.common.hw,
  469. [CLK_SD2] = &clk_sd2.common.hw,
  470. [CLK_UART0] = &clk_uart0.common.hw,
  471. [CLK_UART1] = &clk_uart1.common.hw,
  472. [CLK_UART2] = &clk_uart2.common.hw,
  473. [CLK_UART3] = &clk_uart3.common.hw,
  474. [CLK_UART4] = &clk_uart4.common.hw,
  475. [CLK_UART5] = &clk_uart5.common.hw,
  476. [CLK_UART6] = &clk_uart6.common.hw,
  477. [CLK_PWM0] = &clk_pwm0.common.hw,
  478. [CLK_PWM1] = &clk_pwm1.common.hw,
  479. [CLK_PWM2] = &clk_pwm2.common.hw,
  480. [CLK_PWM3] = &clk_pwm3.common.hw,
  481. [CLK_PWM4] = &clk_pwm4.common.hw,
  482. [CLK_PWM5] = &clk_pwm5.common.hw,
  483. [CLK_GPU3D] = &clk_gpu3d.common.hw,
  484. [CLK_I2C0] = &clk_i2c0.common.hw,
  485. [CLK_I2C1] = &clk_i2c1.common.hw,
  486. [CLK_I2C2] = &clk_i2c2.common.hw,
  487. [CLK_I2C3] = &clk_i2c3.common.hw,
  488. [CLK_SPI0] = &clk_spi0.common.hw,
  489. [CLK_SPI1] = &clk_spi1.common.hw,
  490. [CLK_SPI2] = &clk_spi2.common.hw,
  491. [CLK_SPI3] = &clk_spi3.common.hw,
  492. [CLK_USB3_480MPLL0] = &clk_usb3_480mpll0.common.hw,
  493. [CLK_USB3_480MPHY0] = &clk_usb3_480mphy0.common.hw,
  494. [CLK_USB3_5GPHY] = &clk_usb3_5gphy.common.hw,
  495. [CLK_USB3_CCE] = &clk_usb3_cce.common.hw,
  496. [CLK_LCD] = &clk_lcd.common.hw,
  497. [CLK_HDMI_AUDIO] = &clk_hdmi_audio.common.hw,
  498. [CLK_I2SRX] = &clk_i2srx.common.hw,
  499. [CLK_I2STX] = &clk_i2stx.common.hw,
  500. [CLK_SENSOR0] = &clk_sensor0.common.hw,
  501. [CLK_SENSOR1] = &clk_sensor1.common.hw,
  502. [CLK_HDMI_DEV] = &clk_hdmi_dev.common.hw,
  503. [CLK_ETHERNET] = &clk_ethernet.common.hw,
  504. [CLK_RMII_REF] = &clk_rmii_ref.common.hw,
  505. [CLK_USB2H0_PLLEN] = &clk_usb2h0_pllen.common.hw,
  506. [CLK_USB2H0_PHY] = &clk_usb2h0_phy.common.hw,
  507. [CLK_USB2H0_CCE] = &clk_usb2h0_cce.common.hw,
  508. [CLK_USB2H1_PLLEN] = &clk_usb2h1_pllen.common.hw,
  509. [CLK_USB2H1_PHY] = &clk_usb2h1_phy.common.hw,
  510. [CLK_USB2H1_CCE] = &clk_usb2h1_cce.common.hw,
  511. [CLK_TVOUT] = &clk_tvout.common.hw,
  512. [CLK_THERMAL_SENSOR] = &clk_thermal_sensor.common.hw,
  513. [CLK_IRC_SWITCH] = &clk_irc_switch.common.hw,
  514. [CLK_PCM1] = &clk_pcm1.common.hw,
  515. },
  516. .num = CLK_NR_CLKS,
  517. };
  518. static const struct owl_reset_map s700_resets[] = {
  519. [RESET_DE] = { CMU_DEVRST0, BIT(0) },
  520. [RESET_LCD0] = { CMU_DEVRST0, BIT(1) },
  521. [RESET_DSI] = { CMU_DEVRST0, BIT(2) },
  522. [RESET_CSI] = { CMU_DEVRST0, BIT(13) },
  523. [RESET_SI] = { CMU_DEVRST0, BIT(14) },
  524. [RESET_I2C0] = { CMU_DEVRST1, BIT(0) },
  525. [RESET_I2C1] = { CMU_DEVRST1, BIT(1) },
  526. [RESET_I2C2] = { CMU_DEVRST1, BIT(2) },
  527. [RESET_I2C3] = { CMU_DEVRST1, BIT(3) },
  528. [RESET_SPI0] = { CMU_DEVRST1, BIT(4) },
  529. [RESET_SPI1] = { CMU_DEVRST1, BIT(5) },
  530. [RESET_SPI2] = { CMU_DEVRST1, BIT(6) },
  531. [RESET_SPI3] = { CMU_DEVRST1, BIT(7) },
  532. [RESET_UART0] = { CMU_DEVRST1, BIT(8) },
  533. [RESET_UART1] = { CMU_DEVRST1, BIT(9) },
  534. [RESET_UART2] = { CMU_DEVRST1, BIT(10) },
  535. [RESET_UART3] = { CMU_DEVRST1, BIT(11) },
  536. [RESET_UART4] = { CMU_DEVRST1, BIT(12) },
  537. [RESET_UART5] = { CMU_DEVRST1, BIT(13) },
  538. [RESET_UART6] = { CMU_DEVRST1, BIT(14) },
  539. [RESET_KEY] = { CMU_DEVRST1, BIT(24) },
  540. [RESET_GPIO] = { CMU_DEVRST1, BIT(25) },
  541. [RESET_AUDIO] = { CMU_DEVRST1, BIT(29) },
  542. };
  543. static struct owl_clk_desc s700_clk_desc = {
  544. .clks = s700_clks,
  545. .num_clks = ARRAY_SIZE(s700_clks),
  546. .hw_clks = &s700_hw_clks,
  547. .resets = s700_resets,
  548. .num_resets = ARRAY_SIZE(s700_resets),
  549. };
  550. static int s700_clk_probe(struct platform_device *pdev)
  551. {
  552. struct owl_clk_desc *desc;
  553. struct owl_reset *reset;
  554. int ret;
  555. desc = &s700_clk_desc;
  556. owl_clk_regmap_init(pdev, desc);
  557. /*
  558. * FIXME: Reset controller registration should be moved to
  559. * common code, once all SoCs of Owl family supports it.
  560. */
  561. reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL);
  562. if (!reset)
  563. return -ENOMEM;
  564. reset->rcdev.of_node = pdev->dev.of_node;
  565. reset->rcdev.ops = &owl_reset_ops;
  566. reset->rcdev.nr_resets = desc->num_resets;
  567. reset->reset_map = desc->resets;
  568. reset->regmap = desc->regmap;
  569. ret = devm_reset_controller_register(&pdev->dev, &reset->rcdev);
  570. if (ret)
  571. dev_err(&pdev->dev, "Failed to register reset controller\n");
  572. return owl_clk_probe(&pdev->dev, desc->hw_clks);
  573. }
  574. static const struct of_device_id s700_clk_of_match[] = {
  575. { .compatible = "actions,s700-cmu", },
  576. { /* sentinel */ }
  577. };
  578. static struct platform_driver s700_clk_driver = {
  579. .probe = s700_clk_probe,
  580. .driver = {
  581. .name = "s700-cmu",
  582. .of_match_table = s700_clk_of_match
  583. },
  584. };
  585. static int __init s700_clk_init(void)
  586. {
  587. return platform_driver_register(&s700_clk_driver);
  588. }
  589. core_initcall(s700_clk_init);