owl-s500.c 21 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Actions Semi Owl S500 SoC clock driver
  4. *
  5. * Copyright (c) 2014 Actions Semi Inc.
  6. * Author: David Liu <liuwei@actions-semi.com>
  7. *
  8. * Copyright (c) 2018 Linaro Ltd.
  9. * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
  10. *
  11. * Copyright (c) 2018 LSI-TEC - Caninos Loucos
  12. * Author: Edgar Bernardi Righi <edgar.righi@lsitec.org.br>
  13. */
  14. #include <linux/clk-provider.h>
  15. #include <linux/platform_device.h>
  16. #include "owl-common.h"
  17. #include "owl-composite.h"
  18. #include "owl-divider.h"
  19. #include "owl-factor.h"
  20. #include "owl-fixed-factor.h"
  21. #include "owl-gate.h"
  22. #include "owl-mux.h"
  23. #include "owl-pll.h"
  24. #include "owl-reset.h"
  25. #include <dt-bindings/clock/actions,s500-cmu.h>
  26. #include <dt-bindings/reset/actions,s500-reset.h>
  27. #define CMU_COREPLL (0x0000)
  28. #define CMU_DEVPLL (0x0004)
  29. #define CMU_DDRPLL (0x0008)
  30. #define CMU_NANDPLL (0x000C)
  31. #define CMU_DISPLAYPLL (0x0010)
  32. #define CMU_AUDIOPLL (0x0014)
  33. #define CMU_TVOUTPLL (0x0018)
  34. #define CMU_BUSCLK (0x001C)
  35. #define CMU_SENSORCLK (0x0020)
  36. #define CMU_LCDCLK (0x0024)
  37. #define CMU_DSICLK (0x0028)
  38. #define CMU_CSICLK (0x002C)
  39. #define CMU_DECLK (0x0030)
  40. #define CMU_BISPCLK (0x0034)
  41. #define CMU_BUSCLK1 (0x0038)
  42. #define CMU_VDECLK (0x0040)
  43. #define CMU_VCECLK (0x0044)
  44. #define CMU_NANDCCLK (0x004C)
  45. #define CMU_SD0CLK (0x0050)
  46. #define CMU_SD1CLK (0x0054)
  47. #define CMU_SD2CLK (0x0058)
  48. #define CMU_UART0CLK (0x005C)
  49. #define CMU_UART1CLK (0x0060)
  50. #define CMU_UART2CLK (0x0064)
  51. #define CMU_PWM4CLK (0x0068)
  52. #define CMU_PWM5CLK (0x006C)
  53. #define CMU_PWM0CLK (0x0070)
  54. #define CMU_PWM1CLK (0x0074)
  55. #define CMU_PWM2CLK (0x0078)
  56. #define CMU_PWM3CLK (0x007C)
  57. #define CMU_USBPLL (0x0080)
  58. #define CMU_ETHERNETPLL (0x0084)
  59. #define CMU_CVBSPLL (0x0088)
  60. #define CMU_LENSCLK (0x008C)
  61. #define CMU_GPU3DCLK (0x0090)
  62. #define CMU_CORECTL (0x009C)
  63. #define CMU_DEVCLKEN0 (0x00A0)
  64. #define CMU_DEVCLKEN1 (0x00A4)
  65. #define CMU_DEVRST0 (0x00A8)
  66. #define CMU_DEVRST1 (0x00AC)
  67. #define CMU_UART3CLK (0x00B0)
  68. #define CMU_UART4CLK (0x00B4)
  69. #define CMU_UART5CLK (0x00B8)
  70. #define CMU_UART6CLK (0x00BC)
  71. #define CMU_SSCLK (0x00C0)
  72. #define CMU_DIGITALDEBUG (0x00D0)
  73. #define CMU_ANALOGDEBUG (0x00D4)
  74. #define CMU_COREPLLDEBUG (0x00D8)
  75. #define CMU_DEVPLLDEBUG (0x00DC)
  76. #define CMU_DDRPLLDEBUG (0x00E0)
  77. #define CMU_NANDPLLDEBUG (0x00E4)
  78. #define CMU_DISPLAYPLLDEBUG (0x00E8)
  79. #define CMU_TVOUTPLLDEBUG (0x00EC)
  80. #define CMU_DEEPCOLORPLLDEBUG (0x00F4)
  81. #define CMU_AUDIOPLL_ETHPLLDEBUG (0x00F8)
  82. #define CMU_CVBSPLLDEBUG (0x00FC)
  83. #define OWL_S500_COREPLL_DELAY (150)
  84. #define OWL_S500_DDRPLL_DELAY (63)
  85. #define OWL_S500_DEVPLL_DELAY (28)
  86. #define OWL_S500_NANDPLL_DELAY (44)
  87. #define OWL_S500_DISPLAYPLL_DELAY (57)
  88. #define OWL_S500_ETHERNETPLL_DELAY (25)
  89. #define OWL_S500_AUDIOPLL_DELAY (100)
  90. static const struct clk_pll_table clk_audio_pll_table[] = {
  91. { 0, 45158400 }, { 1, 49152000 },
  92. { 0, 0 },
  93. };
  94. /* pll clocks */
  95. static OWL_PLL_NO_PARENT_DELAY(ethernet_pll_clk, "ethernet_pll_clk", CMU_ETHERNETPLL, 500000000, 0, 0, 0, 0, 0, OWL_S500_ETHERNETPLL_DELAY, NULL, CLK_IGNORE_UNUSED);
  96. static OWL_PLL_NO_PARENT_DELAY(core_pll_clk, "core_pll_clk", CMU_COREPLL, 12000000, 9, 0, 8, 4, 134, OWL_S500_COREPLL_DELAY, NULL, CLK_IGNORE_UNUSED);
  97. static OWL_PLL_NO_PARENT_DELAY(ddr_pll_clk, "ddr_pll_clk", CMU_DDRPLL, 12000000, 8, 0, 8, 1, 67, OWL_S500_DDRPLL_DELAY, NULL, CLK_IGNORE_UNUSED);
  98. static OWL_PLL_NO_PARENT_DELAY(nand_pll_clk, "nand_pll_clk", CMU_NANDPLL, 6000000, 8, 0, 7, 2, 86, OWL_S500_NANDPLL_DELAY, NULL, CLK_IGNORE_UNUSED);
  99. static OWL_PLL_NO_PARENT_DELAY(display_pll_clk, "display_pll_clk", CMU_DISPLAYPLL, 6000000, 8, 0, 8, 2, 126, OWL_S500_DISPLAYPLL_DELAY, NULL, CLK_IGNORE_UNUSED);
  100. static OWL_PLL_NO_PARENT_DELAY(dev_pll_clk, "dev_pll_clk", CMU_DEVPLL, 6000000, 8, 0, 7, 8, 126, OWL_S500_DEVPLL_DELAY, NULL, CLK_IGNORE_UNUSED);
  101. static OWL_PLL_NO_PARENT_DELAY(audio_pll_clk, "audio_pll_clk", CMU_AUDIOPLL, 0, 4, 0, 1, 0, 0, OWL_S500_AUDIOPLL_DELAY, clk_audio_pll_table, CLK_IGNORE_UNUSED);
  102. static const char * const dev_clk_mux_p[] = { "hosc", "dev_pll_clk" };
  103. static const char * const bisp_clk_mux_p[] = { "display_pll_clk", "dev_clk" };
  104. static const char * const sensor_clk_mux_p[] = { "hosc", "bisp_clk" };
  105. static const char * const sd_clk_mux_p[] = { "dev_clk", "nand_pll_clk" };
  106. static const char * const pwm_clk_mux_p[] = { "losc", "hosc" };
  107. static const char * const ahbprediv_clk_mux_p[] = { "dev_clk", "display_pll_clk", "nand_pll_clk", "ddr_pll_clk" };
  108. static const char * const uart_clk_mux_p[] = { "hosc", "dev_pll_clk" };
  109. static const char * const de_clk_mux_p[] = { "display_pll_clk", "dev_clk" };
  110. static const char * const i2s_clk_mux_p[] = { "audio_pll_clk" };
  111. static const char * const hde_clk_mux_p[] = { "dev_clk", "display_pll_clk", "nand_pll_clk", "ddr_pll_clk" };
  112. static const char * const nand_clk_mux_p[] = { "nand_pll_clk", "display_pll_clk", "dev_clk", "ddr_pll_clk" };
  113. static struct clk_factor_table sd_factor_table[] = {
  114. /* bit0 ~ 4 */
  115. { 0, 1, 1 }, { 1, 1, 2 }, { 2, 1, 3 }, { 3, 1, 4 },
  116. { 4, 1, 5 }, { 5, 1, 6 }, { 6, 1, 7 }, { 7, 1, 8 },
  117. { 8, 1, 9 }, { 9, 1, 10 }, { 10, 1, 11 }, { 11, 1, 12 },
  118. { 12, 1, 13 }, { 13, 1, 14 }, { 14, 1, 15 }, { 15, 1, 16 },
  119. { 16, 1, 17 }, { 17, 1, 18 }, { 18, 1, 19 }, { 19, 1, 20 },
  120. { 20, 1, 21 }, { 21, 1, 22 }, { 22, 1, 23 }, { 23, 1, 24 },
  121. { 24, 1, 25 },
  122. /* bit8: /128 */
  123. { 256, 1, 1 * 128 }, { 257, 1, 2 * 128 }, { 258, 1, 3 * 128 }, { 259, 1, 4 * 128 },
  124. { 260, 1, 5 * 128 }, { 261, 1, 6 * 128 }, { 262, 1, 7 * 128 }, { 263, 1, 8 * 128 },
  125. { 264, 1, 9 * 128 }, { 265, 1, 10 * 128 }, { 266, 1, 11 * 128 }, { 267, 1, 12 * 128 },
  126. { 268, 1, 13 * 128 }, { 269, 1, 14 * 128 }, { 270, 1, 15 * 128 }, { 271, 1, 16 * 128 },
  127. { 272, 1, 17 * 128 }, { 273, 1, 18 * 128 }, { 274, 1, 19 * 128 }, { 275, 1, 20 * 128 },
  128. { 276, 1, 21 * 128 }, { 277, 1, 22 * 128 }, { 278, 1, 23 * 128 }, { 279, 1, 24 * 128 },
  129. { 280, 1, 25 * 128 },
  130. { 0, 0, 0 },
  131. };
  132. static struct clk_factor_table de_factor_table[] = {
  133. { 0, 1, 1 }, { 1, 2, 3 }, { 2, 1, 2 }, { 3, 2, 5 },
  134. { 4, 1, 3 }, { 5, 1, 4 }, { 6, 1, 6 }, { 7, 1, 8 },
  135. { 8, 1, 12 },
  136. { 0, 0, 0 },
  137. };
  138. static struct clk_factor_table hde_factor_table[] = {
  139. { 0, 1, 1 }, { 1, 2, 3 }, { 2, 1, 2 }, { 3, 2, 5 },
  140. { 4, 1, 3 }, { 5, 1, 4 }, { 6, 1, 6 }, { 7, 1, 8 },
  141. { 0, 0, 0 },
  142. };
  143. static struct clk_div_table rmii_ref_div_table[] = {
  144. { 0, 4 }, { 1, 10 },
  145. { 0, 0 },
  146. };
  147. static struct clk_div_table std12rate_div_table[] = {
  148. { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
  149. { 4, 5 }, { 5, 6 }, { 6, 7 }, { 7, 8 },
  150. { 8, 9 }, { 9, 10 }, { 10, 11 }, { 11, 12 },
  151. { 0, 0 },
  152. };
  153. static struct clk_div_table i2s_div_table[] = {
  154. { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
  155. { 4, 6 }, { 5, 8 }, { 6, 12 }, { 7, 16 },
  156. { 8, 24 },
  157. { 0, 0 },
  158. };
  159. static struct clk_div_table nand_div_table[] = {
  160. { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 6 },
  161. { 4, 8 }, { 5, 10 }, { 6, 12 }, { 7, 14 },
  162. { 8, 16 }, { 9, 18 }, { 10, 20 }, { 11, 22 },
  163. { 0, 0 },
  164. };
  165. /* mux clock */
  166. static OWL_MUX(dev_clk, "dev_clk", dev_clk_mux_p, CMU_DEVPLL, 12, 1, CLK_SET_RATE_PARENT);
  167. /* gate clocks */
  168. static OWL_GATE(gpio_clk, "gpio_clk", "apb_clk", CMU_DEVCLKEN0, 18, 0, 0);
  169. static OWL_GATE(dmac_clk, "dmac_clk", "h_clk", CMU_DEVCLKEN0, 1, 0, 0);
  170. static OWL_GATE(spi0_clk, "spi0_clk", "ahb_clk", CMU_DEVCLKEN1, 10, 0, CLK_IGNORE_UNUSED);
  171. static OWL_GATE(spi1_clk, "spi1_clk", "ahb_clk", CMU_DEVCLKEN1, 11, 0, CLK_IGNORE_UNUSED);
  172. static OWL_GATE(spi2_clk, "spi2_clk", "ahb_clk", CMU_DEVCLKEN1, 12, 0, CLK_IGNORE_UNUSED);
  173. static OWL_GATE(spi3_clk, "spi3_clk", "ahb_clk", CMU_DEVCLKEN1, 13, 0, CLK_IGNORE_UNUSED);
  174. static OWL_GATE(timer_clk, "timer_clk", "hosc", CMU_DEVCLKEN1, 27, 0, 0);
  175. static OWL_GATE(hdmi_clk, "hdmi_clk", "hosc", CMU_DEVCLKEN1, 3, 0, 0);
  176. /* divider clocks */
  177. static OWL_DIVIDER(h_clk, "h_clk", "ahbprediv_clk", CMU_BUSCLK1, 2, 2, NULL, 0, 0);
  178. static OWL_DIVIDER(apb_clk, "apb_clk", "ahb_clk", CMU_BUSCLK1, 14, 2, NULL, 0, 0);
  179. static OWL_DIVIDER(rmii_ref_clk, "rmii_ref_clk", "ethernet_pll_clk", CMU_ETHERNETPLL, 1, 1, rmii_ref_div_table, 0, 0);
  180. /* factor clocks */
  181. static OWL_FACTOR(de1_clk, "de_clk1", "de_clk", CMU_DECLK, 0, 4, de_factor_table, 0, 0);
  182. static OWL_FACTOR(de2_clk, "de_clk2", "de_clk", CMU_DECLK, 4, 4, de_factor_table, 0, 0);
  183. /* composite clocks */
  184. static OWL_COMP_DIV(ahbprediv_clk, "ahbprediv_clk", ahbprediv_clk_mux_p,
  185. OWL_MUX_HW(CMU_BUSCLK1, 8, 3),
  186. { 0 },
  187. OWL_DIVIDER_HW(CMU_BUSCLK1, 12, 2, 0, NULL),
  188. CLK_SET_RATE_PARENT);
  189. static OWL_COMP_FIXED_FACTOR(ahb_clk, "ahb_clk", "h_clk",
  190. { 0 },
  191. 1, 1, 0);
  192. static OWL_COMP_FACTOR(vce_clk, "vce_clk", hde_clk_mux_p,
  193. OWL_MUX_HW(CMU_VCECLK, 4, 2),
  194. OWL_GATE_HW(CMU_DEVCLKEN0, 26, 0),
  195. OWL_FACTOR_HW(CMU_VCECLK, 0, 3, 0, hde_factor_table),
  196. 0);
  197. static OWL_COMP_FACTOR(vde_clk, "vde_clk", hde_clk_mux_p,
  198. OWL_MUX_HW(CMU_VDECLK, 4, 2),
  199. OWL_GATE_HW(CMU_DEVCLKEN0, 25, 0),
  200. OWL_FACTOR_HW(CMU_VDECLK, 0, 3, 0, hde_factor_table),
  201. 0);
  202. static OWL_COMP_DIV(bisp_clk, "bisp_clk", bisp_clk_mux_p,
  203. OWL_MUX_HW(CMU_BISPCLK, 4, 1),
  204. OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0),
  205. OWL_DIVIDER_HW(CMU_BISPCLK, 0, 4, 0, std12rate_div_table),
  206. 0);
  207. static OWL_COMP_DIV(sensor0_clk, "sensor0_clk", sensor_clk_mux_p,
  208. OWL_MUX_HW(CMU_SENSORCLK, 4, 1),
  209. OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0),
  210. OWL_DIVIDER_HW(CMU_SENSORCLK, 0, 4, 0, std12rate_div_table),
  211. 0);
  212. static OWL_COMP_DIV(sensor1_clk, "sensor1_clk", sensor_clk_mux_p,
  213. OWL_MUX_HW(CMU_SENSORCLK, 4, 1),
  214. OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0),
  215. OWL_DIVIDER_HW(CMU_SENSORCLK, 8, 4, 0, std12rate_div_table),
  216. 0);
  217. static OWL_COMP_FACTOR(sd0_clk, "sd0_clk", sd_clk_mux_p,
  218. OWL_MUX_HW(CMU_SD0CLK, 9, 1),
  219. OWL_GATE_HW(CMU_DEVCLKEN0, 5, 0),
  220. OWL_FACTOR_HW(CMU_SD0CLK, 0, 9, 0, sd_factor_table),
  221. 0);
  222. static OWL_COMP_FACTOR(sd1_clk, "sd1_clk", sd_clk_mux_p,
  223. OWL_MUX_HW(CMU_SD1CLK, 9, 1),
  224. OWL_GATE_HW(CMU_DEVCLKEN0, 6, 0),
  225. OWL_FACTOR_HW(CMU_SD1CLK, 0, 9, 0, sd_factor_table),
  226. 0);
  227. static OWL_COMP_FACTOR(sd2_clk, "sd2_clk", sd_clk_mux_p,
  228. OWL_MUX_HW(CMU_SD2CLK, 9, 1),
  229. OWL_GATE_HW(CMU_DEVCLKEN0, 7, 0),
  230. OWL_FACTOR_HW(CMU_SD2CLK, 0, 9, 0, sd_factor_table),
  231. 0);
  232. static OWL_COMP_DIV(pwm0_clk, "pwm0_clk", pwm_clk_mux_p,
  233. OWL_MUX_HW(CMU_PWM0CLK, 12, 1),
  234. OWL_GATE_HW(CMU_DEVCLKEN1, 23, 0),
  235. OWL_DIVIDER_HW(CMU_PWM0CLK, 0, 10, 0, NULL),
  236. 0);
  237. static OWL_COMP_DIV(pwm1_clk, "pwm1_clk", pwm_clk_mux_p,
  238. OWL_MUX_HW(CMU_PWM1CLK, 12, 1),
  239. OWL_GATE_HW(CMU_DEVCLKEN1, 24, 0),
  240. OWL_DIVIDER_HW(CMU_PWM1CLK, 0, 10, 0, NULL),
  241. 0);
  242. static OWL_COMP_DIV(pwm2_clk, "pwm2_clk", pwm_clk_mux_p,
  243. OWL_MUX_HW(CMU_PWM2CLK, 12, 1),
  244. OWL_GATE_HW(CMU_DEVCLKEN1, 25, 0),
  245. OWL_DIVIDER_HW(CMU_PWM2CLK, 0, 10, 0, NULL),
  246. 0);
  247. static OWL_COMP_DIV(pwm3_clk, "pwm3_clk", pwm_clk_mux_p,
  248. OWL_MUX_HW(CMU_PWM3CLK, 12, 1),
  249. OWL_GATE_HW(CMU_DEVCLKEN1, 26, 0),
  250. OWL_DIVIDER_HW(CMU_PWM3CLK, 0, 10, 0, NULL),
  251. 0);
  252. static OWL_COMP_DIV(pwm4_clk, "pwm4_clk", pwm_clk_mux_p,
  253. OWL_MUX_HW(CMU_PWM4CLK, 12, 1),
  254. OWL_GATE_HW(CMU_DEVCLKEN0, 11, 0),
  255. OWL_DIVIDER_HW(CMU_PWM4CLK, 0, 10, 0, NULL),
  256. 0);
  257. static OWL_COMP_DIV(pwm5_clk, "pwm5_clk", pwm_clk_mux_p,
  258. OWL_MUX_HW(CMU_PWM5CLK, 12, 1),
  259. OWL_GATE_HW(CMU_DEVCLKEN0, 0, 0),
  260. OWL_DIVIDER_HW(CMU_PWM5CLK, 0, 10, 0, NULL),
  261. 0);
  262. static OWL_COMP_PASS(de_clk, "de_clk", de_clk_mux_p,
  263. OWL_MUX_HW(CMU_DECLK, 12, 1),
  264. OWL_GATE_HW(CMU_DEVCLKEN0, 8, 0),
  265. 0);
  266. static OWL_COMP_FIXED_FACTOR(i2c0_clk, "i2c0_clk", "ethernet_pll_clk",
  267. OWL_GATE_HW(CMU_DEVCLKEN1, 14, 0),
  268. 1, 5, 0);
  269. static OWL_COMP_FIXED_FACTOR(i2c1_clk, "i2c1_clk", "ethernet_pll_clk",
  270. OWL_GATE_HW(CMU_DEVCLKEN1, 15, 0),
  271. 1, 5, 0);
  272. static OWL_COMP_FIXED_FACTOR(i2c2_clk, "i2c2_clk", "ethernet_pll_clk",
  273. OWL_GATE_HW(CMU_DEVCLKEN1, 30, 0),
  274. 1, 5, 0);
  275. static OWL_COMP_FIXED_FACTOR(i2c3_clk, "i2c3_clk", "ethernet_pll_clk",
  276. OWL_GATE_HW(CMU_DEVCLKEN1, 31, 0),
  277. 1, 5, 0);
  278. static OWL_COMP_DIV(uart0_clk, "uart0_clk", uart_clk_mux_p,
  279. OWL_MUX_HW(CMU_UART0CLK, 16, 1),
  280. OWL_GATE_HW(CMU_DEVCLKEN1, 6, 0),
  281. OWL_DIVIDER_HW(CMU_UART0CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
  282. CLK_IGNORE_UNUSED);
  283. static OWL_COMP_DIV(uart1_clk, "uart1_clk", uart_clk_mux_p,
  284. OWL_MUX_HW(CMU_UART1CLK, 16, 1),
  285. OWL_GATE_HW(CMU_DEVCLKEN1, 7, 0),
  286. OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
  287. CLK_IGNORE_UNUSED);
  288. static OWL_COMP_DIV(uart2_clk, "uart2_clk", uart_clk_mux_p,
  289. OWL_MUX_HW(CMU_UART2CLK, 16, 1),
  290. OWL_GATE_HW(CMU_DEVCLKEN1, 8, 0),
  291. OWL_DIVIDER_HW(CMU_UART2CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
  292. CLK_IGNORE_UNUSED);
  293. static OWL_COMP_DIV(uart3_clk, "uart3_clk", uart_clk_mux_p,
  294. OWL_MUX_HW(CMU_UART3CLK, 16, 1),
  295. OWL_GATE_HW(CMU_DEVCLKEN1, 19, 0),
  296. OWL_DIVIDER_HW(CMU_UART3CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
  297. CLK_IGNORE_UNUSED);
  298. static OWL_COMP_DIV(uart4_clk, "uart4_clk", uart_clk_mux_p,
  299. OWL_MUX_HW(CMU_UART4CLK, 16, 1),
  300. OWL_GATE_HW(CMU_DEVCLKEN1, 20, 0),
  301. OWL_DIVIDER_HW(CMU_UART4CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
  302. CLK_IGNORE_UNUSED);
  303. static OWL_COMP_DIV(uart5_clk, "uart5_clk", uart_clk_mux_p,
  304. OWL_MUX_HW(CMU_UART5CLK, 16, 1),
  305. OWL_GATE_HW(CMU_DEVCLKEN1, 21, 0),
  306. OWL_DIVIDER_HW(CMU_UART5CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
  307. CLK_IGNORE_UNUSED);
  308. static OWL_COMP_DIV(uart6_clk, "uart6_clk", uart_clk_mux_p,
  309. OWL_MUX_HW(CMU_UART6CLK, 16, 1),
  310. OWL_GATE_HW(CMU_DEVCLKEN1, 18, 0),
  311. OWL_DIVIDER_HW(CMU_UART6CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
  312. CLK_IGNORE_UNUSED);
  313. static OWL_COMP_DIV(i2srx_clk, "i2srx_clk", i2s_clk_mux_p,
  314. OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
  315. OWL_GATE_HW(CMU_DEVCLKEN0, 21, 0),
  316. OWL_DIVIDER_HW(CMU_AUDIOPLL, 20, 4, 0, i2s_div_table),
  317. 0);
  318. static OWL_COMP_DIV(i2stx_clk, "i2stx_clk", i2s_clk_mux_p,
  319. OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
  320. OWL_GATE_HW(CMU_DEVCLKEN0, 20, 0),
  321. OWL_DIVIDER_HW(CMU_AUDIOPLL, 16, 4, 0, i2s_div_table),
  322. 0);
  323. static OWL_COMP_DIV(hdmia_clk, "hdmia_clk", i2s_clk_mux_p,
  324. OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
  325. OWL_GATE_HW(CMU_DEVCLKEN0, 22, 0),
  326. OWL_DIVIDER_HW(CMU_AUDIOPLL, 24, 4, 0, i2s_div_table),
  327. 0);
  328. static OWL_COMP_DIV(spdif_clk, "spdif_clk", i2s_clk_mux_p,
  329. OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
  330. OWL_GATE_HW(CMU_DEVCLKEN0, 23, 0),
  331. OWL_DIVIDER_HW(CMU_AUDIOPLL, 28, 4, 0, i2s_div_table),
  332. 0);
  333. static OWL_COMP_DIV(nand_clk, "nand_clk", nand_clk_mux_p,
  334. OWL_MUX_HW(CMU_NANDCCLK, 8, 2),
  335. OWL_GATE_HW(CMU_DEVCLKEN0, 4, 0),
  336. OWL_DIVIDER_HW(CMU_NANDCCLK, 0, 3, 0, nand_div_table),
  337. CLK_SET_RATE_PARENT);
  338. static OWL_COMP_DIV(ecc_clk, "ecc_clk", nand_clk_mux_p,
  339. OWL_MUX_HW(CMU_NANDCCLK, 8, 2),
  340. OWL_GATE_HW(CMU_DEVCLKEN0, 4, 0),
  341. OWL_DIVIDER_HW(CMU_NANDCCLK, 4, 3, 0, nand_div_table),
  342. CLK_SET_RATE_PARENT);
  343. static struct owl_clk_common *s500_clks[] = {
  344. &ethernet_pll_clk.common,
  345. &core_pll_clk.common,
  346. &ddr_pll_clk.common,
  347. &dev_pll_clk.common,
  348. &nand_pll_clk.common,
  349. &audio_pll_clk.common,
  350. &display_pll_clk.common,
  351. &dev_clk.common,
  352. &timer_clk.common,
  353. &i2c0_clk.common,
  354. &i2c1_clk.common,
  355. &i2c2_clk.common,
  356. &i2c3_clk.common,
  357. &uart0_clk.common,
  358. &uart1_clk.common,
  359. &uart2_clk.common,
  360. &uart3_clk.common,
  361. &uart4_clk.common,
  362. &uart5_clk.common,
  363. &uart6_clk.common,
  364. &pwm0_clk.common,
  365. &pwm1_clk.common,
  366. &pwm2_clk.common,
  367. &pwm3_clk.common,
  368. &pwm4_clk.common,
  369. &pwm5_clk.common,
  370. &sensor0_clk.common,
  371. &sensor1_clk.common,
  372. &sd0_clk.common,
  373. &sd1_clk.common,
  374. &sd2_clk.common,
  375. &bisp_clk.common,
  376. &ahb_clk.common,
  377. &ahbprediv_clk.common,
  378. &h_clk.common,
  379. &spi0_clk.common,
  380. &spi1_clk.common,
  381. &spi2_clk.common,
  382. &spi3_clk.common,
  383. &rmii_ref_clk.common,
  384. &de_clk.common,
  385. &de1_clk.common,
  386. &de2_clk.common,
  387. &i2srx_clk.common,
  388. &i2stx_clk.common,
  389. &hdmia_clk.common,
  390. &hdmi_clk.common,
  391. &vce_clk.common,
  392. &vde_clk.common,
  393. &spdif_clk.common,
  394. &nand_clk.common,
  395. &ecc_clk.common,
  396. &apb_clk.common,
  397. &dmac_clk.common,
  398. &gpio_clk.common,
  399. };
  400. static struct clk_hw_onecell_data s500_hw_clks = {
  401. .hws = {
  402. [CLK_ETHERNET_PLL] = &ethernet_pll_clk.common.hw,
  403. [CLK_CORE_PLL] = &core_pll_clk.common.hw,
  404. [CLK_DDR_PLL] = &ddr_pll_clk.common.hw,
  405. [CLK_NAND_PLL] = &nand_pll_clk.common.hw,
  406. [CLK_DISPLAY_PLL] = &display_pll_clk.common.hw,
  407. [CLK_DEV_PLL] = &dev_pll_clk.common.hw,
  408. [CLK_AUDIO_PLL] = &audio_pll_clk.common.hw,
  409. [CLK_TIMER] = &timer_clk.common.hw,
  410. [CLK_DEV] = &dev_clk.common.hw,
  411. [CLK_DE] = &de_clk.common.hw,
  412. [CLK_DE1] = &de1_clk.common.hw,
  413. [CLK_DE2] = &de2_clk.common.hw,
  414. [CLK_I2C0] = &i2c0_clk.common.hw,
  415. [CLK_I2C1] = &i2c1_clk.common.hw,
  416. [CLK_I2C2] = &i2c2_clk.common.hw,
  417. [CLK_I2C3] = &i2c3_clk.common.hw,
  418. [CLK_I2SRX] = &i2srx_clk.common.hw,
  419. [CLK_I2STX] = &i2stx_clk.common.hw,
  420. [CLK_UART0] = &uart0_clk.common.hw,
  421. [CLK_UART1] = &uart1_clk.common.hw,
  422. [CLK_UART2] = &uart2_clk.common.hw,
  423. [CLK_UART3] = &uart3_clk.common.hw,
  424. [CLK_UART4] = &uart4_clk.common.hw,
  425. [CLK_UART5] = &uart5_clk.common.hw,
  426. [CLK_UART6] = &uart6_clk.common.hw,
  427. [CLK_PWM0] = &pwm0_clk.common.hw,
  428. [CLK_PWM1] = &pwm1_clk.common.hw,
  429. [CLK_PWM2] = &pwm2_clk.common.hw,
  430. [CLK_PWM3] = &pwm3_clk.common.hw,
  431. [CLK_PWM4] = &pwm4_clk.common.hw,
  432. [CLK_PWM5] = &pwm5_clk.common.hw,
  433. [CLK_SENSOR0] = &sensor0_clk.common.hw,
  434. [CLK_SENSOR1] = &sensor1_clk.common.hw,
  435. [CLK_SD0] = &sd0_clk.common.hw,
  436. [CLK_SD1] = &sd1_clk.common.hw,
  437. [CLK_SD2] = &sd2_clk.common.hw,
  438. [CLK_BISP] = &bisp_clk.common.hw,
  439. [CLK_SPI0] = &spi0_clk.common.hw,
  440. [CLK_SPI1] = &spi1_clk.common.hw,
  441. [CLK_SPI2] = &spi2_clk.common.hw,
  442. [CLK_SPI3] = &spi3_clk.common.hw,
  443. [CLK_AHB] = &ahb_clk.common.hw,
  444. [CLK_H] = &h_clk.common.hw,
  445. [CLK_AHBPREDIV] = &ahbprediv_clk.common.hw,
  446. [CLK_RMII_REF] = &rmii_ref_clk.common.hw,
  447. [CLK_HDMI_AUDIO] = &hdmia_clk.common.hw,
  448. [CLK_HDMI] = &hdmi_clk.common.hw,
  449. [CLK_VDE] = &vde_clk.common.hw,
  450. [CLK_VCE] = &vce_clk.common.hw,
  451. [CLK_SPDIF] = &spdif_clk.common.hw,
  452. [CLK_NAND] = &nand_clk.common.hw,
  453. [CLK_ECC] = &ecc_clk.common.hw,
  454. [CLK_APB] = &apb_clk.common.hw,
  455. [CLK_DMAC] = &dmac_clk.common.hw,
  456. [CLK_GPIO] = &gpio_clk.common.hw,
  457. },
  458. .num = CLK_NR_CLKS,
  459. };
  460. static const struct owl_reset_map s500_resets[] = {
  461. [RESET_DMAC] = { CMU_DEVRST0, BIT(0) },
  462. [RESET_NORIF] = { CMU_DEVRST0, BIT(1) },
  463. [RESET_DDR] = { CMU_DEVRST0, BIT(2) },
  464. [RESET_NANDC] = { CMU_DEVRST0, BIT(3) },
  465. [RESET_SD0] = { CMU_DEVRST0, BIT(4) },
  466. [RESET_SD1] = { CMU_DEVRST0, BIT(5) },
  467. [RESET_PCM1] = { CMU_DEVRST0, BIT(6) },
  468. [RESET_DE] = { CMU_DEVRST0, BIT(7) },
  469. [RESET_LCD] = { CMU_DEVRST0, BIT(8) },
  470. [RESET_SD2] = { CMU_DEVRST0, BIT(9) },
  471. [RESET_DSI] = { CMU_DEVRST0, BIT(10) },
  472. [RESET_CSI] = { CMU_DEVRST0, BIT(11) },
  473. [RESET_BISP] = { CMU_DEVRST0, BIT(12) },
  474. [RESET_KEY] = { CMU_DEVRST0, BIT(14) },
  475. [RESET_GPIO] = { CMU_DEVRST0, BIT(15) },
  476. [RESET_AUDIO] = { CMU_DEVRST0, BIT(17) },
  477. [RESET_PCM0] = { CMU_DEVRST0, BIT(18) },
  478. [RESET_VDE] = { CMU_DEVRST0, BIT(19) },
  479. [RESET_VCE] = { CMU_DEVRST0, BIT(20) },
  480. [RESET_GPU3D] = { CMU_DEVRST0, BIT(22) },
  481. [RESET_NIC301] = { CMU_DEVRST0, BIT(23) },
  482. [RESET_LENS] = { CMU_DEVRST0, BIT(26) },
  483. [RESET_PERIPHRESET] = { CMU_DEVRST0, BIT(27) },
  484. [RESET_USB2_0] = { CMU_DEVRST1, BIT(0) },
  485. [RESET_TVOUT] = { CMU_DEVRST1, BIT(1) },
  486. [RESET_HDMI] = { CMU_DEVRST1, BIT(2) },
  487. [RESET_HDCP2TX] = { CMU_DEVRST1, BIT(3) },
  488. [RESET_UART6] = { CMU_DEVRST1, BIT(4) },
  489. [RESET_UART0] = { CMU_DEVRST1, BIT(5) },
  490. [RESET_UART1] = { CMU_DEVRST1, BIT(6) },
  491. [RESET_UART2] = { CMU_DEVRST1, BIT(7) },
  492. [RESET_SPI0] = { CMU_DEVRST1, BIT(8) },
  493. [RESET_SPI1] = { CMU_DEVRST1, BIT(9) },
  494. [RESET_SPI2] = { CMU_DEVRST1, BIT(10) },
  495. [RESET_SPI3] = { CMU_DEVRST1, BIT(11) },
  496. [RESET_I2C0] = { CMU_DEVRST1, BIT(12) },
  497. [RESET_I2C1] = { CMU_DEVRST1, BIT(13) },
  498. [RESET_USB3] = { CMU_DEVRST1, BIT(14) },
  499. [RESET_UART3] = { CMU_DEVRST1, BIT(15) },
  500. [RESET_UART4] = { CMU_DEVRST1, BIT(16) },
  501. [RESET_UART5] = { CMU_DEVRST1, BIT(17) },
  502. [RESET_I2C2] = { CMU_DEVRST1, BIT(18) },
  503. [RESET_I2C3] = { CMU_DEVRST1, BIT(19) },
  504. [RESET_ETHERNET] = { CMU_DEVRST1, BIT(20) },
  505. [RESET_CHIPID] = { CMU_DEVRST1, BIT(21) },
  506. [RESET_USB2_1] = { CMU_DEVRST1, BIT(22) },
  507. [RESET_WD0RESET] = { CMU_DEVRST1, BIT(24) },
  508. [RESET_WD1RESET] = { CMU_DEVRST1, BIT(25) },
  509. [RESET_WD2RESET] = { CMU_DEVRST1, BIT(26) },
  510. [RESET_WD3RESET] = { CMU_DEVRST1, BIT(27) },
  511. [RESET_DBG0RESET] = { CMU_DEVRST1, BIT(28) },
  512. [RESET_DBG1RESET] = { CMU_DEVRST1, BIT(29) },
  513. [RESET_DBG2RESET] = { CMU_DEVRST1, BIT(30) },
  514. [RESET_DBG3RESET] = { CMU_DEVRST1, BIT(31) },
  515. };
  516. static struct owl_clk_desc s500_clk_desc = {
  517. .clks = s500_clks,
  518. .num_clks = ARRAY_SIZE(s500_clks),
  519. .hw_clks = &s500_hw_clks,
  520. .resets = s500_resets,
  521. .num_resets = ARRAY_SIZE(s500_resets),
  522. };
  523. static int s500_clk_probe(struct platform_device *pdev)
  524. {
  525. struct owl_clk_desc *desc;
  526. struct owl_reset *reset;
  527. int ret;
  528. desc = &s500_clk_desc;
  529. owl_clk_regmap_init(pdev, desc);
  530. reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL);
  531. if (!reset)
  532. return -ENOMEM;
  533. reset->rcdev.of_node = pdev->dev.of_node;
  534. reset->rcdev.ops = &owl_reset_ops;
  535. reset->rcdev.nr_resets = desc->num_resets;
  536. reset->reset_map = desc->resets;
  537. reset->regmap = desc->regmap;
  538. ret = devm_reset_controller_register(&pdev->dev, &reset->rcdev);
  539. if (ret)
  540. dev_err(&pdev->dev, "Failed to register reset controller\n");
  541. return owl_clk_probe(&pdev->dev, desc->hw_clks);
  542. }
  543. static const struct of_device_id s500_clk_of_match[] = {
  544. { .compatible = "actions,s500-cmu", },
  545. { /* sentinel */ }
  546. };
  547. static struct platform_driver s500_clk_driver = {
  548. .probe = s500_clk_probe,
  549. .driver = {
  550. .name = "s500-cmu",
  551. .of_match_table = s500_clk_of_match,
  552. },
  553. };
  554. static int __init s500_clk_init(void)
  555. {
  556. return platform_driver_register(&s500_clk_driver);
  557. }
  558. core_initcall(s500_clk_init);