owl-pll.h 2.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. //
  3. // OWL pll clock driver
  4. //
  5. // Copyright (c) 2014 Actions Semi Inc.
  6. // Author: David Liu <liuwei@actions-semi.com>
  7. //
  8. // Copyright (c) 2018 Linaro Ltd.
  9. // Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
  10. #ifndef _OWL_PLL_H_
  11. #define _OWL_PLL_H_
  12. #include "owl-common.h"
  13. #define OWL_PLL_DEF_DELAY 50
  14. /* last entry should have rate = 0 */
  15. struct clk_pll_table {
  16. unsigned int val;
  17. unsigned long rate;
  18. };
  19. struct owl_pll_hw {
  20. u32 reg;
  21. u32 bfreq;
  22. u8 bit_idx;
  23. u8 shift;
  24. u8 width;
  25. u8 min_mul;
  26. u8 max_mul;
  27. u8 delay;
  28. const struct clk_pll_table *table;
  29. };
  30. struct owl_pll {
  31. struct owl_pll_hw pll_hw;
  32. struct owl_clk_common common;
  33. };
  34. #define OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
  35. _width, _min_mul, _max_mul, _delay, _table) \
  36. { \
  37. .reg = _reg, \
  38. .bfreq = _bfreq, \
  39. .bit_idx = _bit_idx, \
  40. .shift = _shift, \
  41. .width = _width, \
  42. .min_mul = _min_mul, \
  43. .max_mul = _max_mul, \
  44. .delay = _delay, \
  45. .table = _table, \
  46. }
  47. #define OWL_PLL(_struct, _name, _parent, _reg, _bfreq, _bit_idx, \
  48. _shift, _width, _min_mul, _max_mul, _table, _flags) \
  49. struct owl_pll _struct = { \
  50. .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
  51. _width, _min_mul, _max_mul, \
  52. OWL_PLL_DEF_DELAY, _table), \
  53. .common = { \
  54. .regmap = NULL, \
  55. .hw.init = CLK_HW_INIT(_name, \
  56. _parent, \
  57. &owl_pll_ops, \
  58. _flags), \
  59. }, \
  60. }
  61. #define OWL_PLL_NO_PARENT(_struct, _name, _reg, _bfreq, _bit_idx, \
  62. _shift, _width, _min_mul, _max_mul, _table, _flags) \
  63. struct owl_pll _struct = { \
  64. .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
  65. _width, _min_mul, _max_mul, \
  66. OWL_PLL_DEF_DELAY, _table), \
  67. .common = { \
  68. .regmap = NULL, \
  69. .hw.init = CLK_HW_INIT_NO_PARENT(_name, \
  70. &owl_pll_ops, \
  71. _flags), \
  72. }, \
  73. }
  74. #define OWL_PLL_NO_PARENT_DELAY(_struct, _name, _reg, _bfreq, _bit_idx, \
  75. _shift, _width, _min_mul, _max_mul, _delay, _table, \
  76. _flags) \
  77. struct owl_pll _struct = { \
  78. .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
  79. _width, _min_mul, _max_mul, \
  80. _delay, _table), \
  81. .common = { \
  82. .regmap = NULL, \
  83. .hw.init = CLK_HW_INIT_NO_PARENT(_name, \
  84. &owl_pll_ops, \
  85. _flags), \
  86. }, \
  87. }
  88. #define mul_mask(m) ((1 << ((m)->width)) - 1)
  89. static inline struct owl_pll *hw_to_owl_pll(const struct clk_hw *hw)
  90. {
  91. struct owl_clk_common *common = hw_to_owl_clk_common(hw);
  92. return container_of(common, struct owl_pll, common);
  93. }
  94. extern const struct clk_ops owl_pll_ops;
  95. #endif /* _OWL_PLL_H_ */