owl-mux.c 1.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960
  1. // SPDX-License-Identifier: GPL-2.0+
  2. //
  3. // OWL mux clock driver
  4. //
  5. // Copyright (c) 2014 Actions Semi Inc.
  6. // Author: David Liu <liuwei@actions-semi.com>
  7. //
  8. // Copyright (c) 2018 Linaro Ltd.
  9. // Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
  10. #include <linux/clk-provider.h>
  11. #include <linux/regmap.h>
  12. #include "owl-mux.h"
  13. u8 owl_mux_helper_get_parent(const struct owl_clk_common *common,
  14. const struct owl_mux_hw *mux_hw)
  15. {
  16. u32 reg;
  17. u8 parent;
  18. regmap_read(common->regmap, mux_hw->reg, &reg);
  19. parent = reg >> mux_hw->shift;
  20. parent &= BIT(mux_hw->width) - 1;
  21. return parent;
  22. }
  23. static u8 owl_mux_get_parent(struct clk_hw *hw)
  24. {
  25. struct owl_mux *mux = hw_to_owl_mux(hw);
  26. return owl_mux_helper_get_parent(&mux->common, &mux->mux_hw);
  27. }
  28. int owl_mux_helper_set_parent(const struct owl_clk_common *common,
  29. struct owl_mux_hw *mux_hw, u8 index)
  30. {
  31. u32 reg;
  32. regmap_read(common->regmap, mux_hw->reg, &reg);
  33. reg &= ~GENMASK(mux_hw->width + mux_hw->shift - 1, mux_hw->shift);
  34. regmap_write(common->regmap, mux_hw->reg,
  35. reg | (index << mux_hw->shift));
  36. return 0;
  37. }
  38. static int owl_mux_set_parent(struct clk_hw *hw, u8 index)
  39. {
  40. struct owl_mux *mux = hw_to_owl_mux(hw);
  41. return owl_mux_helper_set_parent(&mux->common, &mux->mux_hw, index);
  42. }
  43. const struct clk_ops owl_mux_ops = {
  44. .get_parent = owl_mux_get_parent,
  45. .set_parent = owl_mux_set_parent,
  46. .determine_rate = __clk_mux_determine_rate,
  47. };