tlclk.c 23 KB

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  1. /*
  2. * Telecom Clock driver for Intel NetStructure(tm) MPCBL0010
  3. *
  4. * Copyright (C) 2005 Kontron Canada
  5. *
  6. * All rights reserved.
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or (at
  11. * your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful, but
  14. * WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  16. * NON INFRINGEMENT. See the GNU General Public License for more
  17. * details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22. *
  23. * Send feedback to <sebastien.bouchard@ca.kontron.com> and the current
  24. * Maintainer <mark.gross@intel.com>
  25. *
  26. * Description : This is the TELECOM CLOCK module driver for the ATCA
  27. * MPCBL0010 ATCA computer.
  28. */
  29. #include <linux/module.h>
  30. #include <linux/init.h>
  31. #include <linux/kernel.h> /* printk() */
  32. #include <linux/fs.h> /* everything... */
  33. #include <linux/errno.h> /* error codes */
  34. #include <linux/sched.h>
  35. #include <linux/slab.h>
  36. #include <linux/ioport.h>
  37. #include <linux/interrupt.h>
  38. #include <linux/spinlock.h>
  39. #include <linux/mutex.h>
  40. #include <linux/timer.h>
  41. #include <linux/sysfs.h>
  42. #include <linux/device.h>
  43. #include <linux/miscdevice.h>
  44. #include <linux/platform_device.h>
  45. #include <asm/io.h> /* inb/outb */
  46. #include <linux/uaccess.h>
  47. MODULE_AUTHOR("Sebastien Bouchard <sebastien.bouchard@ca.kontron.com>");
  48. MODULE_LICENSE("GPL");
  49. /*Hardware Reset of the PLL */
  50. #define RESET_ON 0x00
  51. #define RESET_OFF 0x01
  52. /* MODE SELECT */
  53. #define NORMAL_MODE 0x00
  54. #define HOLDOVER_MODE 0x10
  55. #define FREERUN_MODE 0x20
  56. /* FILTER SELECT */
  57. #define FILTER_6HZ 0x04
  58. #define FILTER_12HZ 0x00
  59. /* SELECT REFERENCE FREQUENCY */
  60. #define REF_CLK1_8kHz 0x00
  61. #define REF_CLK2_19_44MHz 0x02
  62. /* Select primary or secondary redundant clock */
  63. #define PRIMARY_CLOCK 0x00
  64. #define SECONDARY_CLOCK 0x01
  65. /* CLOCK TRANSMISSION DEFINE */
  66. #define CLK_8kHz 0xff
  67. #define CLK_16_384MHz 0xfb
  68. #define CLK_1_544MHz 0x00
  69. #define CLK_2_048MHz 0x01
  70. #define CLK_4_096MHz 0x02
  71. #define CLK_6_312MHz 0x03
  72. #define CLK_8_192MHz 0x04
  73. #define CLK_19_440MHz 0x06
  74. #define CLK_8_592MHz 0x08
  75. #define CLK_11_184MHz 0x09
  76. #define CLK_34_368MHz 0x0b
  77. #define CLK_44_736MHz 0x0a
  78. /* RECEIVED REFERENCE */
  79. #define AMC_B1 0
  80. #define AMC_B2 1
  81. /* HARDWARE SWITCHING DEFINE */
  82. #define HW_ENABLE 0x80
  83. #define HW_DISABLE 0x00
  84. /* HARDWARE SWITCHING MODE DEFINE */
  85. #define PLL_HOLDOVER 0x40
  86. #define LOST_CLOCK 0x00
  87. /* ALARMS DEFINE */
  88. #define UNLOCK_MASK 0x10
  89. #define HOLDOVER_MASK 0x20
  90. #define SEC_LOST_MASK 0x40
  91. #define PRI_LOST_MASK 0x80
  92. /* INTERRUPT CAUSE DEFINE */
  93. #define PRI_LOS_01_MASK 0x01
  94. #define PRI_LOS_10_MASK 0x02
  95. #define SEC_LOS_01_MASK 0x04
  96. #define SEC_LOS_10_MASK 0x08
  97. #define HOLDOVER_01_MASK 0x10
  98. #define HOLDOVER_10_MASK 0x20
  99. #define UNLOCK_01_MASK 0x40
  100. #define UNLOCK_10_MASK 0x80
  101. struct tlclk_alarms {
  102. __u32 lost_clocks;
  103. __u32 lost_primary_clock;
  104. __u32 lost_secondary_clock;
  105. __u32 primary_clock_back;
  106. __u32 secondary_clock_back;
  107. __u32 switchover_primary;
  108. __u32 switchover_secondary;
  109. __u32 pll_holdover;
  110. __u32 pll_end_holdover;
  111. __u32 pll_lost_sync;
  112. __u32 pll_sync;
  113. };
  114. /* Telecom clock I/O register definition */
  115. #define TLCLK_BASE 0xa08
  116. #define TLCLK_REG0 TLCLK_BASE
  117. #define TLCLK_REG1 (TLCLK_BASE+1)
  118. #define TLCLK_REG2 (TLCLK_BASE+2)
  119. #define TLCLK_REG3 (TLCLK_BASE+3)
  120. #define TLCLK_REG4 (TLCLK_BASE+4)
  121. #define TLCLK_REG5 (TLCLK_BASE+5)
  122. #define TLCLK_REG6 (TLCLK_BASE+6)
  123. #define TLCLK_REG7 (TLCLK_BASE+7)
  124. #define SET_PORT_BITS(port, mask, val) outb(((inb(port) & mask) | val), port)
  125. /* 0 = Dynamic allocation of the major device number */
  126. #define TLCLK_MAJOR 0
  127. /* sysfs interface definition:
  128. Upon loading the driver will create a sysfs directory under
  129. /sys/devices/platform/telco_clock.
  130. This directory exports the following interfaces. There operation is
  131. documented in the MCPBL0010 TPS under the Telecom Clock API section, 11.4.
  132. alarms :
  133. current_ref :
  134. received_ref_clk3a :
  135. received_ref_clk3b :
  136. enable_clk3a_output :
  137. enable_clk3b_output :
  138. enable_clka0_output :
  139. enable_clka1_output :
  140. enable_clkb0_output :
  141. enable_clkb1_output :
  142. filter_select :
  143. hardware_switching :
  144. hardware_switching_mode :
  145. telclock_version :
  146. mode_select :
  147. refalign :
  148. reset :
  149. select_amcb1_transmit_clock :
  150. select_amcb2_transmit_clock :
  151. select_redundant_clock :
  152. select_ref_frequency :
  153. All sysfs interfaces are integers in hex format, i.e echo 99 > refalign
  154. has the same effect as echo 0x99 > refalign.
  155. */
  156. static unsigned int telclk_interrupt;
  157. static int int_events; /* Event that generate a interrupt */
  158. static int got_event; /* if events processing have been done */
  159. static void switchover_timeout(struct timer_list *t);
  160. static struct timer_list switchover_timer;
  161. static unsigned long tlclk_timer_data;
  162. static struct tlclk_alarms *alarm_events;
  163. static DEFINE_SPINLOCK(event_lock);
  164. static int tlclk_major = TLCLK_MAJOR;
  165. static irqreturn_t tlclk_interrupt(int irq, void *dev_id);
  166. static DECLARE_WAIT_QUEUE_HEAD(wq);
  167. static unsigned long useflags;
  168. static DEFINE_MUTEX(tlclk_mutex);
  169. static int tlclk_open(struct inode *inode, struct file *filp)
  170. {
  171. int result;
  172. mutex_lock(&tlclk_mutex);
  173. if (test_and_set_bit(0, &useflags)) {
  174. result = -EBUSY;
  175. /* this legacy device is always one per system and it doesn't
  176. * know how to handle multiple concurrent clients.
  177. */
  178. goto out;
  179. }
  180. /* Make sure there is no interrupt pending while
  181. * initialising interrupt handler */
  182. inb(TLCLK_REG6);
  183. /* This device is wired through the FPGA IO space of the ATCA blade
  184. * we can't share this IRQ */
  185. result = request_irq(telclk_interrupt, &tlclk_interrupt,
  186. 0, "telco_clock", tlclk_interrupt);
  187. if (result == -EBUSY)
  188. printk(KERN_ERR "tlclk: Interrupt can't be reserved.\n");
  189. else
  190. inb(TLCLK_REG6); /* Clear interrupt events */
  191. out:
  192. mutex_unlock(&tlclk_mutex);
  193. return result;
  194. }
  195. static int tlclk_release(struct inode *inode, struct file *filp)
  196. {
  197. free_irq(telclk_interrupt, tlclk_interrupt);
  198. clear_bit(0, &useflags);
  199. return 0;
  200. }
  201. static ssize_t tlclk_read(struct file *filp, char __user *buf, size_t count,
  202. loff_t *f_pos)
  203. {
  204. if (count < sizeof(struct tlclk_alarms))
  205. return -EIO;
  206. if (mutex_lock_interruptible(&tlclk_mutex))
  207. return -EINTR;
  208. wait_event_interruptible(wq, got_event);
  209. if (copy_to_user(buf, alarm_events, sizeof(struct tlclk_alarms))) {
  210. mutex_unlock(&tlclk_mutex);
  211. return -EFAULT;
  212. }
  213. memset(alarm_events, 0, sizeof(struct tlclk_alarms));
  214. got_event = 0;
  215. mutex_unlock(&tlclk_mutex);
  216. return sizeof(struct tlclk_alarms);
  217. }
  218. static const struct file_operations tlclk_fops = {
  219. .read = tlclk_read,
  220. .open = tlclk_open,
  221. .release = tlclk_release,
  222. .llseek = noop_llseek,
  223. };
  224. static struct miscdevice tlclk_miscdev = {
  225. .minor = MISC_DYNAMIC_MINOR,
  226. .name = "telco_clock",
  227. .fops = &tlclk_fops,
  228. };
  229. static ssize_t show_current_ref(struct device *d,
  230. struct device_attribute *attr, char *buf)
  231. {
  232. unsigned long ret_val;
  233. unsigned long flags;
  234. spin_lock_irqsave(&event_lock, flags);
  235. ret_val = ((inb(TLCLK_REG1) & 0x08) >> 3);
  236. spin_unlock_irqrestore(&event_lock, flags);
  237. return sprintf(buf, "0x%lX\n", ret_val);
  238. }
  239. static DEVICE_ATTR(current_ref, S_IRUGO, show_current_ref, NULL);
  240. static ssize_t show_telclock_version(struct device *d,
  241. struct device_attribute *attr, char *buf)
  242. {
  243. unsigned long ret_val;
  244. unsigned long flags;
  245. spin_lock_irqsave(&event_lock, flags);
  246. ret_val = inb(TLCLK_REG5);
  247. spin_unlock_irqrestore(&event_lock, flags);
  248. return sprintf(buf, "0x%lX\n", ret_val);
  249. }
  250. static DEVICE_ATTR(telclock_version, S_IRUGO,
  251. show_telclock_version, NULL);
  252. static ssize_t show_alarms(struct device *d,
  253. struct device_attribute *attr, char *buf)
  254. {
  255. unsigned long ret_val;
  256. unsigned long flags;
  257. spin_lock_irqsave(&event_lock, flags);
  258. ret_val = (inb(TLCLK_REG2) & 0xf0);
  259. spin_unlock_irqrestore(&event_lock, flags);
  260. return sprintf(buf, "0x%lX\n", ret_val);
  261. }
  262. static DEVICE_ATTR(alarms, S_IRUGO, show_alarms, NULL);
  263. static ssize_t store_received_ref_clk3a(struct device *d,
  264. struct device_attribute *attr, const char *buf, size_t count)
  265. {
  266. unsigned long tmp;
  267. unsigned char val;
  268. unsigned long flags;
  269. sscanf(buf, "%lX", &tmp);
  270. dev_dbg(d, ": tmp = 0x%lX\n", tmp);
  271. val = (unsigned char)tmp;
  272. spin_lock_irqsave(&event_lock, flags);
  273. SET_PORT_BITS(TLCLK_REG1, 0xef, val);
  274. spin_unlock_irqrestore(&event_lock, flags);
  275. return strnlen(buf, count);
  276. }
  277. static DEVICE_ATTR(received_ref_clk3a, (S_IWUSR|S_IWGRP), NULL,
  278. store_received_ref_clk3a);
  279. static ssize_t store_received_ref_clk3b(struct device *d,
  280. struct device_attribute *attr, const char *buf, size_t count)
  281. {
  282. unsigned long tmp;
  283. unsigned char val;
  284. unsigned long flags;
  285. sscanf(buf, "%lX", &tmp);
  286. dev_dbg(d, ": tmp = 0x%lX\n", tmp);
  287. val = (unsigned char)tmp;
  288. spin_lock_irqsave(&event_lock, flags);
  289. SET_PORT_BITS(TLCLK_REG1, 0xdf, val << 1);
  290. spin_unlock_irqrestore(&event_lock, flags);
  291. return strnlen(buf, count);
  292. }
  293. static DEVICE_ATTR(received_ref_clk3b, (S_IWUSR|S_IWGRP), NULL,
  294. store_received_ref_clk3b);
  295. static ssize_t store_enable_clk3b_output(struct device *d,
  296. struct device_attribute *attr, const char *buf, size_t count)
  297. {
  298. unsigned long tmp;
  299. unsigned char val;
  300. unsigned long flags;
  301. sscanf(buf, "%lX", &tmp);
  302. dev_dbg(d, ": tmp = 0x%lX\n", tmp);
  303. val = (unsigned char)tmp;
  304. spin_lock_irqsave(&event_lock, flags);
  305. SET_PORT_BITS(TLCLK_REG3, 0x7f, val << 7);
  306. spin_unlock_irqrestore(&event_lock, flags);
  307. return strnlen(buf, count);
  308. }
  309. static DEVICE_ATTR(enable_clk3b_output, (S_IWUSR|S_IWGRP), NULL,
  310. store_enable_clk3b_output);
  311. static ssize_t store_enable_clk3a_output(struct device *d,
  312. struct device_attribute *attr, const char *buf, size_t count)
  313. {
  314. unsigned long flags;
  315. unsigned long tmp;
  316. unsigned char val;
  317. sscanf(buf, "%lX", &tmp);
  318. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  319. val = (unsigned char)tmp;
  320. spin_lock_irqsave(&event_lock, flags);
  321. SET_PORT_BITS(TLCLK_REG3, 0xbf, val << 6);
  322. spin_unlock_irqrestore(&event_lock, flags);
  323. return strnlen(buf, count);
  324. }
  325. static DEVICE_ATTR(enable_clk3a_output, (S_IWUSR|S_IWGRP), NULL,
  326. store_enable_clk3a_output);
  327. static ssize_t store_enable_clkb1_output(struct device *d,
  328. struct device_attribute *attr, const char *buf, size_t count)
  329. {
  330. unsigned long flags;
  331. unsigned long tmp;
  332. unsigned char val;
  333. sscanf(buf, "%lX", &tmp);
  334. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  335. val = (unsigned char)tmp;
  336. spin_lock_irqsave(&event_lock, flags);
  337. SET_PORT_BITS(TLCLK_REG2, 0xf7, val << 3);
  338. spin_unlock_irqrestore(&event_lock, flags);
  339. return strnlen(buf, count);
  340. }
  341. static DEVICE_ATTR(enable_clkb1_output, (S_IWUSR|S_IWGRP), NULL,
  342. store_enable_clkb1_output);
  343. static ssize_t store_enable_clka1_output(struct device *d,
  344. struct device_attribute *attr, const char *buf, size_t count)
  345. {
  346. unsigned long flags;
  347. unsigned long tmp;
  348. unsigned char val;
  349. sscanf(buf, "%lX", &tmp);
  350. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  351. val = (unsigned char)tmp;
  352. spin_lock_irqsave(&event_lock, flags);
  353. SET_PORT_BITS(TLCLK_REG2, 0xfb, val << 2);
  354. spin_unlock_irqrestore(&event_lock, flags);
  355. return strnlen(buf, count);
  356. }
  357. static DEVICE_ATTR(enable_clka1_output, (S_IWUSR|S_IWGRP), NULL,
  358. store_enable_clka1_output);
  359. static ssize_t store_enable_clkb0_output(struct device *d,
  360. struct device_attribute *attr, const char *buf, size_t count)
  361. {
  362. unsigned long flags;
  363. unsigned long tmp;
  364. unsigned char val;
  365. sscanf(buf, "%lX", &tmp);
  366. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  367. val = (unsigned char)tmp;
  368. spin_lock_irqsave(&event_lock, flags);
  369. SET_PORT_BITS(TLCLK_REG2, 0xfd, val << 1);
  370. spin_unlock_irqrestore(&event_lock, flags);
  371. return strnlen(buf, count);
  372. }
  373. static DEVICE_ATTR(enable_clkb0_output, (S_IWUSR|S_IWGRP), NULL,
  374. store_enable_clkb0_output);
  375. static ssize_t store_enable_clka0_output(struct device *d,
  376. struct device_attribute *attr, const char *buf, size_t count)
  377. {
  378. unsigned long flags;
  379. unsigned long tmp;
  380. unsigned char val;
  381. sscanf(buf, "%lX", &tmp);
  382. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  383. val = (unsigned char)tmp;
  384. spin_lock_irqsave(&event_lock, flags);
  385. SET_PORT_BITS(TLCLK_REG2, 0xfe, val);
  386. spin_unlock_irqrestore(&event_lock, flags);
  387. return strnlen(buf, count);
  388. }
  389. static DEVICE_ATTR(enable_clka0_output, (S_IWUSR|S_IWGRP), NULL,
  390. store_enable_clka0_output);
  391. static ssize_t store_select_amcb2_transmit_clock(struct device *d,
  392. struct device_attribute *attr, const char *buf, size_t count)
  393. {
  394. unsigned long flags;
  395. unsigned long tmp;
  396. unsigned char val;
  397. sscanf(buf, "%lX", &tmp);
  398. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  399. val = (unsigned char)tmp;
  400. spin_lock_irqsave(&event_lock, flags);
  401. if ((val == CLK_8kHz) || (val == CLK_16_384MHz)) {
  402. SET_PORT_BITS(TLCLK_REG3, 0xc7, 0x28);
  403. SET_PORT_BITS(TLCLK_REG1, 0xfb, ~val);
  404. } else if (val >= CLK_8_592MHz) {
  405. SET_PORT_BITS(TLCLK_REG3, 0xc7, 0x38);
  406. switch (val) {
  407. case CLK_8_592MHz:
  408. SET_PORT_BITS(TLCLK_REG0, 0xfc, 2);
  409. break;
  410. case CLK_11_184MHz:
  411. SET_PORT_BITS(TLCLK_REG0, 0xfc, 0);
  412. break;
  413. case CLK_34_368MHz:
  414. SET_PORT_BITS(TLCLK_REG0, 0xfc, 3);
  415. break;
  416. case CLK_44_736MHz:
  417. SET_PORT_BITS(TLCLK_REG0, 0xfc, 1);
  418. break;
  419. }
  420. } else {
  421. SET_PORT_BITS(TLCLK_REG3, 0xc7, val << 3);
  422. }
  423. spin_unlock_irqrestore(&event_lock, flags);
  424. return strnlen(buf, count);
  425. }
  426. static DEVICE_ATTR(select_amcb2_transmit_clock, (S_IWUSR|S_IWGRP), NULL,
  427. store_select_amcb2_transmit_clock);
  428. static ssize_t store_select_amcb1_transmit_clock(struct device *d,
  429. struct device_attribute *attr, const char *buf, size_t count)
  430. {
  431. unsigned long tmp;
  432. unsigned char val;
  433. unsigned long flags;
  434. sscanf(buf, "%lX", &tmp);
  435. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  436. val = (unsigned char)tmp;
  437. spin_lock_irqsave(&event_lock, flags);
  438. if ((val == CLK_8kHz) || (val == CLK_16_384MHz)) {
  439. SET_PORT_BITS(TLCLK_REG3, 0xf8, 0x5);
  440. SET_PORT_BITS(TLCLK_REG1, 0xfb, ~val);
  441. } else if (val >= CLK_8_592MHz) {
  442. SET_PORT_BITS(TLCLK_REG3, 0xf8, 0x7);
  443. switch (val) {
  444. case CLK_8_592MHz:
  445. SET_PORT_BITS(TLCLK_REG0, 0xfc, 2);
  446. break;
  447. case CLK_11_184MHz:
  448. SET_PORT_BITS(TLCLK_REG0, 0xfc, 0);
  449. break;
  450. case CLK_34_368MHz:
  451. SET_PORT_BITS(TLCLK_REG0, 0xfc, 3);
  452. break;
  453. case CLK_44_736MHz:
  454. SET_PORT_BITS(TLCLK_REG0, 0xfc, 1);
  455. break;
  456. }
  457. } else {
  458. SET_PORT_BITS(TLCLK_REG3, 0xf8, val);
  459. }
  460. spin_unlock_irqrestore(&event_lock, flags);
  461. return strnlen(buf, count);
  462. }
  463. static DEVICE_ATTR(select_amcb1_transmit_clock, (S_IWUSR|S_IWGRP), NULL,
  464. store_select_amcb1_transmit_clock);
  465. static ssize_t store_select_redundant_clock(struct device *d,
  466. struct device_attribute *attr, const char *buf, size_t count)
  467. {
  468. unsigned long tmp;
  469. unsigned char val;
  470. unsigned long flags;
  471. sscanf(buf, "%lX", &tmp);
  472. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  473. val = (unsigned char)tmp;
  474. spin_lock_irqsave(&event_lock, flags);
  475. SET_PORT_BITS(TLCLK_REG1, 0xfe, val);
  476. spin_unlock_irqrestore(&event_lock, flags);
  477. return strnlen(buf, count);
  478. }
  479. static DEVICE_ATTR(select_redundant_clock, (S_IWUSR|S_IWGRP), NULL,
  480. store_select_redundant_clock);
  481. static ssize_t store_select_ref_frequency(struct device *d,
  482. struct device_attribute *attr, const char *buf, size_t count)
  483. {
  484. unsigned long tmp;
  485. unsigned char val;
  486. unsigned long flags;
  487. sscanf(buf, "%lX", &tmp);
  488. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  489. val = (unsigned char)tmp;
  490. spin_lock_irqsave(&event_lock, flags);
  491. SET_PORT_BITS(TLCLK_REG1, 0xfd, val);
  492. spin_unlock_irqrestore(&event_lock, flags);
  493. return strnlen(buf, count);
  494. }
  495. static DEVICE_ATTR(select_ref_frequency, (S_IWUSR|S_IWGRP), NULL,
  496. store_select_ref_frequency);
  497. static ssize_t store_filter_select(struct device *d,
  498. struct device_attribute *attr, const char *buf, size_t count)
  499. {
  500. unsigned long tmp;
  501. unsigned char val;
  502. unsigned long flags;
  503. sscanf(buf, "%lX", &tmp);
  504. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  505. val = (unsigned char)tmp;
  506. spin_lock_irqsave(&event_lock, flags);
  507. SET_PORT_BITS(TLCLK_REG0, 0xfb, val);
  508. spin_unlock_irqrestore(&event_lock, flags);
  509. return strnlen(buf, count);
  510. }
  511. static DEVICE_ATTR(filter_select, (S_IWUSR|S_IWGRP), NULL, store_filter_select);
  512. static ssize_t store_hardware_switching_mode(struct device *d,
  513. struct device_attribute *attr, const char *buf, size_t count)
  514. {
  515. unsigned long tmp;
  516. unsigned char val;
  517. unsigned long flags;
  518. sscanf(buf, "%lX", &tmp);
  519. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  520. val = (unsigned char)tmp;
  521. spin_lock_irqsave(&event_lock, flags);
  522. SET_PORT_BITS(TLCLK_REG0, 0xbf, val);
  523. spin_unlock_irqrestore(&event_lock, flags);
  524. return strnlen(buf, count);
  525. }
  526. static DEVICE_ATTR(hardware_switching_mode, (S_IWUSR|S_IWGRP), NULL,
  527. store_hardware_switching_mode);
  528. static ssize_t store_hardware_switching(struct device *d,
  529. struct device_attribute *attr, const char *buf, size_t count)
  530. {
  531. unsigned long tmp;
  532. unsigned char val;
  533. unsigned long flags;
  534. sscanf(buf, "%lX", &tmp);
  535. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  536. val = (unsigned char)tmp;
  537. spin_lock_irqsave(&event_lock, flags);
  538. SET_PORT_BITS(TLCLK_REG0, 0x7f, val);
  539. spin_unlock_irqrestore(&event_lock, flags);
  540. return strnlen(buf, count);
  541. }
  542. static DEVICE_ATTR(hardware_switching, (S_IWUSR|S_IWGRP), NULL,
  543. store_hardware_switching);
  544. static ssize_t store_refalign (struct device *d,
  545. struct device_attribute *attr, const char *buf, size_t count)
  546. {
  547. unsigned long tmp;
  548. unsigned long flags;
  549. sscanf(buf, "%lX", &tmp);
  550. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  551. spin_lock_irqsave(&event_lock, flags);
  552. SET_PORT_BITS(TLCLK_REG0, 0xf7, 0);
  553. SET_PORT_BITS(TLCLK_REG0, 0xf7, 0x08);
  554. SET_PORT_BITS(TLCLK_REG0, 0xf7, 0);
  555. spin_unlock_irqrestore(&event_lock, flags);
  556. return strnlen(buf, count);
  557. }
  558. static DEVICE_ATTR(refalign, (S_IWUSR|S_IWGRP), NULL, store_refalign);
  559. static ssize_t store_mode_select (struct device *d,
  560. struct device_attribute *attr, const char *buf, size_t count)
  561. {
  562. unsigned long tmp;
  563. unsigned char val;
  564. unsigned long flags;
  565. sscanf(buf, "%lX", &tmp);
  566. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  567. val = (unsigned char)tmp;
  568. spin_lock_irqsave(&event_lock, flags);
  569. SET_PORT_BITS(TLCLK_REG0, 0xcf, val);
  570. spin_unlock_irqrestore(&event_lock, flags);
  571. return strnlen(buf, count);
  572. }
  573. static DEVICE_ATTR(mode_select, (S_IWUSR|S_IWGRP), NULL, store_mode_select);
  574. static ssize_t store_reset (struct device *d,
  575. struct device_attribute *attr, const char *buf, size_t count)
  576. {
  577. unsigned long tmp;
  578. unsigned char val;
  579. unsigned long flags;
  580. sscanf(buf, "%lX", &tmp);
  581. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  582. val = (unsigned char)tmp;
  583. spin_lock_irqsave(&event_lock, flags);
  584. SET_PORT_BITS(TLCLK_REG4, 0xfd, val);
  585. spin_unlock_irqrestore(&event_lock, flags);
  586. return strnlen(buf, count);
  587. }
  588. static DEVICE_ATTR(reset, (S_IWUSR|S_IWGRP), NULL, store_reset);
  589. static struct attribute *tlclk_sysfs_entries[] = {
  590. &dev_attr_current_ref.attr,
  591. &dev_attr_telclock_version.attr,
  592. &dev_attr_alarms.attr,
  593. &dev_attr_received_ref_clk3a.attr,
  594. &dev_attr_received_ref_clk3b.attr,
  595. &dev_attr_enable_clk3a_output.attr,
  596. &dev_attr_enable_clk3b_output.attr,
  597. &dev_attr_enable_clkb1_output.attr,
  598. &dev_attr_enable_clka1_output.attr,
  599. &dev_attr_enable_clkb0_output.attr,
  600. &dev_attr_enable_clka0_output.attr,
  601. &dev_attr_select_amcb1_transmit_clock.attr,
  602. &dev_attr_select_amcb2_transmit_clock.attr,
  603. &dev_attr_select_redundant_clock.attr,
  604. &dev_attr_select_ref_frequency.attr,
  605. &dev_attr_filter_select.attr,
  606. &dev_attr_hardware_switching_mode.attr,
  607. &dev_attr_hardware_switching.attr,
  608. &dev_attr_refalign.attr,
  609. &dev_attr_mode_select.attr,
  610. &dev_attr_reset.attr,
  611. NULL
  612. };
  613. static const struct attribute_group tlclk_attribute_group = {
  614. .name = NULL, /* put in device directory */
  615. .attrs = tlclk_sysfs_entries,
  616. };
  617. static struct platform_device *tlclk_device;
  618. static int __init tlclk_init(void)
  619. {
  620. int ret;
  621. telclk_interrupt = (inb(TLCLK_REG7) & 0x0f);
  622. alarm_events = kzalloc( sizeof(struct tlclk_alarms), GFP_KERNEL);
  623. if (!alarm_events) {
  624. ret = -ENOMEM;
  625. goto out1;
  626. }
  627. ret = register_chrdev(tlclk_major, "telco_clock", &tlclk_fops);
  628. if (ret < 0) {
  629. printk(KERN_ERR "tlclk: can't get major %d.\n", tlclk_major);
  630. kfree(alarm_events);
  631. return ret;
  632. }
  633. tlclk_major = ret;
  634. /* Read telecom clock IRQ number (Set by BIOS) */
  635. if (!request_region(TLCLK_BASE, 8, "telco_clock")) {
  636. printk(KERN_ERR "tlclk: request_region 0x%X failed.\n",
  637. TLCLK_BASE);
  638. ret = -EBUSY;
  639. goto out2;
  640. }
  641. if (0x0F == telclk_interrupt ) { /* not MCPBL0010 ? */
  642. printk(KERN_ERR "telclk_interrupt = 0x%x non-mcpbl0010 hw.\n",
  643. telclk_interrupt);
  644. ret = -ENXIO;
  645. goto out3;
  646. }
  647. timer_setup(&switchover_timer, switchover_timeout, 0);
  648. ret = misc_register(&tlclk_miscdev);
  649. if (ret < 0) {
  650. printk(KERN_ERR "tlclk: misc_register returns %d.\n", ret);
  651. goto out3;
  652. }
  653. tlclk_device = platform_device_register_simple("telco_clock",
  654. -1, NULL, 0);
  655. if (IS_ERR(tlclk_device)) {
  656. printk(KERN_ERR "tlclk: platform_device_register failed.\n");
  657. ret = PTR_ERR(tlclk_device);
  658. goto out4;
  659. }
  660. ret = sysfs_create_group(&tlclk_device->dev.kobj,
  661. &tlclk_attribute_group);
  662. if (ret) {
  663. printk(KERN_ERR "tlclk: failed to create sysfs device attributes.\n");
  664. goto out5;
  665. }
  666. return 0;
  667. out5:
  668. platform_device_unregister(tlclk_device);
  669. out4:
  670. misc_deregister(&tlclk_miscdev);
  671. out3:
  672. release_region(TLCLK_BASE, 8);
  673. out2:
  674. kfree(alarm_events);
  675. unregister_chrdev(tlclk_major, "telco_clock");
  676. out1:
  677. return ret;
  678. }
  679. static void __exit tlclk_cleanup(void)
  680. {
  681. sysfs_remove_group(&tlclk_device->dev.kobj, &tlclk_attribute_group);
  682. platform_device_unregister(tlclk_device);
  683. misc_deregister(&tlclk_miscdev);
  684. unregister_chrdev(tlclk_major, "telco_clock");
  685. release_region(TLCLK_BASE, 8);
  686. del_timer_sync(&switchover_timer);
  687. kfree(alarm_events);
  688. }
  689. static void switchover_timeout(struct timer_list *unused)
  690. {
  691. unsigned long flags = tlclk_timer_data;
  692. if ((flags & 1)) {
  693. if ((inb(TLCLK_REG1) & 0x08) != (flags & 0x08))
  694. alarm_events->switchover_primary++;
  695. } else {
  696. if ((inb(TLCLK_REG1) & 0x08) != (flags & 0x08))
  697. alarm_events->switchover_secondary++;
  698. }
  699. /* Alarm processing is done, wake up read task */
  700. del_timer(&switchover_timer);
  701. got_event = 1;
  702. wake_up(&wq);
  703. }
  704. static irqreturn_t tlclk_interrupt(int irq, void *dev_id)
  705. {
  706. unsigned long flags;
  707. spin_lock_irqsave(&event_lock, flags);
  708. /* Read and clear interrupt events */
  709. int_events = inb(TLCLK_REG6);
  710. /* Primary_Los changed from 0 to 1 ? */
  711. if (int_events & PRI_LOS_01_MASK) {
  712. if (inb(TLCLK_REG2) & SEC_LOST_MASK)
  713. alarm_events->lost_clocks++;
  714. else
  715. alarm_events->lost_primary_clock++;
  716. }
  717. /* Primary_Los changed from 1 to 0 ? */
  718. if (int_events & PRI_LOS_10_MASK) {
  719. alarm_events->primary_clock_back++;
  720. SET_PORT_BITS(TLCLK_REG1, 0xFE, 1);
  721. }
  722. /* Secondary_Los changed from 0 to 1 ? */
  723. if (int_events & SEC_LOS_01_MASK) {
  724. if (inb(TLCLK_REG2) & PRI_LOST_MASK)
  725. alarm_events->lost_clocks++;
  726. else
  727. alarm_events->lost_secondary_clock++;
  728. }
  729. /* Secondary_Los changed from 1 to 0 ? */
  730. if (int_events & SEC_LOS_10_MASK) {
  731. alarm_events->secondary_clock_back++;
  732. SET_PORT_BITS(TLCLK_REG1, 0xFE, 0);
  733. }
  734. if (int_events & HOLDOVER_10_MASK)
  735. alarm_events->pll_end_holdover++;
  736. if (int_events & UNLOCK_01_MASK)
  737. alarm_events->pll_lost_sync++;
  738. if (int_events & UNLOCK_10_MASK)
  739. alarm_events->pll_sync++;
  740. /* Holdover changed from 0 to 1 ? */
  741. if (int_events & HOLDOVER_01_MASK) {
  742. alarm_events->pll_holdover++;
  743. /* TIMEOUT in ~10ms */
  744. switchover_timer.expires = jiffies + msecs_to_jiffies(10);
  745. tlclk_timer_data = inb(TLCLK_REG1);
  746. mod_timer(&switchover_timer, switchover_timer.expires);
  747. } else {
  748. got_event = 1;
  749. wake_up(&wq);
  750. }
  751. spin_unlock_irqrestore(&event_lock, flags);
  752. return IRQ_HANDLED;
  753. }
  754. module_init(tlclk_init);
  755. module_exit(tlclk_cleanup);