btmrvl_sdio.h 3.3 KB

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  1. /**
  2. * Marvell BT-over-SDIO driver: SDIO interface related definitions
  3. *
  4. * Copyright (C) 2009, Marvell International Ltd.
  5. *
  6. * This software file (the "File") is distributed by Marvell International
  7. * Ltd. under the terms of the GNU General Public License Version 2, June 1991
  8. * (the "License"). You may use, redistribute and/or modify this File in
  9. * accordance with the terms and conditions of the License, a copy of which
  10. * is available by writing to the Free Software Foundation, Inc.,
  11. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
  12. * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
  13. *
  14. *
  15. * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
  16. * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
  17. * ARE EXPRESSLY DISCLAIMED. The License provides additional details about
  18. * this warranty disclaimer.
  19. *
  20. **/
  21. #define SDIO_HEADER_LEN 4
  22. /* SD block size can not bigger than 64 due to buf size limit in firmware */
  23. /* define SD block size for data Tx/Rx */
  24. #define SDIO_BLOCK_SIZE 64
  25. /* Number of blocks for firmware transfer */
  26. #define FIRMWARE_TRANSFER_NBLOCK 2
  27. /* This is for firmware specific length */
  28. #define FW_EXTRA_LEN 36
  29. #define MRVDRV_SIZE_OF_CMD_BUFFER (2 * 1024)
  30. #define MRVDRV_BT_RX_PACKET_BUFFER_SIZE \
  31. (HCI_MAX_FRAME_SIZE + FW_EXTRA_LEN)
  32. #define ALLOC_BUF_SIZE (((max_t (int, MRVDRV_BT_RX_PACKET_BUFFER_SIZE, \
  33. MRVDRV_SIZE_OF_CMD_BUFFER) + SDIO_HEADER_LEN \
  34. + SDIO_BLOCK_SIZE - 1) / SDIO_BLOCK_SIZE) \
  35. * SDIO_BLOCK_SIZE)
  36. /* The number of times to try when polling for status */
  37. #define MAX_POLL_TRIES 100
  38. /* Max retry number of CMD53 write */
  39. #define MAX_WRITE_IOMEM_RETRY 2
  40. /* register bitmasks */
  41. #define HOST_POWER_UP BIT(1)
  42. #define HOST_CMD53_FIN BIT(2)
  43. #define HIM_DISABLE 0xff
  44. #define HIM_ENABLE (BIT(0) | BIT(1))
  45. #define UP_LD_HOST_INT_STATUS BIT(0)
  46. #define DN_LD_HOST_INT_STATUS BIT(1)
  47. #define DN_LD_CARD_RDY BIT(0)
  48. #define CARD_IO_READY BIT(3)
  49. #define FIRMWARE_READY 0xfedc
  50. struct btmrvl_plt_wake_cfg {
  51. int irq_bt;
  52. bool wake_by_bt;
  53. };
  54. struct btmrvl_sdio_card_reg {
  55. u8 cfg;
  56. u8 host_int_mask;
  57. u8 host_intstatus;
  58. u8 card_status;
  59. u8 sq_read_base_addr_a0;
  60. u8 sq_read_base_addr_a1;
  61. u8 card_revision;
  62. u8 card_fw_status0;
  63. u8 card_fw_status1;
  64. u8 card_rx_len;
  65. u8 card_rx_unit;
  66. u8 io_port_0;
  67. u8 io_port_1;
  68. u8 io_port_2;
  69. bool int_read_to_clear;
  70. u8 host_int_rsr;
  71. u8 card_misc_cfg;
  72. u8 fw_dump_ctrl;
  73. u8 fw_dump_start;
  74. u8 fw_dump_end;
  75. };
  76. struct btmrvl_sdio_card {
  77. struct sdio_func *func;
  78. u32 ioport;
  79. const char *helper;
  80. const char *firmware;
  81. const struct btmrvl_sdio_card_reg *reg;
  82. bool support_pscan_win_report;
  83. bool supports_fw_dump;
  84. u16 sd_blksz_fw_dl;
  85. u8 rx_unit;
  86. struct btmrvl_private *priv;
  87. struct device_node *plt_of_node;
  88. struct btmrvl_plt_wake_cfg *plt_wake_cfg;
  89. };
  90. struct btmrvl_sdio_device {
  91. const char *helper;
  92. const char *firmware;
  93. const struct btmrvl_sdio_card_reg *reg;
  94. const bool support_pscan_win_report;
  95. u16 sd_blksz_fw_dl;
  96. bool supports_fw_dump;
  97. };
  98. /* Platform specific DMA alignment */
  99. #define BTSDIO_DMA_ALIGN 8
  100. /* Macros for Data Alignment : size */
  101. #define ALIGN_SZ(p, a) \
  102. (((p) + ((a) - 1)) & ~((a) - 1))
  103. /* Macros for Data Alignment : address */
  104. #define ALIGN_ADDR(p, a) \
  105. ((((unsigned long)(p)) + (((unsigned long)(a)) - 1)) & \
  106. ~(((unsigned long)(a)) - 1))