sata_svw.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * sata_svw.c - ServerWorks / Apple K2 SATA
  4. *
  5. * Maintained by: Benjamin Herrenschmidt <benh@kernel.crashing.org> and
  6. * Jeff Garzik <jgarzik@pobox.com>
  7. * Please ALWAYS copy linux-ide@vger.kernel.org
  8. * on emails.
  9. *
  10. * Copyright 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org>
  11. *
  12. * Bits from Jeff Garzik, Copyright RedHat, Inc.
  13. *
  14. * This driver probably works with non-Apple versions of the
  15. * Broadcom chipset...
  16. *
  17. * libata documentation is available via 'make {ps|pdf}docs',
  18. * as Documentation/driver-api/libata.rst
  19. *
  20. * Hardware documentation available under NDA.
  21. */
  22. #include <linux/kernel.h>
  23. #include <linux/module.h>
  24. #include <linux/pci.h>
  25. #include <linux/blkdev.h>
  26. #include <linux/delay.h>
  27. #include <linux/interrupt.h>
  28. #include <linux/device.h>
  29. #include <scsi/scsi_host.h>
  30. #include <scsi/scsi_cmnd.h>
  31. #include <scsi/scsi.h>
  32. #include <linux/libata.h>
  33. #include <linux/of.h>
  34. #define DRV_NAME "sata_svw"
  35. #define DRV_VERSION "2.3"
  36. enum {
  37. /* ap->flags bits */
  38. K2_FLAG_SATA_8_PORTS = (1 << 24),
  39. K2_FLAG_NO_ATAPI_DMA = (1 << 25),
  40. K2_FLAG_BAR_POS_3 = (1 << 26),
  41. /* Taskfile registers offsets */
  42. K2_SATA_TF_CMD_OFFSET = 0x00,
  43. K2_SATA_TF_DATA_OFFSET = 0x00,
  44. K2_SATA_TF_ERROR_OFFSET = 0x04,
  45. K2_SATA_TF_NSECT_OFFSET = 0x08,
  46. K2_SATA_TF_LBAL_OFFSET = 0x0c,
  47. K2_SATA_TF_LBAM_OFFSET = 0x10,
  48. K2_SATA_TF_LBAH_OFFSET = 0x14,
  49. K2_SATA_TF_DEVICE_OFFSET = 0x18,
  50. K2_SATA_TF_CMDSTAT_OFFSET = 0x1c,
  51. K2_SATA_TF_CTL_OFFSET = 0x20,
  52. /* DMA base */
  53. K2_SATA_DMA_CMD_OFFSET = 0x30,
  54. /* SCRs base */
  55. K2_SATA_SCR_STATUS_OFFSET = 0x40,
  56. K2_SATA_SCR_ERROR_OFFSET = 0x44,
  57. K2_SATA_SCR_CONTROL_OFFSET = 0x48,
  58. /* Others */
  59. K2_SATA_SICR1_OFFSET = 0x80,
  60. K2_SATA_SICR2_OFFSET = 0x84,
  61. K2_SATA_SIM_OFFSET = 0x88,
  62. /* Port stride */
  63. K2_SATA_PORT_OFFSET = 0x100,
  64. chip_svw4 = 0,
  65. chip_svw8 = 1,
  66. chip_svw42 = 2, /* bar 3 */
  67. chip_svw43 = 3, /* bar 5 */
  68. };
  69. static u8 k2_stat_check_status(struct ata_port *ap);
  70. static int k2_sata_check_atapi_dma(struct ata_queued_cmd *qc)
  71. {
  72. u8 cmnd = qc->scsicmd->cmnd[0];
  73. if (qc->ap->flags & K2_FLAG_NO_ATAPI_DMA)
  74. return -1; /* ATAPI DMA not supported */
  75. else {
  76. switch (cmnd) {
  77. case READ_10:
  78. case READ_12:
  79. case READ_16:
  80. case WRITE_10:
  81. case WRITE_12:
  82. case WRITE_16:
  83. return 0;
  84. default:
  85. return -1;
  86. }
  87. }
  88. }
  89. static int k2_sata_scr_read(struct ata_link *link,
  90. unsigned int sc_reg, u32 *val)
  91. {
  92. if (sc_reg > SCR_CONTROL)
  93. return -EINVAL;
  94. *val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 4));
  95. return 0;
  96. }
  97. static int k2_sata_scr_write(struct ata_link *link,
  98. unsigned int sc_reg, u32 val)
  99. {
  100. if (sc_reg > SCR_CONTROL)
  101. return -EINVAL;
  102. writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4));
  103. return 0;
  104. }
  105. static int k2_sata_softreset(struct ata_link *link,
  106. unsigned int *class, unsigned long deadline)
  107. {
  108. u8 dmactl;
  109. void __iomem *mmio = link->ap->ioaddr.bmdma_addr;
  110. dmactl = readb(mmio + ATA_DMA_CMD);
  111. /* Clear the start bit */
  112. if (dmactl & ATA_DMA_START) {
  113. dmactl &= ~ATA_DMA_START;
  114. writeb(dmactl, mmio + ATA_DMA_CMD);
  115. }
  116. return ata_sff_softreset(link, class, deadline);
  117. }
  118. static int k2_sata_hardreset(struct ata_link *link,
  119. unsigned int *class, unsigned long deadline)
  120. {
  121. u8 dmactl;
  122. void __iomem *mmio = link->ap->ioaddr.bmdma_addr;
  123. dmactl = readb(mmio + ATA_DMA_CMD);
  124. /* Clear the start bit */
  125. if (dmactl & ATA_DMA_START) {
  126. dmactl &= ~ATA_DMA_START;
  127. writeb(dmactl, mmio + ATA_DMA_CMD);
  128. }
  129. return sata_sff_hardreset(link, class, deadline);
  130. }
  131. static void k2_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
  132. {
  133. struct ata_ioports *ioaddr = &ap->ioaddr;
  134. unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
  135. if (tf->ctl != ap->last_ctl) {
  136. writeb(tf->ctl, ioaddr->ctl_addr);
  137. ap->last_ctl = tf->ctl;
  138. ata_wait_idle(ap);
  139. }
  140. if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
  141. writew(tf->feature | (((u16)tf->hob_feature) << 8),
  142. ioaddr->feature_addr);
  143. writew(tf->nsect | (((u16)tf->hob_nsect) << 8),
  144. ioaddr->nsect_addr);
  145. writew(tf->lbal | (((u16)tf->hob_lbal) << 8),
  146. ioaddr->lbal_addr);
  147. writew(tf->lbam | (((u16)tf->hob_lbam) << 8),
  148. ioaddr->lbam_addr);
  149. writew(tf->lbah | (((u16)tf->hob_lbah) << 8),
  150. ioaddr->lbah_addr);
  151. } else if (is_addr) {
  152. writew(tf->feature, ioaddr->feature_addr);
  153. writew(tf->nsect, ioaddr->nsect_addr);
  154. writew(tf->lbal, ioaddr->lbal_addr);
  155. writew(tf->lbam, ioaddr->lbam_addr);
  156. writew(tf->lbah, ioaddr->lbah_addr);
  157. }
  158. if (tf->flags & ATA_TFLAG_DEVICE)
  159. writeb(tf->device, ioaddr->device_addr);
  160. ata_wait_idle(ap);
  161. }
  162. static void k2_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
  163. {
  164. struct ata_ioports *ioaddr = &ap->ioaddr;
  165. u16 nsect, lbal, lbam, lbah, feature;
  166. tf->command = k2_stat_check_status(ap);
  167. tf->device = readw(ioaddr->device_addr);
  168. feature = readw(ioaddr->error_addr);
  169. nsect = readw(ioaddr->nsect_addr);
  170. lbal = readw(ioaddr->lbal_addr);
  171. lbam = readw(ioaddr->lbam_addr);
  172. lbah = readw(ioaddr->lbah_addr);
  173. tf->feature = feature;
  174. tf->nsect = nsect;
  175. tf->lbal = lbal;
  176. tf->lbam = lbam;
  177. tf->lbah = lbah;
  178. if (tf->flags & ATA_TFLAG_LBA48) {
  179. tf->hob_feature = feature >> 8;
  180. tf->hob_nsect = nsect >> 8;
  181. tf->hob_lbal = lbal >> 8;
  182. tf->hob_lbam = lbam >> 8;
  183. tf->hob_lbah = lbah >> 8;
  184. }
  185. }
  186. /**
  187. * k2_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction (MMIO)
  188. * @qc: Info associated with this ATA transaction.
  189. *
  190. * LOCKING:
  191. * spin_lock_irqsave(host lock)
  192. */
  193. static void k2_bmdma_setup_mmio(struct ata_queued_cmd *qc)
  194. {
  195. struct ata_port *ap = qc->ap;
  196. unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
  197. u8 dmactl;
  198. void __iomem *mmio = ap->ioaddr.bmdma_addr;
  199. /* load PRD table addr. */
  200. mb(); /* make sure PRD table writes are visible to controller */
  201. writel(ap->bmdma_prd_dma, mmio + ATA_DMA_TABLE_OFS);
  202. /* specify data direction, triple-check start bit is clear */
  203. dmactl = readb(mmio + ATA_DMA_CMD);
  204. dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
  205. if (!rw)
  206. dmactl |= ATA_DMA_WR;
  207. writeb(dmactl, mmio + ATA_DMA_CMD);
  208. /* issue r/w command if this is not a ATA DMA command*/
  209. if (qc->tf.protocol != ATA_PROT_DMA)
  210. ap->ops->sff_exec_command(ap, &qc->tf);
  211. }
  212. /**
  213. * k2_bmdma_start_mmio - Start a PCI IDE BMDMA transaction (MMIO)
  214. * @qc: Info associated with this ATA transaction.
  215. *
  216. * LOCKING:
  217. * spin_lock_irqsave(host lock)
  218. */
  219. static void k2_bmdma_start_mmio(struct ata_queued_cmd *qc)
  220. {
  221. struct ata_port *ap = qc->ap;
  222. void __iomem *mmio = ap->ioaddr.bmdma_addr;
  223. u8 dmactl;
  224. /* start host DMA transaction */
  225. dmactl = readb(mmio + ATA_DMA_CMD);
  226. writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD);
  227. /* This works around possible data corruption.
  228. On certain SATA controllers that can be seen when the r/w
  229. command is given to the controller before the host DMA is
  230. started.
  231. On a Read command, the controller would initiate the
  232. command to the drive even before it sees the DMA
  233. start. When there are very fast drives connected to the
  234. controller, or when the data request hits in the drive
  235. cache, there is the possibility that the drive returns a
  236. part or all of the requested data to the controller before
  237. the DMA start is issued. In this case, the controller
  238. would become confused as to what to do with the data. In
  239. the worst case when all the data is returned back to the
  240. controller, the controller could hang. In other cases it
  241. could return partial data returning in data
  242. corruption. This problem has been seen in PPC systems and
  243. can also appear on an system with very fast disks, where
  244. the SATA controller is sitting behind a number of bridges,
  245. and hence there is significant latency between the r/w
  246. command and the start command. */
  247. /* issue r/w command if the access is to ATA */
  248. if (qc->tf.protocol == ATA_PROT_DMA)
  249. ap->ops->sff_exec_command(ap, &qc->tf);
  250. }
  251. static u8 k2_stat_check_status(struct ata_port *ap)
  252. {
  253. return readl(ap->ioaddr.status_addr);
  254. }
  255. static int k2_sata_show_info(struct seq_file *m, struct Scsi_Host *shost)
  256. {
  257. struct ata_port *ap;
  258. struct device_node *np;
  259. int index;
  260. /* Find the ata_port */
  261. ap = ata_shost_to_port(shost);
  262. if (ap == NULL)
  263. return 0;
  264. /* Find the OF node for the PCI device proper */
  265. np = pci_device_to_OF_node(to_pci_dev(ap->host->dev));
  266. if (np == NULL)
  267. return 0;
  268. /* Match it to a port node */
  269. index = (ap == ap->host->ports[0]) ? 0 : 1;
  270. for (np = np->child; np != NULL; np = np->sibling) {
  271. const u32 *reg = of_get_property(np, "reg", NULL);
  272. if (!reg)
  273. continue;
  274. if (index == *reg) {
  275. seq_printf(m, "devspec: %pOF\n", np);
  276. break;
  277. }
  278. }
  279. return 0;
  280. }
  281. static struct scsi_host_template k2_sata_sht = {
  282. ATA_BMDMA_SHT(DRV_NAME),
  283. .show_info = k2_sata_show_info,
  284. };
  285. static struct ata_port_operations k2_sata_ops = {
  286. .inherits = &ata_bmdma_port_ops,
  287. .softreset = k2_sata_softreset,
  288. .hardreset = k2_sata_hardreset,
  289. .sff_tf_load = k2_sata_tf_load,
  290. .sff_tf_read = k2_sata_tf_read,
  291. .sff_check_status = k2_stat_check_status,
  292. .check_atapi_dma = k2_sata_check_atapi_dma,
  293. .bmdma_setup = k2_bmdma_setup_mmio,
  294. .bmdma_start = k2_bmdma_start_mmio,
  295. .scr_read = k2_sata_scr_read,
  296. .scr_write = k2_sata_scr_write,
  297. };
  298. static const struct ata_port_info k2_port_info[] = {
  299. /* chip_svw4 */
  300. {
  301. .flags = ATA_FLAG_SATA | K2_FLAG_NO_ATAPI_DMA,
  302. .pio_mask = ATA_PIO4,
  303. .mwdma_mask = ATA_MWDMA2,
  304. .udma_mask = ATA_UDMA6,
  305. .port_ops = &k2_sata_ops,
  306. },
  307. /* chip_svw8 */
  308. {
  309. .flags = ATA_FLAG_SATA | K2_FLAG_NO_ATAPI_DMA |
  310. K2_FLAG_SATA_8_PORTS,
  311. .pio_mask = ATA_PIO4,
  312. .mwdma_mask = ATA_MWDMA2,
  313. .udma_mask = ATA_UDMA6,
  314. .port_ops = &k2_sata_ops,
  315. },
  316. /* chip_svw42 */
  317. {
  318. .flags = ATA_FLAG_SATA | K2_FLAG_BAR_POS_3,
  319. .pio_mask = ATA_PIO4,
  320. .mwdma_mask = ATA_MWDMA2,
  321. .udma_mask = ATA_UDMA6,
  322. .port_ops = &k2_sata_ops,
  323. },
  324. /* chip_svw43 */
  325. {
  326. .flags = ATA_FLAG_SATA,
  327. .pio_mask = ATA_PIO4,
  328. .mwdma_mask = ATA_MWDMA2,
  329. .udma_mask = ATA_UDMA6,
  330. .port_ops = &k2_sata_ops,
  331. },
  332. };
  333. static void k2_sata_setup_port(struct ata_ioports *port, void __iomem *base)
  334. {
  335. port->cmd_addr = base + K2_SATA_TF_CMD_OFFSET;
  336. port->data_addr = base + K2_SATA_TF_DATA_OFFSET;
  337. port->feature_addr =
  338. port->error_addr = base + K2_SATA_TF_ERROR_OFFSET;
  339. port->nsect_addr = base + K2_SATA_TF_NSECT_OFFSET;
  340. port->lbal_addr = base + K2_SATA_TF_LBAL_OFFSET;
  341. port->lbam_addr = base + K2_SATA_TF_LBAM_OFFSET;
  342. port->lbah_addr = base + K2_SATA_TF_LBAH_OFFSET;
  343. port->device_addr = base + K2_SATA_TF_DEVICE_OFFSET;
  344. port->command_addr =
  345. port->status_addr = base + K2_SATA_TF_CMDSTAT_OFFSET;
  346. port->altstatus_addr =
  347. port->ctl_addr = base + K2_SATA_TF_CTL_OFFSET;
  348. port->bmdma_addr = base + K2_SATA_DMA_CMD_OFFSET;
  349. port->scr_addr = base + K2_SATA_SCR_STATUS_OFFSET;
  350. }
  351. static int k2_sata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
  352. {
  353. const struct ata_port_info *ppi[] =
  354. { &k2_port_info[ent->driver_data], NULL };
  355. struct ata_host *host;
  356. void __iomem *mmio_base;
  357. int n_ports, i, rc, bar_pos;
  358. ata_print_version_once(&pdev->dev, DRV_VERSION);
  359. /* allocate host */
  360. n_ports = 4;
  361. if (ppi[0]->flags & K2_FLAG_SATA_8_PORTS)
  362. n_ports = 8;
  363. host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
  364. if (!host)
  365. return -ENOMEM;
  366. bar_pos = 5;
  367. if (ppi[0]->flags & K2_FLAG_BAR_POS_3)
  368. bar_pos = 3;
  369. /*
  370. * If this driver happens to only be useful on Apple's K2, then
  371. * we should check that here as it has a normal Serverworks ID
  372. */
  373. rc = pcim_enable_device(pdev);
  374. if (rc)
  375. return rc;
  376. /*
  377. * Check if we have resources mapped at all (second function may
  378. * have been disabled by firmware)
  379. */
  380. if (pci_resource_len(pdev, bar_pos) == 0) {
  381. /* In IDE mode we need to pin the device to ensure that
  382. pcim_release does not clear the busmaster bit in config
  383. space, clearing causes busmaster DMA to fail on
  384. ports 3 & 4 */
  385. pcim_pin_device(pdev);
  386. return -ENODEV;
  387. }
  388. /* Request and iomap PCI regions */
  389. rc = pcim_iomap_regions(pdev, 1 << bar_pos, DRV_NAME);
  390. if (rc == -EBUSY)
  391. pcim_pin_device(pdev);
  392. if (rc)
  393. return rc;
  394. host->iomap = pcim_iomap_table(pdev);
  395. mmio_base = host->iomap[bar_pos];
  396. /* different controllers have different number of ports - currently 4 or 8 */
  397. /* All ports are on the same function. Multi-function device is no
  398. * longer available. This should not be seen in any system. */
  399. for (i = 0; i < host->n_ports; i++) {
  400. struct ata_port *ap = host->ports[i];
  401. unsigned int offset = i * K2_SATA_PORT_OFFSET;
  402. k2_sata_setup_port(&ap->ioaddr, mmio_base + offset);
  403. ata_port_pbar_desc(ap, 5, -1, "mmio");
  404. ata_port_pbar_desc(ap, 5, offset, "port");
  405. }
  406. rc = dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK);
  407. if (rc)
  408. return rc;
  409. /* Clear a magic bit in SCR1 according to Darwin, those help
  410. * some funky seagate drives (though so far, those were already
  411. * set by the firmware on the machines I had access to)
  412. */
  413. writel(readl(mmio_base + K2_SATA_SICR1_OFFSET) & ~0x00040000,
  414. mmio_base + K2_SATA_SICR1_OFFSET);
  415. /* Clear SATA error & interrupts we don't use */
  416. writel(0xffffffff, mmio_base + K2_SATA_SCR_ERROR_OFFSET);
  417. writel(0x0, mmio_base + K2_SATA_SIM_OFFSET);
  418. pci_set_master(pdev);
  419. return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
  420. IRQF_SHARED, &k2_sata_sht);
  421. }
  422. /* 0x240 is device ID for Apple K2 device
  423. * 0x241 is device ID for Serverworks Frodo4
  424. * 0x242 is device ID for Serverworks Frodo8
  425. * 0x24a is device ID for BCM5785 (aka HT1000) HT southbridge integrated SATA
  426. * controller
  427. * */
  428. static const struct pci_device_id k2_sata_pci_tbl[] = {
  429. { PCI_VDEVICE(SERVERWORKS, 0x0240), chip_svw4 },
  430. { PCI_VDEVICE(SERVERWORKS, 0x0241), chip_svw8 },
  431. { PCI_VDEVICE(SERVERWORKS, 0x0242), chip_svw4 },
  432. { PCI_VDEVICE(SERVERWORKS, 0x024a), chip_svw4 },
  433. { PCI_VDEVICE(SERVERWORKS, 0x024b), chip_svw4 },
  434. { PCI_VDEVICE(SERVERWORKS, 0x0410), chip_svw42 },
  435. { PCI_VDEVICE(SERVERWORKS, 0x0411), chip_svw43 },
  436. { }
  437. };
  438. static struct pci_driver k2_sata_pci_driver = {
  439. .name = DRV_NAME,
  440. .id_table = k2_sata_pci_tbl,
  441. .probe = k2_sata_init_one,
  442. .remove = ata_pci_remove_one,
  443. };
  444. module_pci_driver(k2_sata_pci_driver);
  445. MODULE_AUTHOR("Benjamin Herrenschmidt");
  446. MODULE_DESCRIPTION("low-level driver for K2 SATA controller");
  447. MODULE_LICENSE("GPL");
  448. MODULE_DEVICE_TABLE(pci, k2_sata_pci_tbl);
  449. MODULE_VERSION(DRV_VERSION);