sata_sis.c 7.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * sata_sis.c - Silicon Integrated Systems SATA
  4. *
  5. * Maintained by: Uwe Koziolek
  6. * Please ALWAYS copy linux-ide@vger.kernel.org
  7. * on emails.
  8. *
  9. * Copyright 2004 Uwe Koziolek
  10. *
  11. * libata documentation is available via 'make {ps|pdf}docs',
  12. * as Documentation/driver-api/libata.rst
  13. *
  14. * Hardware documentation available under NDA.
  15. */
  16. #include <linux/kernel.h>
  17. #include <linux/module.h>
  18. #include <linux/pci.h>
  19. #include <linux/blkdev.h>
  20. #include <linux/delay.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/device.h>
  23. #include <scsi/scsi_host.h>
  24. #include <linux/libata.h>
  25. #include "sis.h"
  26. #define DRV_NAME "sata_sis"
  27. #define DRV_VERSION "1.0"
  28. enum {
  29. sis_180 = 0,
  30. SIS_SCR_PCI_BAR = 5,
  31. /* PCI configuration registers */
  32. SIS_GENCTL = 0x54, /* IDE General Control register */
  33. SIS_SCR_BASE = 0xc0, /* sata0 phy SCR registers */
  34. SIS180_SATA1_OFS = 0x10, /* offset from sata0->sata1 phy regs */
  35. SIS182_SATA1_OFS = 0x20, /* offset from sata0->sata1 phy regs */
  36. SIS_PMR = 0x90, /* port mapping register */
  37. SIS_PMR_COMBINED = 0x30,
  38. /* random bits */
  39. SIS_FLAG_CFGSCR = (1 << 30), /* host flag: SCRs via PCI cfg */
  40. GENCTL_IOMAPPED_SCR = (1 << 26), /* if set, SCRs are in IO space */
  41. };
  42. static int sis_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
  43. static int sis_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
  44. static int sis_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
  45. static const struct pci_device_id sis_pci_tbl[] = {
  46. { PCI_VDEVICE(SI, 0x0180), sis_180 }, /* SiS 964/180 */
  47. { PCI_VDEVICE(SI, 0x0181), sis_180 }, /* SiS 964/180 */
  48. { PCI_VDEVICE(SI, 0x0182), sis_180 }, /* SiS 965/965L */
  49. { PCI_VDEVICE(SI, 0x0183), sis_180 }, /* SiS 965/965L */
  50. { PCI_VDEVICE(SI, 0x1182), sis_180 }, /* SiS 966/680 */
  51. { PCI_VDEVICE(SI, 0x1183), sis_180 }, /* SiS 966/966L/968/680 */
  52. { } /* terminate list */
  53. };
  54. static struct pci_driver sis_pci_driver = {
  55. .name = DRV_NAME,
  56. .id_table = sis_pci_tbl,
  57. .probe = sis_init_one,
  58. .remove = ata_pci_remove_one,
  59. #ifdef CONFIG_PM_SLEEP
  60. .suspend = ata_pci_device_suspend,
  61. .resume = ata_pci_device_resume,
  62. #endif
  63. };
  64. static struct scsi_host_template sis_sht = {
  65. ATA_BMDMA_SHT(DRV_NAME),
  66. };
  67. static struct ata_port_operations sis_ops = {
  68. .inherits = &ata_bmdma_port_ops,
  69. .scr_read = sis_scr_read,
  70. .scr_write = sis_scr_write,
  71. };
  72. static const struct ata_port_info sis_port_info = {
  73. .flags = ATA_FLAG_SATA,
  74. .pio_mask = ATA_PIO4,
  75. .mwdma_mask = ATA_MWDMA2,
  76. .udma_mask = ATA_UDMA6,
  77. .port_ops = &sis_ops,
  78. };
  79. MODULE_AUTHOR("Uwe Koziolek");
  80. MODULE_DESCRIPTION("low-level driver for Silicon Integrated Systems SATA controller");
  81. MODULE_LICENSE("GPL");
  82. MODULE_DEVICE_TABLE(pci, sis_pci_tbl);
  83. MODULE_VERSION(DRV_VERSION);
  84. static unsigned int get_scr_cfg_addr(struct ata_link *link, unsigned int sc_reg)
  85. {
  86. struct ata_port *ap = link->ap;
  87. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  88. unsigned int addr = SIS_SCR_BASE + (4 * sc_reg);
  89. u8 pmr;
  90. if (ap->port_no) {
  91. switch (pdev->device) {
  92. case 0x0180:
  93. case 0x0181:
  94. pci_read_config_byte(pdev, SIS_PMR, &pmr);
  95. if ((pmr & SIS_PMR_COMBINED) == 0)
  96. addr += SIS180_SATA1_OFS;
  97. break;
  98. case 0x0182:
  99. case 0x0183:
  100. case 0x1182:
  101. addr += SIS182_SATA1_OFS;
  102. break;
  103. }
  104. }
  105. if (link->pmp)
  106. addr += 0x10;
  107. return addr;
  108. }
  109. static u32 sis_scr_cfg_read(struct ata_link *link,
  110. unsigned int sc_reg, u32 *val)
  111. {
  112. struct pci_dev *pdev = to_pci_dev(link->ap->host->dev);
  113. unsigned int cfg_addr = get_scr_cfg_addr(link, sc_reg);
  114. if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */
  115. return -EINVAL;
  116. pci_read_config_dword(pdev, cfg_addr, val);
  117. return 0;
  118. }
  119. static int sis_scr_cfg_write(struct ata_link *link,
  120. unsigned int sc_reg, u32 val)
  121. {
  122. struct pci_dev *pdev = to_pci_dev(link->ap->host->dev);
  123. unsigned int cfg_addr = get_scr_cfg_addr(link, sc_reg);
  124. pci_write_config_dword(pdev, cfg_addr, val);
  125. return 0;
  126. }
  127. static int sis_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
  128. {
  129. struct ata_port *ap = link->ap;
  130. void __iomem *base = ap->ioaddr.scr_addr + link->pmp * 0x10;
  131. if (sc_reg > SCR_CONTROL)
  132. return -EINVAL;
  133. if (ap->flags & SIS_FLAG_CFGSCR)
  134. return sis_scr_cfg_read(link, sc_reg, val);
  135. *val = ioread32(base + sc_reg * 4);
  136. return 0;
  137. }
  138. static int sis_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
  139. {
  140. struct ata_port *ap = link->ap;
  141. void __iomem *base = ap->ioaddr.scr_addr + link->pmp * 0x10;
  142. if (sc_reg > SCR_CONTROL)
  143. return -EINVAL;
  144. if (ap->flags & SIS_FLAG_CFGSCR)
  145. return sis_scr_cfg_write(link, sc_reg, val);
  146. iowrite32(val, base + (sc_reg * 4));
  147. return 0;
  148. }
  149. static int sis_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
  150. {
  151. struct ata_port_info pi = sis_port_info;
  152. const struct ata_port_info *ppi[] = { &pi, &pi };
  153. struct ata_host *host;
  154. u32 genctl, val;
  155. u8 pmr;
  156. u8 port2_start = 0x20;
  157. int i, rc;
  158. ata_print_version_once(&pdev->dev, DRV_VERSION);
  159. rc = pcim_enable_device(pdev);
  160. if (rc)
  161. return rc;
  162. /* check and see if the SCRs are in IO space or PCI cfg space */
  163. pci_read_config_dword(pdev, SIS_GENCTL, &genctl);
  164. if ((genctl & GENCTL_IOMAPPED_SCR) == 0)
  165. pi.flags |= SIS_FLAG_CFGSCR;
  166. /* if hardware thinks SCRs are in IO space, but there are
  167. * no IO resources assigned, change to PCI cfg space.
  168. */
  169. if ((!(pi.flags & SIS_FLAG_CFGSCR)) &&
  170. ((pci_resource_start(pdev, SIS_SCR_PCI_BAR) == 0) ||
  171. (pci_resource_len(pdev, SIS_SCR_PCI_BAR) < 128))) {
  172. genctl &= ~GENCTL_IOMAPPED_SCR;
  173. pci_write_config_dword(pdev, SIS_GENCTL, genctl);
  174. pi.flags |= SIS_FLAG_CFGSCR;
  175. }
  176. pci_read_config_byte(pdev, SIS_PMR, &pmr);
  177. switch (ent->device) {
  178. case 0x0180:
  179. case 0x0181:
  180. /* The PATA-handling is provided by pata_sis */
  181. switch (pmr & 0x30) {
  182. case 0x10:
  183. ppi[1] = &sis_info133_for_sata;
  184. break;
  185. case 0x30:
  186. ppi[0] = &sis_info133_for_sata;
  187. break;
  188. }
  189. if ((pmr & SIS_PMR_COMBINED) == 0) {
  190. dev_info(&pdev->dev,
  191. "Detected SiS 180/181/964 chipset in SATA mode\n");
  192. port2_start = 64;
  193. } else {
  194. dev_info(&pdev->dev,
  195. "Detected SiS 180/181 chipset in combined mode\n");
  196. port2_start = 0;
  197. pi.flags |= ATA_FLAG_SLAVE_POSS;
  198. }
  199. break;
  200. case 0x0182:
  201. case 0x0183:
  202. pci_read_config_dword(pdev, 0x6C, &val);
  203. if (val & (1L << 31)) {
  204. dev_info(&pdev->dev, "Detected SiS 182/965 chipset\n");
  205. pi.flags |= ATA_FLAG_SLAVE_POSS;
  206. } else {
  207. dev_info(&pdev->dev, "Detected SiS 182/965L chipset\n");
  208. }
  209. break;
  210. case 0x1182:
  211. dev_info(&pdev->dev,
  212. "Detected SiS 1182/966/680 SATA controller\n");
  213. pi.flags |= ATA_FLAG_SLAVE_POSS;
  214. break;
  215. case 0x1183:
  216. dev_info(&pdev->dev,
  217. "Detected SiS 1183/966/966L/968/680 controller in PATA mode\n");
  218. ppi[0] = &sis_info133_for_sata;
  219. ppi[1] = &sis_info133_for_sata;
  220. break;
  221. }
  222. rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
  223. if (rc)
  224. return rc;
  225. for (i = 0; i < 2; i++) {
  226. struct ata_port *ap = host->ports[i];
  227. if (ap->flags & ATA_FLAG_SATA &&
  228. ap->flags & ATA_FLAG_SLAVE_POSS) {
  229. rc = ata_slave_link_init(ap);
  230. if (rc)
  231. return rc;
  232. }
  233. }
  234. if (!(pi.flags & SIS_FLAG_CFGSCR)) {
  235. void __iomem *mmio;
  236. rc = pcim_iomap_regions(pdev, 1 << SIS_SCR_PCI_BAR, DRV_NAME);
  237. if (rc)
  238. return rc;
  239. mmio = host->iomap[SIS_SCR_PCI_BAR];
  240. host->ports[0]->ioaddr.scr_addr = mmio;
  241. host->ports[1]->ioaddr.scr_addr = mmio + port2_start;
  242. }
  243. pci_set_master(pdev);
  244. pci_intx(pdev, 1);
  245. return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
  246. IRQF_SHARED, &sis_sht);
  247. }
  248. module_pci_driver(sis_pci_driver);