sata_promise.c 33 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * sata_promise.c - Promise SATA
  4. *
  5. * Maintained by: Tejun Heo <tj@kernel.org>
  6. * Mikael Pettersson
  7. * Please ALWAYS copy linux-ide@vger.kernel.org
  8. * on emails.
  9. *
  10. * Copyright 2003-2004 Red Hat, Inc.
  11. *
  12. * libata documentation is available via 'make {ps|pdf}docs',
  13. * as Documentation/driver-api/libata.rst
  14. *
  15. * Hardware information only available under NDA.
  16. */
  17. #include <linux/kernel.h>
  18. #include <linux/module.h>
  19. #include <linux/gfp.h>
  20. #include <linux/pci.h>
  21. #include <linux/blkdev.h>
  22. #include <linux/delay.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/device.h>
  25. #include <scsi/scsi.h>
  26. #include <scsi/scsi_host.h>
  27. #include <scsi/scsi_cmnd.h>
  28. #include <linux/libata.h>
  29. #include "sata_promise.h"
  30. #define DRV_NAME "sata_promise"
  31. #define DRV_VERSION "2.12"
  32. enum {
  33. PDC_MAX_PORTS = 4,
  34. PDC_MMIO_BAR = 3,
  35. PDC_MAX_PRD = LIBATA_MAX_PRD - 1, /* -1 for ASIC PRD bug workaround */
  36. /* host register offsets (from host->iomap[PDC_MMIO_BAR]) */
  37. PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
  38. PDC_FLASH_CTL = 0x44, /* Flash control register */
  39. PDC_PCI_CTL = 0x48, /* PCI control/status reg */
  40. PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
  41. PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */
  42. PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */
  43. PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */
  44. /* per-port ATA register offsets (from ap->ioaddr.cmd_addr) */
  45. PDC_FEATURE = 0x04, /* Feature/Error reg (per port) */
  46. PDC_SECTOR_COUNT = 0x08, /* Sector count reg (per port) */
  47. PDC_SECTOR_NUMBER = 0x0C, /* Sector number reg (per port) */
  48. PDC_CYLINDER_LOW = 0x10, /* Cylinder low reg (per port) */
  49. PDC_CYLINDER_HIGH = 0x14, /* Cylinder high reg (per port) */
  50. PDC_DEVICE = 0x18, /* Device/Head reg (per port) */
  51. PDC_COMMAND = 0x1C, /* Command/status reg (per port) */
  52. PDC_ALTSTATUS = 0x38, /* Alternate-status/device-control reg (per port) */
  53. PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
  54. PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
  55. PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
  56. /* per-port SATA register offsets (from ap->ioaddr.scr_addr) */
  57. PDC_SATA_ERROR = 0x04,
  58. PDC_PHYMODE4 = 0x14,
  59. PDC_LINK_LAYER_ERRORS = 0x6C,
  60. PDC_FPDMA_CTLSTAT = 0xD8,
  61. PDC_INTERNAL_DEBUG_1 = 0xF8, /* also used for PATA */
  62. PDC_INTERNAL_DEBUG_2 = 0xFC, /* also used for PATA */
  63. /* PDC_FPDMA_CTLSTAT bit definitions */
  64. PDC_FPDMA_CTLSTAT_RESET = 1 << 3,
  65. PDC_FPDMA_CTLSTAT_DMASETUP_INT_FLAG = 1 << 10,
  66. PDC_FPDMA_CTLSTAT_SETDB_INT_FLAG = 1 << 11,
  67. /* PDC_GLOBAL_CTL bit definitions */
  68. PDC_PH_ERR = (1 << 8), /* PCI error while loading packet */
  69. PDC_SH_ERR = (1 << 9), /* PCI error while loading S/G table */
  70. PDC_DH_ERR = (1 << 10), /* PCI error while loading data */
  71. PDC2_HTO_ERR = (1 << 12), /* host bus timeout */
  72. PDC2_ATA_HBA_ERR = (1 << 13), /* error during SATA DATA FIS transmission */
  73. PDC2_ATA_DMA_CNT_ERR = (1 << 14), /* DMA DATA FIS size differs from S/G count */
  74. PDC_OVERRUN_ERR = (1 << 19), /* S/G byte count larger than HD requires */
  75. PDC_UNDERRUN_ERR = (1 << 20), /* S/G byte count less than HD requires */
  76. PDC_DRIVE_ERR = (1 << 21), /* drive error */
  77. PDC_PCI_SYS_ERR = (1 << 22), /* PCI system error */
  78. PDC1_PCI_PARITY_ERR = (1 << 23), /* PCI parity error (from SATA150 driver) */
  79. PDC1_ERR_MASK = PDC1_PCI_PARITY_ERR,
  80. PDC2_ERR_MASK = PDC2_HTO_ERR | PDC2_ATA_HBA_ERR |
  81. PDC2_ATA_DMA_CNT_ERR,
  82. PDC_ERR_MASK = PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR |
  83. PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR |
  84. PDC_DRIVE_ERR | PDC_PCI_SYS_ERR |
  85. PDC1_ERR_MASK | PDC2_ERR_MASK,
  86. board_2037x = 0, /* FastTrak S150 TX2plus */
  87. board_2037x_pata = 1, /* FastTrak S150 TX2plus PATA port */
  88. board_20319 = 2, /* FastTrak S150 TX4 */
  89. board_20619 = 3, /* FastTrak TX4000 */
  90. board_2057x = 4, /* SATAII150 Tx2plus */
  91. board_2057x_pata = 5, /* SATAII150 Tx2plus PATA port */
  92. board_40518 = 6, /* SATAII150 Tx4 */
  93. PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */
  94. /* Sequence counter control registers bit definitions */
  95. PDC_SEQCNTRL_INT_MASK = (1 << 5), /* Sequence Interrupt Mask */
  96. /* Feature register values */
  97. PDC_FEATURE_ATAPI_PIO = 0x00, /* ATAPI data xfer by PIO */
  98. PDC_FEATURE_ATAPI_DMA = 0x01, /* ATAPI data xfer by DMA */
  99. /* Device/Head register values */
  100. PDC_DEVICE_SATA = 0xE0, /* Device/Head value for SATA devices */
  101. /* PDC_CTLSTAT bit definitions */
  102. PDC_DMA_ENABLE = (1 << 7),
  103. PDC_IRQ_DISABLE = (1 << 10),
  104. PDC_RESET = (1 << 11), /* HDMA reset */
  105. PDC_COMMON_FLAGS = ATA_FLAG_PIO_POLLING,
  106. /* ap->flags bits */
  107. PDC_FLAG_GEN_II = (1 << 24),
  108. PDC_FLAG_SATA_PATA = (1 << 25), /* supports SATA + PATA */
  109. PDC_FLAG_4_PORTS = (1 << 26), /* 4 ports */
  110. };
  111. struct pdc_port_priv {
  112. u8 *pkt;
  113. dma_addr_t pkt_dma;
  114. };
  115. struct pdc_host_priv {
  116. spinlock_t hard_reset_lock;
  117. };
  118. static int pdc_sata_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
  119. static int pdc_sata_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
  120. static int pdc_ata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
  121. static int pdc_common_port_start(struct ata_port *ap);
  122. static int pdc_sata_port_start(struct ata_port *ap);
  123. static enum ata_completion_errors pdc_qc_prep(struct ata_queued_cmd *qc);
  124. static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
  125. static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
  126. static int pdc_check_atapi_dma(struct ata_queued_cmd *qc);
  127. static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc);
  128. static void pdc_irq_clear(struct ata_port *ap);
  129. static unsigned int pdc_qc_issue(struct ata_queued_cmd *qc);
  130. static void pdc_freeze(struct ata_port *ap);
  131. static void pdc_sata_freeze(struct ata_port *ap);
  132. static void pdc_thaw(struct ata_port *ap);
  133. static void pdc_sata_thaw(struct ata_port *ap);
  134. static int pdc_pata_softreset(struct ata_link *link, unsigned int *class,
  135. unsigned long deadline);
  136. static int pdc_sata_hardreset(struct ata_link *link, unsigned int *class,
  137. unsigned long deadline);
  138. static void pdc_error_handler(struct ata_port *ap);
  139. static void pdc_post_internal_cmd(struct ata_queued_cmd *qc);
  140. static int pdc_pata_cable_detect(struct ata_port *ap);
  141. static struct scsi_host_template pdc_ata_sht = {
  142. ATA_BASE_SHT(DRV_NAME),
  143. .sg_tablesize = PDC_MAX_PRD,
  144. .dma_boundary = ATA_DMA_BOUNDARY,
  145. };
  146. static const struct ata_port_operations pdc_common_ops = {
  147. .inherits = &ata_sff_port_ops,
  148. .sff_tf_load = pdc_tf_load_mmio,
  149. .sff_exec_command = pdc_exec_command_mmio,
  150. .check_atapi_dma = pdc_check_atapi_dma,
  151. .qc_prep = pdc_qc_prep,
  152. .qc_issue = pdc_qc_issue,
  153. .sff_irq_clear = pdc_irq_clear,
  154. .lost_interrupt = ATA_OP_NULL,
  155. .post_internal_cmd = pdc_post_internal_cmd,
  156. .error_handler = pdc_error_handler,
  157. };
  158. static struct ata_port_operations pdc_sata_ops = {
  159. .inherits = &pdc_common_ops,
  160. .cable_detect = ata_cable_sata,
  161. .freeze = pdc_sata_freeze,
  162. .thaw = pdc_sata_thaw,
  163. .scr_read = pdc_sata_scr_read,
  164. .scr_write = pdc_sata_scr_write,
  165. .port_start = pdc_sata_port_start,
  166. .hardreset = pdc_sata_hardreset,
  167. };
  168. /* First-generation chips need a more restrictive ->check_atapi_dma op,
  169. and ->freeze/thaw that ignore the hotplug controls. */
  170. static struct ata_port_operations pdc_old_sata_ops = {
  171. .inherits = &pdc_sata_ops,
  172. .freeze = pdc_freeze,
  173. .thaw = pdc_thaw,
  174. .check_atapi_dma = pdc_old_sata_check_atapi_dma,
  175. };
  176. static struct ata_port_operations pdc_pata_ops = {
  177. .inherits = &pdc_common_ops,
  178. .cable_detect = pdc_pata_cable_detect,
  179. .freeze = pdc_freeze,
  180. .thaw = pdc_thaw,
  181. .port_start = pdc_common_port_start,
  182. .softreset = pdc_pata_softreset,
  183. };
  184. static const struct ata_port_info pdc_port_info[] = {
  185. [board_2037x] =
  186. {
  187. .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
  188. PDC_FLAG_SATA_PATA,
  189. .pio_mask = ATA_PIO4,
  190. .mwdma_mask = ATA_MWDMA2,
  191. .udma_mask = ATA_UDMA6,
  192. .port_ops = &pdc_old_sata_ops,
  193. },
  194. [board_2037x_pata] =
  195. {
  196. .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS,
  197. .pio_mask = ATA_PIO4,
  198. .mwdma_mask = ATA_MWDMA2,
  199. .udma_mask = ATA_UDMA6,
  200. .port_ops = &pdc_pata_ops,
  201. },
  202. [board_20319] =
  203. {
  204. .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
  205. PDC_FLAG_4_PORTS,
  206. .pio_mask = ATA_PIO4,
  207. .mwdma_mask = ATA_MWDMA2,
  208. .udma_mask = ATA_UDMA6,
  209. .port_ops = &pdc_old_sata_ops,
  210. },
  211. [board_20619] =
  212. {
  213. .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS |
  214. PDC_FLAG_4_PORTS,
  215. .pio_mask = ATA_PIO4,
  216. .mwdma_mask = ATA_MWDMA2,
  217. .udma_mask = ATA_UDMA6,
  218. .port_ops = &pdc_pata_ops,
  219. },
  220. [board_2057x] =
  221. {
  222. .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
  223. PDC_FLAG_GEN_II | PDC_FLAG_SATA_PATA,
  224. .pio_mask = ATA_PIO4,
  225. .mwdma_mask = ATA_MWDMA2,
  226. .udma_mask = ATA_UDMA6,
  227. .port_ops = &pdc_sata_ops,
  228. },
  229. [board_2057x_pata] =
  230. {
  231. .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS |
  232. PDC_FLAG_GEN_II,
  233. .pio_mask = ATA_PIO4,
  234. .mwdma_mask = ATA_MWDMA2,
  235. .udma_mask = ATA_UDMA6,
  236. .port_ops = &pdc_pata_ops,
  237. },
  238. [board_40518] =
  239. {
  240. .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
  241. PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS,
  242. .pio_mask = ATA_PIO4,
  243. .mwdma_mask = ATA_MWDMA2,
  244. .udma_mask = ATA_UDMA6,
  245. .port_ops = &pdc_sata_ops,
  246. },
  247. };
  248. static const struct pci_device_id pdc_ata_pci_tbl[] = {
  249. { PCI_VDEVICE(PROMISE, 0x3371), board_2037x },
  250. { PCI_VDEVICE(PROMISE, 0x3373), board_2037x },
  251. { PCI_VDEVICE(PROMISE, 0x3375), board_2037x },
  252. { PCI_VDEVICE(PROMISE, 0x3376), board_2037x },
  253. { PCI_VDEVICE(PROMISE, 0x3570), board_2057x },
  254. { PCI_VDEVICE(PROMISE, 0x3571), board_2057x },
  255. { PCI_VDEVICE(PROMISE, 0x3574), board_2057x },
  256. { PCI_VDEVICE(PROMISE, 0x3577), board_2057x },
  257. { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x },
  258. { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x },
  259. { PCI_VDEVICE(PROMISE, 0x3318), board_20319 },
  260. { PCI_VDEVICE(PROMISE, 0x3319), board_20319 },
  261. { PCI_VDEVICE(PROMISE, 0x3515), board_40518 },
  262. { PCI_VDEVICE(PROMISE, 0x3519), board_40518 },
  263. { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 },
  264. { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 },
  265. { PCI_VDEVICE(PROMISE, 0x6629), board_20619 },
  266. { } /* terminate list */
  267. };
  268. static struct pci_driver pdc_ata_pci_driver = {
  269. .name = DRV_NAME,
  270. .id_table = pdc_ata_pci_tbl,
  271. .probe = pdc_ata_init_one,
  272. .remove = ata_pci_remove_one,
  273. };
  274. static int pdc_common_port_start(struct ata_port *ap)
  275. {
  276. struct device *dev = ap->host->dev;
  277. struct pdc_port_priv *pp;
  278. int rc;
  279. /* we use the same prd table as bmdma, allocate it */
  280. rc = ata_bmdma_port_start(ap);
  281. if (rc)
  282. return rc;
  283. pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
  284. if (!pp)
  285. return -ENOMEM;
  286. pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
  287. if (!pp->pkt)
  288. return -ENOMEM;
  289. ap->private_data = pp;
  290. return 0;
  291. }
  292. static int pdc_sata_port_start(struct ata_port *ap)
  293. {
  294. int rc;
  295. rc = pdc_common_port_start(ap);
  296. if (rc)
  297. return rc;
  298. /* fix up PHYMODE4 align timing */
  299. if (ap->flags & PDC_FLAG_GEN_II) {
  300. void __iomem *sata_mmio = ap->ioaddr.scr_addr;
  301. unsigned int tmp;
  302. tmp = readl(sata_mmio + PDC_PHYMODE4);
  303. tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */
  304. writel(tmp, sata_mmio + PDC_PHYMODE4);
  305. }
  306. return 0;
  307. }
  308. static void pdc_fpdma_clear_interrupt_flag(struct ata_port *ap)
  309. {
  310. void __iomem *sata_mmio = ap->ioaddr.scr_addr;
  311. u32 tmp;
  312. tmp = readl(sata_mmio + PDC_FPDMA_CTLSTAT);
  313. tmp |= PDC_FPDMA_CTLSTAT_DMASETUP_INT_FLAG;
  314. tmp |= PDC_FPDMA_CTLSTAT_SETDB_INT_FLAG;
  315. /* It's not allowed to write to the entire FPDMA_CTLSTAT register
  316. when NCQ is running. So do a byte-sized write to bits 10 and 11. */
  317. writeb(tmp >> 8, sata_mmio + PDC_FPDMA_CTLSTAT + 1);
  318. readb(sata_mmio + PDC_FPDMA_CTLSTAT + 1); /* flush */
  319. }
  320. static void pdc_fpdma_reset(struct ata_port *ap)
  321. {
  322. void __iomem *sata_mmio = ap->ioaddr.scr_addr;
  323. u8 tmp;
  324. tmp = (u8)readl(sata_mmio + PDC_FPDMA_CTLSTAT);
  325. tmp &= 0x7F;
  326. tmp |= PDC_FPDMA_CTLSTAT_RESET;
  327. writeb(tmp, sata_mmio + PDC_FPDMA_CTLSTAT);
  328. readl(sata_mmio + PDC_FPDMA_CTLSTAT); /* flush */
  329. udelay(100);
  330. tmp &= ~PDC_FPDMA_CTLSTAT_RESET;
  331. writeb(tmp, sata_mmio + PDC_FPDMA_CTLSTAT);
  332. readl(sata_mmio + PDC_FPDMA_CTLSTAT); /* flush */
  333. pdc_fpdma_clear_interrupt_flag(ap);
  334. }
  335. static void pdc_not_at_command_packet_phase(struct ata_port *ap)
  336. {
  337. void __iomem *sata_mmio = ap->ioaddr.scr_addr;
  338. unsigned int i;
  339. u32 tmp;
  340. /* check not at ASIC packet command phase */
  341. for (i = 0; i < 100; ++i) {
  342. writel(0, sata_mmio + PDC_INTERNAL_DEBUG_1);
  343. tmp = readl(sata_mmio + PDC_INTERNAL_DEBUG_2);
  344. if ((tmp & 0xF) != 1)
  345. break;
  346. udelay(100);
  347. }
  348. }
  349. static void pdc_clear_internal_debug_record_error_register(struct ata_port *ap)
  350. {
  351. void __iomem *sata_mmio = ap->ioaddr.scr_addr;
  352. writel(0xffffffff, sata_mmio + PDC_SATA_ERROR);
  353. writel(0xffff0000, sata_mmio + PDC_LINK_LAYER_ERRORS);
  354. }
  355. static void pdc_reset_port(struct ata_port *ap)
  356. {
  357. void __iomem *ata_ctlstat_mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT;
  358. unsigned int i;
  359. u32 tmp;
  360. if (ap->flags & PDC_FLAG_GEN_II)
  361. pdc_not_at_command_packet_phase(ap);
  362. tmp = readl(ata_ctlstat_mmio);
  363. tmp |= PDC_RESET;
  364. writel(tmp, ata_ctlstat_mmio);
  365. for (i = 11; i > 0; i--) {
  366. tmp = readl(ata_ctlstat_mmio);
  367. if (tmp & PDC_RESET)
  368. break;
  369. udelay(100);
  370. tmp |= PDC_RESET;
  371. writel(tmp, ata_ctlstat_mmio);
  372. }
  373. tmp &= ~PDC_RESET;
  374. writel(tmp, ata_ctlstat_mmio);
  375. readl(ata_ctlstat_mmio); /* flush */
  376. if (sata_scr_valid(&ap->link) && (ap->flags & PDC_FLAG_GEN_II)) {
  377. pdc_fpdma_reset(ap);
  378. pdc_clear_internal_debug_record_error_register(ap);
  379. }
  380. }
  381. static int pdc_pata_cable_detect(struct ata_port *ap)
  382. {
  383. u8 tmp;
  384. void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
  385. tmp = readb(ata_mmio + PDC_CTLSTAT + 3);
  386. if (tmp & 0x01)
  387. return ATA_CBL_PATA40;
  388. return ATA_CBL_PATA80;
  389. }
  390. static int pdc_sata_scr_read(struct ata_link *link,
  391. unsigned int sc_reg, u32 *val)
  392. {
  393. if (sc_reg > SCR_CONTROL)
  394. return -EINVAL;
  395. *val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 4));
  396. return 0;
  397. }
  398. static int pdc_sata_scr_write(struct ata_link *link,
  399. unsigned int sc_reg, u32 val)
  400. {
  401. if (sc_reg > SCR_CONTROL)
  402. return -EINVAL;
  403. writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4));
  404. return 0;
  405. }
  406. static void pdc_atapi_pkt(struct ata_queued_cmd *qc)
  407. {
  408. struct ata_port *ap = qc->ap;
  409. dma_addr_t sg_table = ap->bmdma_prd_dma;
  410. unsigned int cdb_len = qc->dev->cdb_len;
  411. u8 *cdb = qc->cdb;
  412. struct pdc_port_priv *pp = ap->private_data;
  413. u8 *buf = pp->pkt;
  414. __le32 *buf32 = (__le32 *) buf;
  415. unsigned int dev_sel, feature;
  416. /* set control bits (byte 0), zero delay seq id (byte 3),
  417. * and seq id (byte 2)
  418. */
  419. switch (qc->tf.protocol) {
  420. case ATAPI_PROT_DMA:
  421. if (!(qc->tf.flags & ATA_TFLAG_WRITE))
  422. buf32[0] = cpu_to_le32(PDC_PKT_READ);
  423. else
  424. buf32[0] = 0;
  425. break;
  426. case ATAPI_PROT_NODATA:
  427. buf32[0] = cpu_to_le32(PDC_PKT_NODATA);
  428. break;
  429. default:
  430. BUG();
  431. break;
  432. }
  433. buf32[1] = cpu_to_le32(sg_table); /* S/G table addr */
  434. buf32[2] = 0; /* no next-packet */
  435. /* select drive */
  436. if (sata_scr_valid(&ap->link))
  437. dev_sel = PDC_DEVICE_SATA;
  438. else
  439. dev_sel = qc->tf.device;
  440. buf[12] = (1 << 5) | ATA_REG_DEVICE;
  441. buf[13] = dev_sel;
  442. buf[14] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_CLEAR_BSY;
  443. buf[15] = dev_sel; /* once more, waiting for BSY to clear */
  444. buf[16] = (1 << 5) | ATA_REG_NSECT;
  445. buf[17] = qc->tf.nsect;
  446. buf[18] = (1 << 5) | ATA_REG_LBAL;
  447. buf[19] = qc->tf.lbal;
  448. /* set feature and byte counter registers */
  449. if (qc->tf.protocol != ATAPI_PROT_DMA)
  450. feature = PDC_FEATURE_ATAPI_PIO;
  451. else
  452. feature = PDC_FEATURE_ATAPI_DMA;
  453. buf[20] = (1 << 5) | ATA_REG_FEATURE;
  454. buf[21] = feature;
  455. buf[22] = (1 << 5) | ATA_REG_BYTEL;
  456. buf[23] = qc->tf.lbam;
  457. buf[24] = (1 << 5) | ATA_REG_BYTEH;
  458. buf[25] = qc->tf.lbah;
  459. /* send ATAPI packet command 0xA0 */
  460. buf[26] = (1 << 5) | ATA_REG_CMD;
  461. buf[27] = qc->tf.command;
  462. /* select drive and check DRQ */
  463. buf[28] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_WAIT_DRDY;
  464. buf[29] = dev_sel;
  465. /* we can represent cdb lengths 2/4/6/8/10/12/14/16 */
  466. BUG_ON(cdb_len & ~0x1E);
  467. /* append the CDB as the final part */
  468. buf[30] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG;
  469. memcpy(buf+31, cdb, cdb_len);
  470. }
  471. /**
  472. * pdc_fill_sg - Fill PCI IDE PRD table
  473. * @qc: Metadata associated with taskfile to be transferred
  474. *
  475. * Fill PCI IDE PRD (scatter-gather) table with segments
  476. * associated with the current disk command.
  477. * Make sure hardware does not choke on it.
  478. *
  479. * LOCKING:
  480. * spin_lock_irqsave(host lock)
  481. *
  482. */
  483. static void pdc_fill_sg(struct ata_queued_cmd *qc)
  484. {
  485. struct ata_port *ap = qc->ap;
  486. struct ata_bmdma_prd *prd = ap->bmdma_prd;
  487. struct scatterlist *sg;
  488. const u32 SG_COUNT_ASIC_BUG = 41*4;
  489. unsigned int si, idx;
  490. u32 len;
  491. if (!(qc->flags & ATA_QCFLAG_DMAMAP))
  492. return;
  493. idx = 0;
  494. for_each_sg(qc->sg, sg, qc->n_elem, si) {
  495. u32 addr, offset;
  496. u32 sg_len;
  497. /* determine if physical DMA addr spans 64K boundary.
  498. * Note h/w doesn't support 64-bit, so we unconditionally
  499. * truncate dma_addr_t to u32.
  500. */
  501. addr = (u32) sg_dma_address(sg);
  502. sg_len = sg_dma_len(sg);
  503. while (sg_len) {
  504. offset = addr & 0xffff;
  505. len = sg_len;
  506. if ((offset + sg_len) > 0x10000)
  507. len = 0x10000 - offset;
  508. prd[idx].addr = cpu_to_le32(addr);
  509. prd[idx].flags_len = cpu_to_le32(len & 0xffff);
  510. VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
  511. idx++;
  512. sg_len -= len;
  513. addr += len;
  514. }
  515. }
  516. len = le32_to_cpu(prd[idx - 1].flags_len);
  517. if (len > SG_COUNT_ASIC_BUG) {
  518. u32 addr;
  519. VPRINTK("Splitting last PRD.\n");
  520. addr = le32_to_cpu(prd[idx - 1].addr);
  521. prd[idx - 1].flags_len = cpu_to_le32(len - SG_COUNT_ASIC_BUG);
  522. VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx - 1, addr, SG_COUNT_ASIC_BUG);
  523. addr = addr + len - SG_COUNT_ASIC_BUG;
  524. len = SG_COUNT_ASIC_BUG;
  525. prd[idx].addr = cpu_to_le32(addr);
  526. prd[idx].flags_len = cpu_to_le32(len);
  527. VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
  528. idx++;
  529. }
  530. prd[idx - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
  531. }
  532. static enum ata_completion_errors pdc_qc_prep(struct ata_queued_cmd *qc)
  533. {
  534. struct pdc_port_priv *pp = qc->ap->private_data;
  535. unsigned int i;
  536. VPRINTK("ENTER\n");
  537. switch (qc->tf.protocol) {
  538. case ATA_PROT_DMA:
  539. pdc_fill_sg(qc);
  540. fallthrough;
  541. case ATA_PROT_NODATA:
  542. i = pdc_pkt_header(&qc->tf, qc->ap->bmdma_prd_dma,
  543. qc->dev->devno, pp->pkt);
  544. if (qc->tf.flags & ATA_TFLAG_LBA48)
  545. i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
  546. else
  547. i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
  548. pdc_pkt_footer(&qc->tf, pp->pkt, i);
  549. break;
  550. case ATAPI_PROT_PIO:
  551. pdc_fill_sg(qc);
  552. break;
  553. case ATAPI_PROT_DMA:
  554. pdc_fill_sg(qc);
  555. fallthrough;
  556. case ATAPI_PROT_NODATA:
  557. pdc_atapi_pkt(qc);
  558. break;
  559. default:
  560. break;
  561. }
  562. return AC_ERR_OK;
  563. }
  564. static int pdc_is_sataii_tx4(unsigned long flags)
  565. {
  566. const unsigned long mask = PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS;
  567. return (flags & mask) == mask;
  568. }
  569. static unsigned int pdc_port_no_to_ata_no(unsigned int port_no,
  570. int is_sataii_tx4)
  571. {
  572. static const unsigned char sataii_tx4_port_remap[4] = { 3, 1, 0, 2};
  573. return is_sataii_tx4 ? sataii_tx4_port_remap[port_no] : port_no;
  574. }
  575. static unsigned int pdc_sata_nr_ports(const struct ata_port *ap)
  576. {
  577. return (ap->flags & PDC_FLAG_4_PORTS) ? 4 : 2;
  578. }
  579. static unsigned int pdc_sata_ata_port_to_ata_no(const struct ata_port *ap)
  580. {
  581. const struct ata_host *host = ap->host;
  582. unsigned int nr_ports = pdc_sata_nr_ports(ap);
  583. unsigned int i;
  584. for (i = 0; i < nr_ports && host->ports[i] != ap; ++i)
  585. ;
  586. BUG_ON(i >= nr_ports);
  587. return pdc_port_no_to_ata_no(i, pdc_is_sataii_tx4(ap->flags));
  588. }
  589. static void pdc_freeze(struct ata_port *ap)
  590. {
  591. void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
  592. u32 tmp;
  593. tmp = readl(ata_mmio + PDC_CTLSTAT);
  594. tmp |= PDC_IRQ_DISABLE;
  595. tmp &= ~PDC_DMA_ENABLE;
  596. writel(tmp, ata_mmio + PDC_CTLSTAT);
  597. readl(ata_mmio + PDC_CTLSTAT); /* flush */
  598. }
  599. static void pdc_sata_freeze(struct ata_port *ap)
  600. {
  601. struct ata_host *host = ap->host;
  602. void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR];
  603. unsigned int hotplug_offset = PDC2_SATA_PLUG_CSR;
  604. unsigned int ata_no = pdc_sata_ata_port_to_ata_no(ap);
  605. u32 hotplug_status;
  606. /* Disable hotplug events on this port.
  607. *
  608. * Locking:
  609. * 1) hotplug register accesses must be serialised via host->lock
  610. * 2) ap->lock == &ap->host->lock
  611. * 3) ->freeze() and ->thaw() are called with ap->lock held
  612. */
  613. hotplug_status = readl(host_mmio + hotplug_offset);
  614. hotplug_status |= 0x11 << (ata_no + 16);
  615. writel(hotplug_status, host_mmio + hotplug_offset);
  616. readl(host_mmio + hotplug_offset); /* flush */
  617. pdc_freeze(ap);
  618. }
  619. static void pdc_thaw(struct ata_port *ap)
  620. {
  621. void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
  622. u32 tmp;
  623. /* clear IRQ */
  624. readl(ata_mmio + PDC_COMMAND);
  625. /* turn IRQ back on */
  626. tmp = readl(ata_mmio + PDC_CTLSTAT);
  627. tmp &= ~PDC_IRQ_DISABLE;
  628. writel(tmp, ata_mmio + PDC_CTLSTAT);
  629. readl(ata_mmio + PDC_CTLSTAT); /* flush */
  630. }
  631. static void pdc_sata_thaw(struct ata_port *ap)
  632. {
  633. struct ata_host *host = ap->host;
  634. void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR];
  635. unsigned int hotplug_offset = PDC2_SATA_PLUG_CSR;
  636. unsigned int ata_no = pdc_sata_ata_port_to_ata_no(ap);
  637. u32 hotplug_status;
  638. pdc_thaw(ap);
  639. /* Enable hotplug events on this port.
  640. * Locking: see pdc_sata_freeze().
  641. */
  642. hotplug_status = readl(host_mmio + hotplug_offset);
  643. hotplug_status |= 0x11 << ata_no;
  644. hotplug_status &= ~(0x11 << (ata_no + 16));
  645. writel(hotplug_status, host_mmio + hotplug_offset);
  646. readl(host_mmio + hotplug_offset); /* flush */
  647. }
  648. static int pdc_pata_softreset(struct ata_link *link, unsigned int *class,
  649. unsigned long deadline)
  650. {
  651. pdc_reset_port(link->ap);
  652. return ata_sff_softreset(link, class, deadline);
  653. }
  654. static unsigned int pdc_ata_port_to_ata_no(const struct ata_port *ap)
  655. {
  656. void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
  657. void __iomem *host_mmio = ap->host->iomap[PDC_MMIO_BAR];
  658. /* ata_mmio == host_mmio + 0x200 + ata_no * 0x80 */
  659. return (ata_mmio - host_mmio - 0x200) / 0x80;
  660. }
  661. static void pdc_hard_reset_port(struct ata_port *ap)
  662. {
  663. void __iomem *host_mmio = ap->host->iomap[PDC_MMIO_BAR];
  664. void __iomem *pcictl_b1_mmio = host_mmio + PDC_PCI_CTL + 1;
  665. unsigned int ata_no = pdc_ata_port_to_ata_no(ap);
  666. struct pdc_host_priv *hpriv = ap->host->private_data;
  667. u8 tmp;
  668. spin_lock(&hpriv->hard_reset_lock);
  669. tmp = readb(pcictl_b1_mmio);
  670. tmp &= ~(0x10 << ata_no);
  671. writeb(tmp, pcictl_b1_mmio);
  672. readb(pcictl_b1_mmio); /* flush */
  673. udelay(100);
  674. tmp |= (0x10 << ata_no);
  675. writeb(tmp, pcictl_b1_mmio);
  676. readb(pcictl_b1_mmio); /* flush */
  677. spin_unlock(&hpriv->hard_reset_lock);
  678. }
  679. static int pdc_sata_hardreset(struct ata_link *link, unsigned int *class,
  680. unsigned long deadline)
  681. {
  682. if (link->ap->flags & PDC_FLAG_GEN_II)
  683. pdc_not_at_command_packet_phase(link->ap);
  684. /* hotplug IRQs should have been masked by pdc_sata_freeze() */
  685. pdc_hard_reset_port(link->ap);
  686. pdc_reset_port(link->ap);
  687. /* sata_promise can't reliably acquire the first D2H Reg FIS
  688. * after hardreset. Do non-waiting hardreset and request
  689. * follow-up SRST.
  690. */
  691. return sata_std_hardreset(link, class, deadline);
  692. }
  693. static void pdc_error_handler(struct ata_port *ap)
  694. {
  695. if (!(ap->pflags & ATA_PFLAG_FROZEN))
  696. pdc_reset_port(ap);
  697. ata_sff_error_handler(ap);
  698. }
  699. static void pdc_post_internal_cmd(struct ata_queued_cmd *qc)
  700. {
  701. struct ata_port *ap = qc->ap;
  702. /* make DMA engine forget about the failed command */
  703. if (qc->flags & ATA_QCFLAG_FAILED)
  704. pdc_reset_port(ap);
  705. }
  706. static void pdc_error_intr(struct ata_port *ap, struct ata_queued_cmd *qc,
  707. u32 port_status, u32 err_mask)
  708. {
  709. struct ata_eh_info *ehi = &ap->link.eh_info;
  710. unsigned int ac_err_mask = 0;
  711. ata_ehi_clear_desc(ehi);
  712. ata_ehi_push_desc(ehi, "port_status 0x%08x", port_status);
  713. port_status &= err_mask;
  714. if (port_status & PDC_DRIVE_ERR)
  715. ac_err_mask |= AC_ERR_DEV;
  716. if (port_status & (PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR))
  717. ac_err_mask |= AC_ERR_OTHER;
  718. if (port_status & (PDC2_ATA_HBA_ERR | PDC2_ATA_DMA_CNT_ERR))
  719. ac_err_mask |= AC_ERR_ATA_BUS;
  720. if (port_status & (PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | PDC2_HTO_ERR
  721. | PDC_PCI_SYS_ERR | PDC1_PCI_PARITY_ERR))
  722. ac_err_mask |= AC_ERR_HOST_BUS;
  723. if (sata_scr_valid(&ap->link)) {
  724. u32 serror;
  725. pdc_sata_scr_read(&ap->link, SCR_ERROR, &serror);
  726. ehi->serror |= serror;
  727. }
  728. qc->err_mask |= ac_err_mask;
  729. pdc_reset_port(ap);
  730. ata_port_abort(ap);
  731. }
  732. static unsigned int pdc_host_intr(struct ata_port *ap,
  733. struct ata_queued_cmd *qc)
  734. {
  735. unsigned int handled = 0;
  736. void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
  737. u32 port_status, err_mask;
  738. err_mask = PDC_ERR_MASK;
  739. if (ap->flags & PDC_FLAG_GEN_II)
  740. err_mask &= ~PDC1_ERR_MASK;
  741. else
  742. err_mask &= ~PDC2_ERR_MASK;
  743. port_status = readl(ata_mmio + PDC_GLOBAL_CTL);
  744. if (unlikely(port_status & err_mask)) {
  745. pdc_error_intr(ap, qc, port_status, err_mask);
  746. return 1;
  747. }
  748. switch (qc->tf.protocol) {
  749. case ATA_PROT_DMA:
  750. case ATA_PROT_NODATA:
  751. case ATAPI_PROT_DMA:
  752. case ATAPI_PROT_NODATA:
  753. qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
  754. ata_qc_complete(qc);
  755. handled = 1;
  756. break;
  757. default:
  758. ap->stats.idle_irq++;
  759. break;
  760. }
  761. return handled;
  762. }
  763. static void pdc_irq_clear(struct ata_port *ap)
  764. {
  765. void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
  766. readl(ata_mmio + PDC_COMMAND);
  767. }
  768. static irqreturn_t pdc_interrupt(int irq, void *dev_instance)
  769. {
  770. struct ata_host *host = dev_instance;
  771. struct ata_port *ap;
  772. u32 mask = 0;
  773. unsigned int i, tmp;
  774. unsigned int handled = 0;
  775. void __iomem *host_mmio;
  776. unsigned int hotplug_offset, ata_no;
  777. u32 hotplug_status;
  778. int is_sataii_tx4;
  779. VPRINTK("ENTER\n");
  780. if (!host || !host->iomap[PDC_MMIO_BAR]) {
  781. VPRINTK("QUICK EXIT\n");
  782. return IRQ_NONE;
  783. }
  784. host_mmio = host->iomap[PDC_MMIO_BAR];
  785. spin_lock(&host->lock);
  786. /* read and clear hotplug flags for all ports */
  787. if (host->ports[0]->flags & PDC_FLAG_GEN_II) {
  788. hotplug_offset = PDC2_SATA_PLUG_CSR;
  789. hotplug_status = readl(host_mmio + hotplug_offset);
  790. if (hotplug_status & 0xff)
  791. writel(hotplug_status | 0xff, host_mmio + hotplug_offset);
  792. hotplug_status &= 0xff; /* clear uninteresting bits */
  793. } else
  794. hotplug_status = 0;
  795. /* reading should also clear interrupts */
  796. mask = readl(host_mmio + PDC_INT_SEQMASK);
  797. if (mask == 0xffffffff && hotplug_status == 0) {
  798. VPRINTK("QUICK EXIT 2\n");
  799. goto done_irq;
  800. }
  801. mask &= 0xffff; /* only 16 SEQIDs possible */
  802. if (mask == 0 && hotplug_status == 0) {
  803. VPRINTK("QUICK EXIT 3\n");
  804. goto done_irq;
  805. }
  806. writel(mask, host_mmio + PDC_INT_SEQMASK);
  807. is_sataii_tx4 = pdc_is_sataii_tx4(host->ports[0]->flags);
  808. for (i = 0; i < host->n_ports; i++) {
  809. VPRINTK("port %u\n", i);
  810. ap = host->ports[i];
  811. /* check for a plug or unplug event */
  812. ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4);
  813. tmp = hotplug_status & (0x11 << ata_no);
  814. if (tmp) {
  815. struct ata_eh_info *ehi = &ap->link.eh_info;
  816. ata_ehi_clear_desc(ehi);
  817. ata_ehi_hotplugged(ehi);
  818. ata_ehi_push_desc(ehi, "hotplug_status %#x", tmp);
  819. ata_port_freeze(ap);
  820. ++handled;
  821. continue;
  822. }
  823. /* check for a packet interrupt */
  824. tmp = mask & (1 << (i + 1));
  825. if (tmp) {
  826. struct ata_queued_cmd *qc;
  827. qc = ata_qc_from_tag(ap, ap->link.active_tag);
  828. if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
  829. handled += pdc_host_intr(ap, qc);
  830. }
  831. }
  832. VPRINTK("EXIT\n");
  833. done_irq:
  834. spin_unlock(&host->lock);
  835. return IRQ_RETVAL(handled);
  836. }
  837. static void pdc_packet_start(struct ata_queued_cmd *qc)
  838. {
  839. struct ata_port *ap = qc->ap;
  840. struct pdc_port_priv *pp = ap->private_data;
  841. void __iomem *host_mmio = ap->host->iomap[PDC_MMIO_BAR];
  842. void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
  843. unsigned int port_no = ap->port_no;
  844. u8 seq = (u8) (port_no + 1);
  845. VPRINTK("ENTER, ap %p\n", ap);
  846. writel(0x00000001, host_mmio + (seq * 4));
  847. readl(host_mmio + (seq * 4)); /* flush */
  848. pp->pkt[2] = seq;
  849. wmb(); /* flush PRD, pkt writes */
  850. writel(pp->pkt_dma, ata_mmio + PDC_PKT_SUBMIT);
  851. readl(ata_mmio + PDC_PKT_SUBMIT); /* flush */
  852. }
  853. static unsigned int pdc_qc_issue(struct ata_queued_cmd *qc)
  854. {
  855. switch (qc->tf.protocol) {
  856. case ATAPI_PROT_NODATA:
  857. if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
  858. break;
  859. fallthrough;
  860. case ATA_PROT_NODATA:
  861. if (qc->tf.flags & ATA_TFLAG_POLLING)
  862. break;
  863. fallthrough;
  864. case ATAPI_PROT_DMA:
  865. case ATA_PROT_DMA:
  866. pdc_packet_start(qc);
  867. return 0;
  868. default:
  869. break;
  870. }
  871. return ata_sff_qc_issue(qc);
  872. }
  873. static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
  874. {
  875. WARN_ON(tf->protocol == ATA_PROT_DMA || tf->protocol == ATAPI_PROT_DMA);
  876. ata_sff_tf_load(ap, tf);
  877. }
  878. static void pdc_exec_command_mmio(struct ata_port *ap,
  879. const struct ata_taskfile *tf)
  880. {
  881. WARN_ON(tf->protocol == ATA_PROT_DMA || tf->protocol == ATAPI_PROT_DMA);
  882. ata_sff_exec_command(ap, tf);
  883. }
  884. static int pdc_check_atapi_dma(struct ata_queued_cmd *qc)
  885. {
  886. u8 *scsicmd = qc->scsicmd->cmnd;
  887. int pio = 1; /* atapi dma off by default */
  888. /* Whitelist commands that may use DMA. */
  889. switch (scsicmd[0]) {
  890. case WRITE_12:
  891. case WRITE_10:
  892. case WRITE_6:
  893. case READ_12:
  894. case READ_10:
  895. case READ_6:
  896. case 0xad: /* READ_DVD_STRUCTURE */
  897. case 0xbe: /* READ_CD */
  898. pio = 0;
  899. }
  900. /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */
  901. if (scsicmd[0] == WRITE_10) {
  902. unsigned int lba =
  903. (scsicmd[2] << 24) |
  904. (scsicmd[3] << 16) |
  905. (scsicmd[4] << 8) |
  906. scsicmd[5];
  907. if (lba >= 0xFFFF4FA2)
  908. pio = 1;
  909. }
  910. return pio;
  911. }
  912. static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc)
  913. {
  914. /* First generation chips cannot use ATAPI DMA on SATA ports */
  915. return 1;
  916. }
  917. static void pdc_ata_setup_port(struct ata_port *ap,
  918. void __iomem *base, void __iomem *scr_addr)
  919. {
  920. ap->ioaddr.cmd_addr = base;
  921. ap->ioaddr.data_addr = base;
  922. ap->ioaddr.feature_addr =
  923. ap->ioaddr.error_addr = base + 0x4;
  924. ap->ioaddr.nsect_addr = base + 0x8;
  925. ap->ioaddr.lbal_addr = base + 0xc;
  926. ap->ioaddr.lbam_addr = base + 0x10;
  927. ap->ioaddr.lbah_addr = base + 0x14;
  928. ap->ioaddr.device_addr = base + 0x18;
  929. ap->ioaddr.command_addr =
  930. ap->ioaddr.status_addr = base + 0x1c;
  931. ap->ioaddr.altstatus_addr =
  932. ap->ioaddr.ctl_addr = base + 0x38;
  933. ap->ioaddr.scr_addr = scr_addr;
  934. }
  935. static void pdc_host_init(struct ata_host *host)
  936. {
  937. void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR];
  938. int is_gen2 = host->ports[0]->flags & PDC_FLAG_GEN_II;
  939. int hotplug_offset;
  940. u32 tmp;
  941. if (is_gen2)
  942. hotplug_offset = PDC2_SATA_PLUG_CSR;
  943. else
  944. hotplug_offset = PDC_SATA_PLUG_CSR;
  945. /*
  946. * Except for the hotplug stuff, this is voodoo from the
  947. * Promise driver. Label this entire section
  948. * "TODO: figure out why we do this"
  949. */
  950. /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */
  951. tmp = readl(host_mmio + PDC_FLASH_CTL);
  952. tmp |= 0x02000; /* bit 13 (enable bmr burst) */
  953. if (!is_gen2)
  954. tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */
  955. writel(tmp, host_mmio + PDC_FLASH_CTL);
  956. /* clear plug/unplug flags for all ports */
  957. tmp = readl(host_mmio + hotplug_offset);
  958. writel(tmp | 0xff, host_mmio + hotplug_offset);
  959. tmp = readl(host_mmio + hotplug_offset);
  960. if (is_gen2) /* unmask plug/unplug ints */
  961. writel(tmp & ~0xff0000, host_mmio + hotplug_offset);
  962. else /* mask plug/unplug ints */
  963. writel(tmp | 0xff0000, host_mmio + hotplug_offset);
  964. /* don't initialise TBG or SLEW on 2nd generation chips */
  965. if (is_gen2)
  966. return;
  967. /* reduce TBG clock to 133 Mhz. */
  968. tmp = readl(host_mmio + PDC_TBG_MODE);
  969. tmp &= ~0x30000; /* clear bit 17, 16*/
  970. tmp |= 0x10000; /* set bit 17:16 = 0:1 */
  971. writel(tmp, host_mmio + PDC_TBG_MODE);
  972. readl(host_mmio + PDC_TBG_MODE); /* flush */
  973. msleep(10);
  974. /* adjust slew rate control register. */
  975. tmp = readl(host_mmio + PDC_SLEW_CTL);
  976. tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
  977. tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
  978. writel(tmp, host_mmio + PDC_SLEW_CTL);
  979. }
  980. static int pdc_ata_init_one(struct pci_dev *pdev,
  981. const struct pci_device_id *ent)
  982. {
  983. const struct ata_port_info *pi = &pdc_port_info[ent->driver_data];
  984. const struct ata_port_info *ppi[PDC_MAX_PORTS];
  985. struct ata_host *host;
  986. struct pdc_host_priv *hpriv;
  987. void __iomem *host_mmio;
  988. int n_ports, i, rc;
  989. int is_sataii_tx4;
  990. ata_print_version_once(&pdev->dev, DRV_VERSION);
  991. /* enable and acquire resources */
  992. rc = pcim_enable_device(pdev);
  993. if (rc)
  994. return rc;
  995. rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME);
  996. if (rc == -EBUSY)
  997. pcim_pin_device(pdev);
  998. if (rc)
  999. return rc;
  1000. host_mmio = pcim_iomap_table(pdev)[PDC_MMIO_BAR];
  1001. /* determine port configuration and setup host */
  1002. n_ports = 2;
  1003. if (pi->flags & PDC_FLAG_4_PORTS)
  1004. n_ports = 4;
  1005. for (i = 0; i < n_ports; i++)
  1006. ppi[i] = pi;
  1007. if (pi->flags & PDC_FLAG_SATA_PATA) {
  1008. u8 tmp = readb(host_mmio + PDC_FLASH_CTL + 1);
  1009. if (!(tmp & 0x80))
  1010. ppi[n_ports++] = pi + 1;
  1011. }
  1012. host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
  1013. if (!host) {
  1014. dev_err(&pdev->dev, "failed to allocate host\n");
  1015. return -ENOMEM;
  1016. }
  1017. hpriv = devm_kzalloc(&pdev->dev, sizeof *hpriv, GFP_KERNEL);
  1018. if (!hpriv)
  1019. return -ENOMEM;
  1020. spin_lock_init(&hpriv->hard_reset_lock);
  1021. host->private_data = hpriv;
  1022. host->iomap = pcim_iomap_table(pdev);
  1023. is_sataii_tx4 = pdc_is_sataii_tx4(pi->flags);
  1024. for (i = 0; i < host->n_ports; i++) {
  1025. struct ata_port *ap = host->ports[i];
  1026. unsigned int ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4);
  1027. unsigned int ata_offset = 0x200 + ata_no * 0x80;
  1028. unsigned int scr_offset = 0x400 + ata_no * 0x100;
  1029. pdc_ata_setup_port(ap, host_mmio + ata_offset, host_mmio + scr_offset);
  1030. ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio");
  1031. ata_port_pbar_desc(ap, PDC_MMIO_BAR, ata_offset, "ata");
  1032. }
  1033. /* initialize adapter */
  1034. pdc_host_init(host);
  1035. rc = dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK);
  1036. if (rc)
  1037. return rc;
  1038. /* start host, request IRQ and attach */
  1039. pci_set_master(pdev);
  1040. return ata_host_activate(host, pdev->irq, pdc_interrupt, IRQF_SHARED,
  1041. &pdc_ata_sht);
  1042. }
  1043. module_pci_driver(pdc_ata_pci_driver);
  1044. MODULE_AUTHOR("Jeff Garzik");
  1045. MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
  1046. MODULE_LICENSE("GPL");
  1047. MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
  1048. MODULE_VERSION(DRV_VERSION);