sata_mv.c 122 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * sata_mv.c - Marvell SATA support
  4. *
  5. * Copyright 2008-2009: Marvell Corporation, all rights reserved.
  6. * Copyright 2005: EMC Corporation, all rights reserved.
  7. * Copyright 2005 Red Hat, Inc. All rights reserved.
  8. *
  9. * Originally written by Brett Russ.
  10. * Extensive overhaul and enhancement by Mark Lord <mlord@pobox.com>.
  11. *
  12. * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
  13. */
  14. /*
  15. * sata_mv TODO list:
  16. *
  17. * --> Develop a low-power-consumption strategy, and implement it.
  18. *
  19. * --> Add sysfs attributes for per-chip / per-HC IRQ coalescing thresholds.
  20. *
  21. * --> [Experiment, Marvell value added] Is it possible to use target
  22. * mode to cross-connect two Linux boxes with Marvell cards? If so,
  23. * creating LibATA target mode support would be very interesting.
  24. *
  25. * Target mode, for those without docs, is the ability to directly
  26. * connect two SATA ports.
  27. */
  28. /*
  29. * 80x1-B2 errata PCI#11:
  30. *
  31. * Users of the 6041/6081 Rev.B2 chips (current is C0)
  32. * should be careful to insert those cards only onto PCI-X bus #0,
  33. * and only in device slots 0..7, not higher. The chips may not
  34. * work correctly otherwise (note: this is a pretty rare condition).
  35. */
  36. #include <linux/kernel.h>
  37. #include <linux/module.h>
  38. #include <linux/pci.h>
  39. #include <linux/init.h>
  40. #include <linux/blkdev.h>
  41. #include <linux/delay.h>
  42. #include <linux/interrupt.h>
  43. #include <linux/dmapool.h>
  44. #include <linux/dma-mapping.h>
  45. #include <linux/device.h>
  46. #include <linux/clk.h>
  47. #include <linux/phy/phy.h>
  48. #include <linux/platform_device.h>
  49. #include <linux/ata_platform.h>
  50. #include <linux/mbus.h>
  51. #include <linux/bitops.h>
  52. #include <linux/gfp.h>
  53. #include <linux/of.h>
  54. #include <linux/of_irq.h>
  55. #include <scsi/scsi_host.h>
  56. #include <scsi/scsi_cmnd.h>
  57. #include <scsi/scsi_device.h>
  58. #include <linux/libata.h>
  59. #define DRV_NAME "sata_mv"
  60. #define DRV_VERSION "1.28"
  61. /*
  62. * module options
  63. */
  64. #ifdef CONFIG_PCI
  65. static int msi;
  66. module_param(msi, int, S_IRUGO);
  67. MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
  68. #endif
  69. static int irq_coalescing_io_count;
  70. module_param(irq_coalescing_io_count, int, S_IRUGO);
  71. MODULE_PARM_DESC(irq_coalescing_io_count,
  72. "IRQ coalescing I/O count threshold (0..255)");
  73. static int irq_coalescing_usecs;
  74. module_param(irq_coalescing_usecs, int, S_IRUGO);
  75. MODULE_PARM_DESC(irq_coalescing_usecs,
  76. "IRQ coalescing time threshold in usecs");
  77. enum {
  78. /* BAR's are enumerated in terms of pci_resource_start() terms */
  79. MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
  80. MV_IO_BAR = 2, /* offset 0x18: IO space */
  81. MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
  82. MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
  83. MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
  84. /* For use with both IRQ coalescing methods ("all ports" or "per-HC" */
  85. COAL_CLOCKS_PER_USEC = 150, /* for calculating COAL_TIMEs */
  86. MAX_COAL_TIME_THRESHOLD = ((1 << 24) - 1), /* internal clocks count */
  87. MAX_COAL_IO_COUNT = 255, /* completed I/O count */
  88. MV_PCI_REG_BASE = 0,
  89. /*
  90. * Per-chip ("all ports") interrupt coalescing feature.
  91. * This is only for GEN_II / GEN_IIE hardware.
  92. *
  93. * Coalescing defers the interrupt until either the IO_THRESHOLD
  94. * (count of completed I/Os) is met, or the TIME_THRESHOLD is met.
  95. */
  96. COAL_REG_BASE = 0x18000,
  97. IRQ_COAL_CAUSE = (COAL_REG_BASE + 0x08),
  98. ALL_PORTS_COAL_IRQ = (1 << 4), /* all ports irq event */
  99. IRQ_COAL_IO_THRESHOLD = (COAL_REG_BASE + 0xcc),
  100. IRQ_COAL_TIME_THRESHOLD = (COAL_REG_BASE + 0xd0),
  101. /*
  102. * Registers for the (unused here) transaction coalescing feature:
  103. */
  104. TRAN_COAL_CAUSE_LO = (COAL_REG_BASE + 0x88),
  105. TRAN_COAL_CAUSE_HI = (COAL_REG_BASE + 0x8c),
  106. SATAHC0_REG_BASE = 0x20000,
  107. FLASH_CTL = 0x1046c,
  108. GPIO_PORT_CTL = 0x104f0,
  109. RESET_CFG = 0x180d8,
  110. MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
  111. MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
  112. MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
  113. MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
  114. MV_MAX_Q_DEPTH = 32,
  115. MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
  116. /* CRQB needs alignment on a 1KB boundary. Size == 1KB
  117. * CRPB needs alignment on a 256B boundary. Size == 256B
  118. * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
  119. */
  120. MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
  121. MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
  122. MV_MAX_SG_CT = 256,
  123. MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
  124. /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
  125. MV_PORT_HC_SHIFT = 2,
  126. MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */
  127. /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
  128. MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */
  129. /* Host Flags */
  130. MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
  131. MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_PIO_POLLING,
  132. MV_GEN_I_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NO_ATAPI,
  133. MV_GEN_II_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NCQ |
  134. ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA,
  135. MV_GEN_IIE_FLAGS = MV_GEN_II_FLAGS | ATA_FLAG_AN,
  136. CRQB_FLAG_READ = (1 << 0),
  137. CRQB_TAG_SHIFT = 1,
  138. CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
  139. CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */
  140. CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
  141. CRQB_CMD_ADDR_SHIFT = 8,
  142. CRQB_CMD_CS = (0x2 << 11),
  143. CRQB_CMD_LAST = (1 << 15),
  144. CRPB_FLAG_STATUS_SHIFT = 8,
  145. CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */
  146. CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */
  147. EPRD_FLAG_END_OF_TBL = (1 << 31),
  148. /* PCI interface registers */
  149. MV_PCI_COMMAND = 0xc00,
  150. MV_PCI_COMMAND_MWRCOM = (1 << 4), /* PCI Master Write Combining */
  151. MV_PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */
  152. PCI_MAIN_CMD_STS = 0xd30,
  153. STOP_PCI_MASTER = (1 << 2),
  154. PCI_MASTER_EMPTY = (1 << 3),
  155. GLOB_SFT_RST = (1 << 4),
  156. MV_PCI_MODE = 0xd00,
  157. MV_PCI_MODE_MASK = 0x30,
  158. MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
  159. MV_PCI_DISC_TIMER = 0xd04,
  160. MV_PCI_MSI_TRIGGER = 0xc38,
  161. MV_PCI_SERR_MASK = 0xc28,
  162. MV_PCI_XBAR_TMOUT = 0x1d04,
  163. MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
  164. MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
  165. MV_PCI_ERR_ATTRIBUTE = 0x1d48,
  166. MV_PCI_ERR_COMMAND = 0x1d50,
  167. PCI_IRQ_CAUSE = 0x1d58,
  168. PCI_IRQ_MASK = 0x1d5c,
  169. PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
  170. PCIE_IRQ_CAUSE = 0x1900,
  171. PCIE_IRQ_MASK = 0x1910,
  172. PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */
  173. /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
  174. PCI_HC_MAIN_IRQ_CAUSE = 0x1d60,
  175. PCI_HC_MAIN_IRQ_MASK = 0x1d64,
  176. SOC_HC_MAIN_IRQ_CAUSE = 0x20020,
  177. SOC_HC_MAIN_IRQ_MASK = 0x20024,
  178. ERR_IRQ = (1 << 0), /* shift by (2 * port #) */
  179. DONE_IRQ = (1 << 1), /* shift by (2 * port #) */
  180. HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
  181. HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
  182. DONE_IRQ_0_3 = 0x000000aa, /* DONE_IRQ ports 0,1,2,3 */
  183. DONE_IRQ_4_7 = (DONE_IRQ_0_3 << HC_SHIFT), /* 4,5,6,7 */
  184. PCI_ERR = (1 << 18),
  185. TRAN_COAL_LO_DONE = (1 << 19), /* transaction coalescing */
  186. TRAN_COAL_HI_DONE = (1 << 20), /* transaction coalescing */
  187. PORTS_0_3_COAL_DONE = (1 << 8), /* HC0 IRQ coalescing */
  188. PORTS_4_7_COAL_DONE = (1 << 17), /* HC1 IRQ coalescing */
  189. ALL_PORTS_COAL_DONE = (1 << 21), /* GEN_II(E) IRQ coalescing */
  190. GPIO_INT = (1 << 22),
  191. SELF_INT = (1 << 23),
  192. TWSI_INT = (1 << 24),
  193. HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
  194. HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
  195. HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
  196. /* SATAHC registers */
  197. HC_CFG = 0x00,
  198. HC_IRQ_CAUSE = 0x14,
  199. DMA_IRQ = (1 << 0), /* shift by port # */
  200. HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */
  201. DEV_IRQ = (1 << 8), /* shift by port # */
  202. /*
  203. * Per-HC (Host-Controller) interrupt coalescing feature.
  204. * This is present on all chip generations.
  205. *
  206. * Coalescing defers the interrupt until either the IO_THRESHOLD
  207. * (count of completed I/Os) is met, or the TIME_THRESHOLD is met.
  208. */
  209. HC_IRQ_COAL_IO_THRESHOLD = 0x000c,
  210. HC_IRQ_COAL_TIME_THRESHOLD = 0x0010,
  211. SOC_LED_CTRL = 0x2c,
  212. SOC_LED_CTRL_BLINK = (1 << 0), /* Active LED blink */
  213. SOC_LED_CTRL_ACT_PRESENCE = (1 << 2), /* Multiplex dev presence */
  214. /* with dev activity LED */
  215. /* Shadow block registers */
  216. SHD_BLK = 0x100,
  217. SHD_CTL_AST = 0x20, /* ofs from SHD_BLK */
  218. /* SATA registers */
  219. SATA_STATUS = 0x300, /* ctrl, err regs follow status */
  220. SATA_ACTIVE = 0x350,
  221. FIS_IRQ_CAUSE = 0x364,
  222. FIS_IRQ_CAUSE_AN = (1 << 9), /* async notification */
  223. LTMODE = 0x30c, /* requires read-after-write */
  224. LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */
  225. PHY_MODE2 = 0x330,
  226. PHY_MODE3 = 0x310,
  227. PHY_MODE4 = 0x314, /* requires read-after-write */
  228. PHY_MODE4_CFG_MASK = 0x00000003, /* phy internal config field */
  229. PHY_MODE4_CFG_VALUE = 0x00000001, /* phy internal config field */
  230. PHY_MODE4_RSVD_ZEROS = 0x5de3fffa, /* Gen2e always write zeros */
  231. PHY_MODE4_RSVD_ONES = 0x00000005, /* Gen2e always write ones */
  232. SATA_IFCTL = 0x344,
  233. SATA_TESTCTL = 0x348,
  234. SATA_IFSTAT = 0x34c,
  235. VENDOR_UNIQUE_FIS = 0x35c,
  236. FISCFG = 0x360,
  237. FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */
  238. FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */
  239. PHY_MODE9_GEN2 = 0x398,
  240. PHY_MODE9_GEN1 = 0x39c,
  241. PHYCFG_OFS = 0x3a0, /* only in 65n devices */
  242. MV5_PHY_MODE = 0x74,
  243. MV5_LTMODE = 0x30,
  244. MV5_PHY_CTL = 0x0C,
  245. SATA_IFCFG = 0x050,
  246. LP_PHY_CTL = 0x058,
  247. LP_PHY_CTL_PIN_PU_PLL = (1 << 0),
  248. LP_PHY_CTL_PIN_PU_RX = (1 << 1),
  249. LP_PHY_CTL_PIN_PU_TX = (1 << 2),
  250. LP_PHY_CTL_GEN_TX_3G = (1 << 5),
  251. LP_PHY_CTL_GEN_RX_3G = (1 << 9),
  252. MV_M2_PREAMP_MASK = 0x7e0,
  253. /* Port registers */
  254. EDMA_CFG = 0,
  255. EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */
  256. EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */
  257. EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
  258. EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
  259. EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
  260. EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
  261. EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */
  262. EDMA_ERR_IRQ_CAUSE = 0x8,
  263. EDMA_ERR_IRQ_MASK = 0xc,
  264. EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */
  265. EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */
  266. EDMA_ERR_DEV = (1 << 2), /* device error */
  267. EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */
  268. EDMA_ERR_DEV_CON = (1 << 4), /* device connected */
  269. EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */
  270. EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
  271. EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
  272. EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */
  273. EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */
  274. EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */
  275. EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */
  276. EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */
  277. EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */
  278. EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */
  279. EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */
  280. EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */
  281. EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */
  282. EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */
  283. EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */
  284. EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */
  285. EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */
  286. EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */
  287. EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */
  288. EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */
  289. EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */
  290. EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */
  291. EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */
  292. EDMA_ERR_OVERRUN_5 = (1 << 5),
  293. EDMA_ERR_UNDERRUN_5 = (1 << 6),
  294. EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 |
  295. EDMA_ERR_LNK_CTRL_RX_1 |
  296. EDMA_ERR_LNK_CTRL_RX_3 |
  297. EDMA_ERR_LNK_CTRL_TX,
  298. EDMA_EH_FREEZE = EDMA_ERR_D_PAR |
  299. EDMA_ERR_PRD_PAR |
  300. EDMA_ERR_DEV_DCON |
  301. EDMA_ERR_DEV_CON |
  302. EDMA_ERR_SERR |
  303. EDMA_ERR_SELF_DIS |
  304. EDMA_ERR_CRQB_PAR |
  305. EDMA_ERR_CRPB_PAR |
  306. EDMA_ERR_INTRL_PAR |
  307. EDMA_ERR_IORDY |
  308. EDMA_ERR_LNK_CTRL_RX_2 |
  309. EDMA_ERR_LNK_DATA_RX |
  310. EDMA_ERR_LNK_DATA_TX |
  311. EDMA_ERR_TRANS_PROTO,
  312. EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR |
  313. EDMA_ERR_PRD_PAR |
  314. EDMA_ERR_DEV_DCON |
  315. EDMA_ERR_DEV_CON |
  316. EDMA_ERR_OVERRUN_5 |
  317. EDMA_ERR_UNDERRUN_5 |
  318. EDMA_ERR_SELF_DIS_5 |
  319. EDMA_ERR_CRQB_PAR |
  320. EDMA_ERR_CRPB_PAR |
  321. EDMA_ERR_INTRL_PAR |
  322. EDMA_ERR_IORDY,
  323. EDMA_REQ_Q_BASE_HI = 0x10,
  324. EDMA_REQ_Q_IN_PTR = 0x14, /* also contains BASE_LO */
  325. EDMA_REQ_Q_OUT_PTR = 0x18,
  326. EDMA_REQ_Q_PTR_SHIFT = 5,
  327. EDMA_RSP_Q_BASE_HI = 0x1c,
  328. EDMA_RSP_Q_IN_PTR = 0x20,
  329. EDMA_RSP_Q_OUT_PTR = 0x24, /* also contains BASE_LO */
  330. EDMA_RSP_Q_PTR_SHIFT = 3,
  331. EDMA_CMD = 0x28, /* EDMA command register */
  332. EDMA_EN = (1 << 0), /* enable EDMA */
  333. EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
  334. EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */
  335. EDMA_STATUS = 0x30, /* EDMA engine status */
  336. EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */
  337. EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */
  338. EDMA_IORDY_TMOUT = 0x34,
  339. EDMA_ARB_CFG = 0x38,
  340. EDMA_HALTCOND = 0x60, /* GenIIe halt conditions */
  341. EDMA_UNKNOWN_RSVD = 0x6C, /* GenIIe unknown/reserved */
  342. BMDMA_CMD = 0x224, /* bmdma command register */
  343. BMDMA_STATUS = 0x228, /* bmdma status register */
  344. BMDMA_PRD_LOW = 0x22c, /* bmdma PRD addr 31:0 */
  345. BMDMA_PRD_HIGH = 0x230, /* bmdma PRD addr 63:32 */
  346. /* Host private flags (hp_flags) */
  347. MV_HP_FLAG_MSI = (1 << 0),
  348. MV_HP_ERRATA_50XXB0 = (1 << 1),
  349. MV_HP_ERRATA_50XXB2 = (1 << 2),
  350. MV_HP_ERRATA_60X1B2 = (1 << 3),
  351. MV_HP_ERRATA_60X1C0 = (1 << 4),
  352. MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */
  353. MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */
  354. MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */
  355. MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */
  356. MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
  357. MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */
  358. MV_HP_QUIRK_LED_BLINK_EN = (1 << 12), /* is led blinking enabled? */
  359. MV_HP_FIX_LP_PHY_CTL = (1 << 13), /* fix speed in LP_PHY_CTL ? */
  360. /* Port private flags (pp_flags) */
  361. MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
  362. MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */
  363. MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */
  364. MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */
  365. MV_PP_FLAG_FAKE_ATA_BUSY = (1 << 4), /* ignore initial ATA_DRDY */
  366. };
  367. #define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
  368. #define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
  369. #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
  370. #define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
  371. #define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC)
  372. #define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
  373. #define WINDOW_BASE(i) (0x20034 + ((i) << 4))
  374. enum {
  375. /* DMA boundary 0xffff is required by the s/g splitting
  376. * we need on /length/ in mv_fill-sg().
  377. */
  378. MV_DMA_BOUNDARY = 0xffffU,
  379. /* mask of register bits containing lower 32 bits
  380. * of EDMA request queue DMA address
  381. */
  382. EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
  383. /* ditto, for response queue */
  384. EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
  385. };
  386. enum chip_type {
  387. chip_504x,
  388. chip_508x,
  389. chip_5080,
  390. chip_604x,
  391. chip_608x,
  392. chip_6042,
  393. chip_7042,
  394. chip_soc,
  395. };
  396. /* Command ReQuest Block: 32B */
  397. struct mv_crqb {
  398. __le32 sg_addr;
  399. __le32 sg_addr_hi;
  400. __le16 ctrl_flags;
  401. __le16 ata_cmd[11];
  402. };
  403. struct mv_crqb_iie {
  404. __le32 addr;
  405. __le32 addr_hi;
  406. __le32 flags;
  407. __le32 len;
  408. __le32 ata_cmd[4];
  409. };
  410. /* Command ResPonse Block: 8B */
  411. struct mv_crpb {
  412. __le16 id;
  413. __le16 flags;
  414. __le32 tmstmp;
  415. };
  416. /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
  417. struct mv_sg {
  418. __le32 addr;
  419. __le32 flags_size;
  420. __le32 addr_hi;
  421. __le32 reserved;
  422. };
  423. /*
  424. * We keep a local cache of a few frequently accessed port
  425. * registers here, to avoid having to read them (very slow)
  426. * when switching between EDMA and non-EDMA modes.
  427. */
  428. struct mv_cached_regs {
  429. u32 fiscfg;
  430. u32 ltmode;
  431. u32 haltcond;
  432. u32 unknown_rsvd;
  433. };
  434. struct mv_port_priv {
  435. struct mv_crqb *crqb;
  436. dma_addr_t crqb_dma;
  437. struct mv_crpb *crpb;
  438. dma_addr_t crpb_dma;
  439. struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH];
  440. dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH];
  441. unsigned int req_idx;
  442. unsigned int resp_idx;
  443. u32 pp_flags;
  444. struct mv_cached_regs cached;
  445. unsigned int delayed_eh_pmp_map;
  446. };
  447. struct mv_port_signal {
  448. u32 amps;
  449. u32 pre;
  450. };
  451. struct mv_host_priv {
  452. u32 hp_flags;
  453. unsigned int board_idx;
  454. u32 main_irq_mask;
  455. struct mv_port_signal signal[8];
  456. const struct mv_hw_ops *ops;
  457. int n_ports;
  458. void __iomem *base;
  459. void __iomem *main_irq_cause_addr;
  460. void __iomem *main_irq_mask_addr;
  461. u32 irq_cause_offset;
  462. u32 irq_mask_offset;
  463. u32 unmask_all_irqs;
  464. /*
  465. * Needed on some devices that require their clocks to be enabled.
  466. * These are optional: if the platform device does not have any
  467. * clocks, they won't be used. Also, if the underlying hardware
  468. * does not support the common clock framework (CONFIG_HAVE_CLK=n),
  469. * all the clock operations become no-ops (see clk.h).
  470. */
  471. struct clk *clk;
  472. struct clk **port_clks;
  473. /*
  474. * Some devices have a SATA PHY which can be enabled/disabled
  475. * in order to save power. These are optional: if the platform
  476. * devices does not have any phy, they won't be used.
  477. */
  478. struct phy **port_phys;
  479. /*
  480. * These consistent DMA memory pools give us guaranteed
  481. * alignment for hardware-accessed data structures,
  482. * and less memory waste in accomplishing the alignment.
  483. */
  484. struct dma_pool *crqb_pool;
  485. struct dma_pool *crpb_pool;
  486. struct dma_pool *sg_tbl_pool;
  487. };
  488. struct mv_hw_ops {
  489. void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
  490. unsigned int port);
  491. void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
  492. void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
  493. void __iomem *mmio);
  494. int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
  495. unsigned int n_hc);
  496. void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
  497. void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
  498. };
  499. static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
  500. static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
  501. static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
  502. static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
  503. static int mv_port_start(struct ata_port *ap);
  504. static void mv_port_stop(struct ata_port *ap);
  505. static int mv_qc_defer(struct ata_queued_cmd *qc);
  506. static enum ata_completion_errors mv_qc_prep(struct ata_queued_cmd *qc);
  507. static enum ata_completion_errors mv_qc_prep_iie(struct ata_queued_cmd *qc);
  508. static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
  509. static int mv_hardreset(struct ata_link *link, unsigned int *class,
  510. unsigned long deadline);
  511. static void mv_eh_freeze(struct ata_port *ap);
  512. static void mv_eh_thaw(struct ata_port *ap);
  513. static void mv6_dev_config(struct ata_device *dev);
  514. static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
  515. unsigned int port);
  516. static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
  517. static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
  518. void __iomem *mmio);
  519. static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
  520. unsigned int n_hc);
  521. static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
  522. static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio);
  523. static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
  524. unsigned int port);
  525. static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
  526. static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
  527. void __iomem *mmio);
  528. static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
  529. unsigned int n_hc);
  530. static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
  531. static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
  532. void __iomem *mmio);
  533. static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
  534. void __iomem *mmio);
  535. static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
  536. void __iomem *mmio, unsigned int n_hc);
  537. static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
  538. void __iomem *mmio);
  539. static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
  540. static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,
  541. void __iomem *mmio, unsigned int port);
  542. static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
  543. static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
  544. unsigned int port_no);
  545. static int mv_stop_edma(struct ata_port *ap);
  546. static int mv_stop_edma_engine(void __iomem *port_mmio);
  547. static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma);
  548. static void mv_pmp_select(struct ata_port *ap, int pmp);
  549. static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
  550. unsigned long deadline);
  551. static int mv_softreset(struct ata_link *link, unsigned int *class,
  552. unsigned long deadline);
  553. static void mv_pmp_error_handler(struct ata_port *ap);
  554. static void mv_process_crpb_entries(struct ata_port *ap,
  555. struct mv_port_priv *pp);
  556. static void mv_sff_irq_clear(struct ata_port *ap);
  557. static int mv_check_atapi_dma(struct ata_queued_cmd *qc);
  558. static void mv_bmdma_setup(struct ata_queued_cmd *qc);
  559. static void mv_bmdma_start(struct ata_queued_cmd *qc);
  560. static void mv_bmdma_stop(struct ata_queued_cmd *qc);
  561. static u8 mv_bmdma_status(struct ata_port *ap);
  562. static u8 mv_sff_check_status(struct ata_port *ap);
  563. /* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below
  564. * because we have to allow room for worst case splitting of
  565. * PRDs for 64K boundaries in mv_fill_sg().
  566. */
  567. #ifdef CONFIG_PCI
  568. static struct scsi_host_template mv5_sht = {
  569. ATA_BASE_SHT(DRV_NAME),
  570. .sg_tablesize = MV_MAX_SG_CT / 2,
  571. .dma_boundary = MV_DMA_BOUNDARY,
  572. };
  573. #endif
  574. static struct scsi_host_template mv6_sht = {
  575. ATA_NCQ_SHT(DRV_NAME),
  576. .can_queue = MV_MAX_Q_DEPTH - 1,
  577. .sg_tablesize = MV_MAX_SG_CT / 2,
  578. .dma_boundary = MV_DMA_BOUNDARY,
  579. };
  580. static struct ata_port_operations mv5_ops = {
  581. .inherits = &ata_sff_port_ops,
  582. .lost_interrupt = ATA_OP_NULL,
  583. .qc_defer = mv_qc_defer,
  584. .qc_prep = mv_qc_prep,
  585. .qc_issue = mv_qc_issue,
  586. .freeze = mv_eh_freeze,
  587. .thaw = mv_eh_thaw,
  588. .hardreset = mv_hardreset,
  589. .scr_read = mv5_scr_read,
  590. .scr_write = mv5_scr_write,
  591. .port_start = mv_port_start,
  592. .port_stop = mv_port_stop,
  593. };
  594. static struct ata_port_operations mv6_ops = {
  595. .inherits = &ata_bmdma_port_ops,
  596. .lost_interrupt = ATA_OP_NULL,
  597. .qc_defer = mv_qc_defer,
  598. .qc_prep = mv_qc_prep,
  599. .qc_issue = mv_qc_issue,
  600. .dev_config = mv6_dev_config,
  601. .freeze = mv_eh_freeze,
  602. .thaw = mv_eh_thaw,
  603. .hardreset = mv_hardreset,
  604. .softreset = mv_softreset,
  605. .pmp_hardreset = mv_pmp_hardreset,
  606. .pmp_softreset = mv_softreset,
  607. .error_handler = mv_pmp_error_handler,
  608. .scr_read = mv_scr_read,
  609. .scr_write = mv_scr_write,
  610. .sff_check_status = mv_sff_check_status,
  611. .sff_irq_clear = mv_sff_irq_clear,
  612. .check_atapi_dma = mv_check_atapi_dma,
  613. .bmdma_setup = mv_bmdma_setup,
  614. .bmdma_start = mv_bmdma_start,
  615. .bmdma_stop = mv_bmdma_stop,
  616. .bmdma_status = mv_bmdma_status,
  617. .port_start = mv_port_start,
  618. .port_stop = mv_port_stop,
  619. };
  620. static struct ata_port_operations mv_iie_ops = {
  621. .inherits = &mv6_ops,
  622. .dev_config = ATA_OP_NULL,
  623. .qc_prep = mv_qc_prep_iie,
  624. };
  625. static const struct ata_port_info mv_port_info[] = {
  626. { /* chip_504x */
  627. .flags = MV_GEN_I_FLAGS,
  628. .pio_mask = ATA_PIO4,
  629. .udma_mask = ATA_UDMA6,
  630. .port_ops = &mv5_ops,
  631. },
  632. { /* chip_508x */
  633. .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
  634. .pio_mask = ATA_PIO4,
  635. .udma_mask = ATA_UDMA6,
  636. .port_ops = &mv5_ops,
  637. },
  638. { /* chip_5080 */
  639. .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
  640. .pio_mask = ATA_PIO4,
  641. .udma_mask = ATA_UDMA6,
  642. .port_ops = &mv5_ops,
  643. },
  644. { /* chip_604x */
  645. .flags = MV_GEN_II_FLAGS,
  646. .pio_mask = ATA_PIO4,
  647. .udma_mask = ATA_UDMA6,
  648. .port_ops = &mv6_ops,
  649. },
  650. { /* chip_608x */
  651. .flags = MV_GEN_II_FLAGS | MV_FLAG_DUAL_HC,
  652. .pio_mask = ATA_PIO4,
  653. .udma_mask = ATA_UDMA6,
  654. .port_ops = &mv6_ops,
  655. },
  656. { /* chip_6042 */
  657. .flags = MV_GEN_IIE_FLAGS,
  658. .pio_mask = ATA_PIO4,
  659. .udma_mask = ATA_UDMA6,
  660. .port_ops = &mv_iie_ops,
  661. },
  662. { /* chip_7042 */
  663. .flags = MV_GEN_IIE_FLAGS,
  664. .pio_mask = ATA_PIO4,
  665. .udma_mask = ATA_UDMA6,
  666. .port_ops = &mv_iie_ops,
  667. },
  668. { /* chip_soc */
  669. .flags = MV_GEN_IIE_FLAGS,
  670. .pio_mask = ATA_PIO4,
  671. .udma_mask = ATA_UDMA6,
  672. .port_ops = &mv_iie_ops,
  673. },
  674. };
  675. static const struct pci_device_id mv_pci_tbl[] = {
  676. { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
  677. { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
  678. { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
  679. { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
  680. /* RocketRAID 1720/174x have different identifiers */
  681. { PCI_VDEVICE(TTI, 0x1720), chip_6042 },
  682. { PCI_VDEVICE(TTI, 0x1740), chip_6042 },
  683. { PCI_VDEVICE(TTI, 0x1742), chip_6042 },
  684. { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
  685. { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
  686. { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
  687. { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
  688. { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
  689. { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
  690. /* Adaptec 1430SA */
  691. { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 },
  692. /* Marvell 7042 support */
  693. { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
  694. /* Highpoint RocketRAID PCIe series */
  695. { PCI_VDEVICE(TTI, 0x2300), chip_7042 },
  696. { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
  697. { } /* terminate list */
  698. };
  699. static const struct mv_hw_ops mv5xxx_ops = {
  700. .phy_errata = mv5_phy_errata,
  701. .enable_leds = mv5_enable_leds,
  702. .read_preamp = mv5_read_preamp,
  703. .reset_hc = mv5_reset_hc,
  704. .reset_flash = mv5_reset_flash,
  705. .reset_bus = mv5_reset_bus,
  706. };
  707. static const struct mv_hw_ops mv6xxx_ops = {
  708. .phy_errata = mv6_phy_errata,
  709. .enable_leds = mv6_enable_leds,
  710. .read_preamp = mv6_read_preamp,
  711. .reset_hc = mv6_reset_hc,
  712. .reset_flash = mv6_reset_flash,
  713. .reset_bus = mv_reset_pci_bus,
  714. };
  715. static const struct mv_hw_ops mv_soc_ops = {
  716. .phy_errata = mv6_phy_errata,
  717. .enable_leds = mv_soc_enable_leds,
  718. .read_preamp = mv_soc_read_preamp,
  719. .reset_hc = mv_soc_reset_hc,
  720. .reset_flash = mv_soc_reset_flash,
  721. .reset_bus = mv_soc_reset_bus,
  722. };
  723. static const struct mv_hw_ops mv_soc_65n_ops = {
  724. .phy_errata = mv_soc_65n_phy_errata,
  725. .enable_leds = mv_soc_enable_leds,
  726. .reset_hc = mv_soc_reset_hc,
  727. .reset_flash = mv_soc_reset_flash,
  728. .reset_bus = mv_soc_reset_bus,
  729. };
  730. /*
  731. * Functions
  732. */
  733. static inline void writelfl(unsigned long data, void __iomem *addr)
  734. {
  735. writel(data, addr);
  736. (void) readl(addr); /* flush to avoid PCI posted write */
  737. }
  738. static inline unsigned int mv_hc_from_port(unsigned int port)
  739. {
  740. return port >> MV_PORT_HC_SHIFT;
  741. }
  742. static inline unsigned int mv_hardport_from_port(unsigned int port)
  743. {
  744. return port & MV_PORT_MASK;
  745. }
  746. /*
  747. * Consolidate some rather tricky bit shift calculations.
  748. * This is hot-path stuff, so not a function.
  749. * Simple code, with two return values, so macro rather than inline.
  750. *
  751. * port is the sole input, in range 0..7.
  752. * shift is one output, for use with main_irq_cause / main_irq_mask registers.
  753. * hardport is the other output, in range 0..3.
  754. *
  755. * Note that port and hardport may be the same variable in some cases.
  756. */
  757. #define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \
  758. { \
  759. shift = mv_hc_from_port(port) * HC_SHIFT; \
  760. hardport = mv_hardport_from_port(port); \
  761. shift += hardport * 2; \
  762. }
  763. static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
  764. {
  765. return (base + SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
  766. }
  767. static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
  768. unsigned int port)
  769. {
  770. return mv_hc_base(base, mv_hc_from_port(port));
  771. }
  772. static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
  773. {
  774. return mv_hc_base_from_port(base, port) +
  775. MV_SATAHC_ARBTR_REG_SZ +
  776. (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
  777. }
  778. static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
  779. {
  780. void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
  781. unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
  782. return hc_mmio + ofs;
  783. }
  784. static inline void __iomem *mv_host_base(struct ata_host *host)
  785. {
  786. struct mv_host_priv *hpriv = host->private_data;
  787. return hpriv->base;
  788. }
  789. static inline void __iomem *mv_ap_base(struct ata_port *ap)
  790. {
  791. return mv_port_base(mv_host_base(ap->host), ap->port_no);
  792. }
  793. static inline int mv_get_hc_count(unsigned long port_flags)
  794. {
  795. return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
  796. }
  797. /**
  798. * mv_save_cached_regs - (re-)initialize cached port registers
  799. * @ap: the port whose registers we are caching
  800. *
  801. * Initialize the local cache of port registers,
  802. * so that reading them over and over again can
  803. * be avoided on the hotter paths of this driver.
  804. * This saves a few microseconds each time we switch
  805. * to/from EDMA mode to perform (eg.) a drive cache flush.
  806. */
  807. static void mv_save_cached_regs(struct ata_port *ap)
  808. {
  809. void __iomem *port_mmio = mv_ap_base(ap);
  810. struct mv_port_priv *pp = ap->private_data;
  811. pp->cached.fiscfg = readl(port_mmio + FISCFG);
  812. pp->cached.ltmode = readl(port_mmio + LTMODE);
  813. pp->cached.haltcond = readl(port_mmio + EDMA_HALTCOND);
  814. pp->cached.unknown_rsvd = readl(port_mmio + EDMA_UNKNOWN_RSVD);
  815. }
  816. /**
  817. * mv_write_cached_reg - write to a cached port register
  818. * @addr: hardware address of the register
  819. * @old: pointer to cached value of the register
  820. * @new: new value for the register
  821. *
  822. * Write a new value to a cached register,
  823. * but only if the value is different from before.
  824. */
  825. static inline void mv_write_cached_reg(void __iomem *addr, u32 *old, u32 new)
  826. {
  827. if (new != *old) {
  828. unsigned long laddr;
  829. *old = new;
  830. /*
  831. * Workaround for 88SX60x1-B2 FEr SATA#13:
  832. * Read-after-write is needed to prevent generating 64-bit
  833. * write cycles on the PCI bus for SATA interface registers
  834. * at offsets ending in 0x4 or 0xc.
  835. *
  836. * Looks like a lot of fuss, but it avoids an unnecessary
  837. * +1 usec read-after-write delay for unaffected registers.
  838. */
  839. laddr = (unsigned long)addr & 0xffff;
  840. if (laddr >= 0x300 && laddr <= 0x33c) {
  841. laddr &= 0x000f;
  842. if (laddr == 0x4 || laddr == 0xc) {
  843. writelfl(new, addr); /* read after write */
  844. return;
  845. }
  846. }
  847. writel(new, addr); /* unaffected by the errata */
  848. }
  849. }
  850. static void mv_set_edma_ptrs(void __iomem *port_mmio,
  851. struct mv_host_priv *hpriv,
  852. struct mv_port_priv *pp)
  853. {
  854. u32 index;
  855. /*
  856. * initialize request queue
  857. */
  858. pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
  859. index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
  860. WARN_ON(pp->crqb_dma & 0x3ff);
  861. writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI);
  862. writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index,
  863. port_mmio + EDMA_REQ_Q_IN_PTR);
  864. writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR);
  865. /*
  866. * initialize response queue
  867. */
  868. pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
  869. index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT;
  870. WARN_ON(pp->crpb_dma & 0xff);
  871. writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI);
  872. writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR);
  873. writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index,
  874. port_mmio + EDMA_RSP_Q_OUT_PTR);
  875. }
  876. static void mv_write_main_irq_mask(u32 mask, struct mv_host_priv *hpriv)
  877. {
  878. /*
  879. * When writing to the main_irq_mask in hardware,
  880. * we must ensure exclusivity between the interrupt coalescing bits
  881. * and the corresponding individual port DONE_IRQ bits.
  882. *
  883. * Note that this register is really an "IRQ enable" register,
  884. * not an "IRQ mask" register as Marvell's naming might suggest.
  885. */
  886. if (mask & (ALL_PORTS_COAL_DONE | PORTS_0_3_COAL_DONE))
  887. mask &= ~DONE_IRQ_0_3;
  888. if (mask & (ALL_PORTS_COAL_DONE | PORTS_4_7_COAL_DONE))
  889. mask &= ~DONE_IRQ_4_7;
  890. writelfl(mask, hpriv->main_irq_mask_addr);
  891. }
  892. static void mv_set_main_irq_mask(struct ata_host *host,
  893. u32 disable_bits, u32 enable_bits)
  894. {
  895. struct mv_host_priv *hpriv = host->private_data;
  896. u32 old_mask, new_mask;
  897. old_mask = hpriv->main_irq_mask;
  898. new_mask = (old_mask & ~disable_bits) | enable_bits;
  899. if (new_mask != old_mask) {
  900. hpriv->main_irq_mask = new_mask;
  901. mv_write_main_irq_mask(new_mask, hpriv);
  902. }
  903. }
  904. static void mv_enable_port_irqs(struct ata_port *ap,
  905. unsigned int port_bits)
  906. {
  907. unsigned int shift, hardport, port = ap->port_no;
  908. u32 disable_bits, enable_bits;
  909. MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
  910. disable_bits = (DONE_IRQ | ERR_IRQ) << shift;
  911. enable_bits = port_bits << shift;
  912. mv_set_main_irq_mask(ap->host, disable_bits, enable_bits);
  913. }
  914. static void mv_clear_and_enable_port_irqs(struct ata_port *ap,
  915. void __iomem *port_mmio,
  916. unsigned int port_irqs)
  917. {
  918. struct mv_host_priv *hpriv = ap->host->private_data;
  919. int hardport = mv_hardport_from_port(ap->port_no);
  920. void __iomem *hc_mmio = mv_hc_base_from_port(
  921. mv_host_base(ap->host), ap->port_no);
  922. u32 hc_irq_cause;
  923. /* clear EDMA event indicators, if any */
  924. writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
  925. /* clear pending irq events */
  926. hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
  927. writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE);
  928. /* clear FIS IRQ Cause */
  929. if (IS_GEN_IIE(hpriv))
  930. writelfl(0, port_mmio + FIS_IRQ_CAUSE);
  931. mv_enable_port_irqs(ap, port_irqs);
  932. }
  933. static void mv_set_irq_coalescing(struct ata_host *host,
  934. unsigned int count, unsigned int usecs)
  935. {
  936. struct mv_host_priv *hpriv = host->private_data;
  937. void __iomem *mmio = hpriv->base, *hc_mmio;
  938. u32 coal_enable = 0;
  939. unsigned long flags;
  940. unsigned int clks, is_dual_hc = hpriv->n_ports > MV_PORTS_PER_HC;
  941. const u32 coal_disable = PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
  942. ALL_PORTS_COAL_DONE;
  943. /* Disable IRQ coalescing if either threshold is zero */
  944. if (!usecs || !count) {
  945. clks = count = 0;
  946. } else {
  947. /* Respect maximum limits of the hardware */
  948. clks = usecs * COAL_CLOCKS_PER_USEC;
  949. if (clks > MAX_COAL_TIME_THRESHOLD)
  950. clks = MAX_COAL_TIME_THRESHOLD;
  951. if (count > MAX_COAL_IO_COUNT)
  952. count = MAX_COAL_IO_COUNT;
  953. }
  954. spin_lock_irqsave(&host->lock, flags);
  955. mv_set_main_irq_mask(host, coal_disable, 0);
  956. if (is_dual_hc && !IS_GEN_I(hpriv)) {
  957. /*
  958. * GEN_II/GEN_IIE with dual host controllers:
  959. * one set of global thresholds for the entire chip.
  960. */
  961. writel(clks, mmio + IRQ_COAL_TIME_THRESHOLD);
  962. writel(count, mmio + IRQ_COAL_IO_THRESHOLD);
  963. /* clear leftover coal IRQ bit */
  964. writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE);
  965. if (count)
  966. coal_enable = ALL_PORTS_COAL_DONE;
  967. clks = count = 0; /* force clearing of regular regs below */
  968. }
  969. /*
  970. * All chips: independent thresholds for each HC on the chip.
  971. */
  972. hc_mmio = mv_hc_base_from_port(mmio, 0);
  973. writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD);
  974. writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD);
  975. writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE);
  976. if (count)
  977. coal_enable |= PORTS_0_3_COAL_DONE;
  978. if (is_dual_hc) {
  979. hc_mmio = mv_hc_base_from_port(mmio, MV_PORTS_PER_HC);
  980. writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD);
  981. writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD);
  982. writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE);
  983. if (count)
  984. coal_enable |= PORTS_4_7_COAL_DONE;
  985. }
  986. mv_set_main_irq_mask(host, 0, coal_enable);
  987. spin_unlock_irqrestore(&host->lock, flags);
  988. }
  989. /**
  990. * mv_start_edma - Enable eDMA engine
  991. * @base: port base address
  992. * @pp: port private data
  993. *
  994. * Verify the local cache of the eDMA state is accurate with a
  995. * WARN_ON.
  996. *
  997. * LOCKING:
  998. * Inherited from caller.
  999. */
  1000. static void mv_start_edma(struct ata_port *ap, void __iomem *port_mmio,
  1001. struct mv_port_priv *pp, u8 protocol)
  1002. {
  1003. int want_ncq = (protocol == ATA_PROT_NCQ);
  1004. if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
  1005. int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0);
  1006. if (want_ncq != using_ncq)
  1007. mv_stop_edma(ap);
  1008. }
  1009. if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
  1010. struct mv_host_priv *hpriv = ap->host->private_data;
  1011. mv_edma_cfg(ap, want_ncq, 1);
  1012. mv_set_edma_ptrs(port_mmio, hpriv, pp);
  1013. mv_clear_and_enable_port_irqs(ap, port_mmio, DONE_IRQ|ERR_IRQ);
  1014. writelfl(EDMA_EN, port_mmio + EDMA_CMD);
  1015. pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
  1016. }
  1017. }
  1018. static void mv_wait_for_edma_empty_idle(struct ata_port *ap)
  1019. {
  1020. void __iomem *port_mmio = mv_ap_base(ap);
  1021. const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE);
  1022. const int per_loop = 5, timeout = (15 * 1000 / per_loop);
  1023. int i;
  1024. /*
  1025. * Wait for the EDMA engine to finish transactions in progress.
  1026. * No idea what a good "timeout" value might be, but measurements
  1027. * indicate that it often requires hundreds of microseconds
  1028. * with two drives in-use. So we use the 15msec value above
  1029. * as a rough guess at what even more drives might require.
  1030. */
  1031. for (i = 0; i < timeout; ++i) {
  1032. u32 edma_stat = readl(port_mmio + EDMA_STATUS);
  1033. if ((edma_stat & empty_idle) == empty_idle)
  1034. break;
  1035. udelay(per_loop);
  1036. }
  1037. /* ata_port_info(ap, "%s: %u+ usecs\n", __func__, i); */
  1038. }
  1039. /**
  1040. * mv_stop_edma_engine - Disable eDMA engine
  1041. * @port_mmio: io base address
  1042. *
  1043. * LOCKING:
  1044. * Inherited from caller.
  1045. */
  1046. static int mv_stop_edma_engine(void __iomem *port_mmio)
  1047. {
  1048. int i;
  1049. /* Disable eDMA. The disable bit auto clears. */
  1050. writelfl(EDMA_DS, port_mmio + EDMA_CMD);
  1051. /* Wait for the chip to confirm eDMA is off. */
  1052. for (i = 10000; i > 0; i--) {
  1053. u32 reg = readl(port_mmio + EDMA_CMD);
  1054. if (!(reg & EDMA_EN))
  1055. return 0;
  1056. udelay(10);
  1057. }
  1058. return -EIO;
  1059. }
  1060. static int mv_stop_edma(struct ata_port *ap)
  1061. {
  1062. void __iomem *port_mmio = mv_ap_base(ap);
  1063. struct mv_port_priv *pp = ap->private_data;
  1064. int err = 0;
  1065. if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
  1066. return 0;
  1067. pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
  1068. mv_wait_for_edma_empty_idle(ap);
  1069. if (mv_stop_edma_engine(port_mmio)) {
  1070. ata_port_err(ap, "Unable to stop eDMA\n");
  1071. err = -EIO;
  1072. }
  1073. mv_edma_cfg(ap, 0, 0);
  1074. return err;
  1075. }
  1076. #ifdef ATA_DEBUG
  1077. static void mv_dump_mem(void __iomem *start, unsigned bytes)
  1078. {
  1079. int b, w;
  1080. for (b = 0; b < bytes; ) {
  1081. DPRINTK("%p: ", start + b);
  1082. for (w = 0; b < bytes && w < 4; w++) {
  1083. printk("%08x ", readl(start + b));
  1084. b += sizeof(u32);
  1085. }
  1086. printk("\n");
  1087. }
  1088. }
  1089. #endif
  1090. #if defined(ATA_DEBUG) || defined(CONFIG_PCI)
  1091. static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
  1092. {
  1093. #ifdef ATA_DEBUG
  1094. int b, w;
  1095. u32 dw;
  1096. for (b = 0; b < bytes; ) {
  1097. DPRINTK("%02x: ", b);
  1098. for (w = 0; b < bytes && w < 4; w++) {
  1099. (void) pci_read_config_dword(pdev, b, &dw);
  1100. printk("%08x ", dw);
  1101. b += sizeof(u32);
  1102. }
  1103. printk("\n");
  1104. }
  1105. #endif
  1106. }
  1107. #endif
  1108. static void mv_dump_all_regs(void __iomem *mmio_base, int port,
  1109. struct pci_dev *pdev)
  1110. {
  1111. #ifdef ATA_DEBUG
  1112. void __iomem *hc_base = mv_hc_base(mmio_base,
  1113. port >> MV_PORT_HC_SHIFT);
  1114. void __iomem *port_base;
  1115. int start_port, num_ports, p, start_hc, num_hcs, hc;
  1116. if (0 > port) {
  1117. start_hc = start_port = 0;
  1118. num_ports = 8; /* shld be benign for 4 port devs */
  1119. num_hcs = 2;
  1120. } else {
  1121. start_hc = port >> MV_PORT_HC_SHIFT;
  1122. start_port = port;
  1123. num_ports = num_hcs = 1;
  1124. }
  1125. DPRINTK("All registers for port(s) %u-%u:\n", start_port,
  1126. num_ports > 1 ? num_ports - 1 : start_port);
  1127. if (NULL != pdev) {
  1128. DPRINTK("PCI config space regs:\n");
  1129. mv_dump_pci_cfg(pdev, 0x68);
  1130. }
  1131. DPRINTK("PCI regs:\n");
  1132. mv_dump_mem(mmio_base+0xc00, 0x3c);
  1133. mv_dump_mem(mmio_base+0xd00, 0x34);
  1134. mv_dump_mem(mmio_base+0xf00, 0x4);
  1135. mv_dump_mem(mmio_base+0x1d00, 0x6c);
  1136. for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
  1137. hc_base = mv_hc_base(mmio_base, hc);
  1138. DPRINTK("HC regs (HC %i):\n", hc);
  1139. mv_dump_mem(hc_base, 0x1c);
  1140. }
  1141. for (p = start_port; p < start_port + num_ports; p++) {
  1142. port_base = mv_port_base(mmio_base, p);
  1143. DPRINTK("EDMA regs (port %i):\n", p);
  1144. mv_dump_mem(port_base, 0x54);
  1145. DPRINTK("SATA regs (port %i):\n", p);
  1146. mv_dump_mem(port_base+0x300, 0x60);
  1147. }
  1148. #endif
  1149. }
  1150. static unsigned int mv_scr_offset(unsigned int sc_reg_in)
  1151. {
  1152. unsigned int ofs;
  1153. switch (sc_reg_in) {
  1154. case SCR_STATUS:
  1155. case SCR_CONTROL:
  1156. case SCR_ERROR:
  1157. ofs = SATA_STATUS + (sc_reg_in * sizeof(u32));
  1158. break;
  1159. case SCR_ACTIVE:
  1160. ofs = SATA_ACTIVE; /* active is not with the others */
  1161. break;
  1162. default:
  1163. ofs = 0xffffffffU;
  1164. break;
  1165. }
  1166. return ofs;
  1167. }
  1168. static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
  1169. {
  1170. unsigned int ofs = mv_scr_offset(sc_reg_in);
  1171. if (ofs != 0xffffffffU) {
  1172. *val = readl(mv_ap_base(link->ap) + ofs);
  1173. return 0;
  1174. } else
  1175. return -EINVAL;
  1176. }
  1177. static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
  1178. {
  1179. unsigned int ofs = mv_scr_offset(sc_reg_in);
  1180. if (ofs != 0xffffffffU) {
  1181. void __iomem *addr = mv_ap_base(link->ap) + ofs;
  1182. struct mv_host_priv *hpriv = link->ap->host->private_data;
  1183. if (sc_reg_in == SCR_CONTROL) {
  1184. /*
  1185. * Workaround for 88SX60x1 FEr SATA#26:
  1186. *
  1187. * COMRESETs have to take care not to accidentally
  1188. * put the drive to sleep when writing SCR_CONTROL.
  1189. * Setting bits 12..15 prevents this problem.
  1190. *
  1191. * So if we see an outbound COMMRESET, set those bits.
  1192. * Ditto for the followup write that clears the reset.
  1193. *
  1194. * The proprietary driver does this for
  1195. * all chip versions, and so do we.
  1196. */
  1197. if ((val & 0xf) == 1 || (readl(addr) & 0xf) == 1)
  1198. val |= 0xf000;
  1199. if (hpriv->hp_flags & MV_HP_FIX_LP_PHY_CTL) {
  1200. void __iomem *lp_phy_addr =
  1201. mv_ap_base(link->ap) + LP_PHY_CTL;
  1202. /*
  1203. * Set PHY speed according to SControl speed.
  1204. */
  1205. u32 lp_phy_val =
  1206. LP_PHY_CTL_PIN_PU_PLL |
  1207. LP_PHY_CTL_PIN_PU_RX |
  1208. LP_PHY_CTL_PIN_PU_TX;
  1209. if ((val & 0xf0) != 0x10)
  1210. lp_phy_val |=
  1211. LP_PHY_CTL_GEN_TX_3G |
  1212. LP_PHY_CTL_GEN_RX_3G;
  1213. writelfl(lp_phy_val, lp_phy_addr);
  1214. }
  1215. }
  1216. writelfl(val, addr);
  1217. return 0;
  1218. } else
  1219. return -EINVAL;
  1220. }
  1221. static void mv6_dev_config(struct ata_device *adev)
  1222. {
  1223. /*
  1224. * Deal with Gen-II ("mv6") hardware quirks/restrictions:
  1225. *
  1226. * Gen-II does not support NCQ over a port multiplier
  1227. * (no FIS-based switching).
  1228. */
  1229. if (adev->flags & ATA_DFLAG_NCQ) {
  1230. if (sata_pmp_attached(adev->link->ap)) {
  1231. adev->flags &= ~ATA_DFLAG_NCQ;
  1232. ata_dev_info(adev,
  1233. "NCQ disabled for command-based switching\n");
  1234. }
  1235. }
  1236. }
  1237. static int mv_qc_defer(struct ata_queued_cmd *qc)
  1238. {
  1239. struct ata_link *link = qc->dev->link;
  1240. struct ata_port *ap = link->ap;
  1241. struct mv_port_priv *pp = ap->private_data;
  1242. /*
  1243. * Don't allow new commands if we're in a delayed EH state
  1244. * for NCQ and/or FIS-based switching.
  1245. */
  1246. if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
  1247. return ATA_DEFER_PORT;
  1248. /* PIO commands need exclusive link: no other commands [DMA or PIO]
  1249. * can run concurrently.
  1250. * set excl_link when we want to send a PIO command in DMA mode
  1251. * or a non-NCQ command in NCQ mode.
  1252. * When we receive a command from that link, and there are no
  1253. * outstanding commands, mark a flag to clear excl_link and let
  1254. * the command go through.
  1255. */
  1256. if (unlikely(ap->excl_link)) {
  1257. if (link == ap->excl_link) {
  1258. if (ap->nr_active_links)
  1259. return ATA_DEFER_PORT;
  1260. qc->flags |= ATA_QCFLAG_CLEAR_EXCL;
  1261. return 0;
  1262. } else
  1263. return ATA_DEFER_PORT;
  1264. }
  1265. /*
  1266. * If the port is completely idle, then allow the new qc.
  1267. */
  1268. if (ap->nr_active_links == 0)
  1269. return 0;
  1270. /*
  1271. * The port is operating in host queuing mode (EDMA) with NCQ
  1272. * enabled, allow multiple NCQ commands. EDMA also allows
  1273. * queueing multiple DMA commands but libata core currently
  1274. * doesn't allow it.
  1275. */
  1276. if ((pp->pp_flags & MV_PP_FLAG_EDMA_EN) &&
  1277. (pp->pp_flags & MV_PP_FLAG_NCQ_EN)) {
  1278. if (ata_is_ncq(qc->tf.protocol))
  1279. return 0;
  1280. else {
  1281. ap->excl_link = link;
  1282. return ATA_DEFER_PORT;
  1283. }
  1284. }
  1285. return ATA_DEFER_PORT;
  1286. }
  1287. static void mv_config_fbs(struct ata_port *ap, int want_ncq, int want_fbs)
  1288. {
  1289. struct mv_port_priv *pp = ap->private_data;
  1290. void __iomem *port_mmio;
  1291. u32 fiscfg, *old_fiscfg = &pp->cached.fiscfg;
  1292. u32 ltmode, *old_ltmode = &pp->cached.ltmode;
  1293. u32 haltcond, *old_haltcond = &pp->cached.haltcond;
  1294. ltmode = *old_ltmode & ~LTMODE_BIT8;
  1295. haltcond = *old_haltcond | EDMA_ERR_DEV;
  1296. if (want_fbs) {
  1297. fiscfg = *old_fiscfg | FISCFG_SINGLE_SYNC;
  1298. ltmode = *old_ltmode | LTMODE_BIT8;
  1299. if (want_ncq)
  1300. haltcond &= ~EDMA_ERR_DEV;
  1301. else
  1302. fiscfg |= FISCFG_WAIT_DEV_ERR;
  1303. } else {
  1304. fiscfg = *old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR);
  1305. }
  1306. port_mmio = mv_ap_base(ap);
  1307. mv_write_cached_reg(port_mmio + FISCFG, old_fiscfg, fiscfg);
  1308. mv_write_cached_reg(port_mmio + LTMODE, old_ltmode, ltmode);
  1309. mv_write_cached_reg(port_mmio + EDMA_HALTCOND, old_haltcond, haltcond);
  1310. }
  1311. static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq)
  1312. {
  1313. struct mv_host_priv *hpriv = ap->host->private_data;
  1314. u32 old, new;
  1315. /* workaround for 88SX60x1 FEr SATA#25 (part 1) */
  1316. old = readl(hpriv->base + GPIO_PORT_CTL);
  1317. if (want_ncq)
  1318. new = old | (1 << 22);
  1319. else
  1320. new = old & ~(1 << 22);
  1321. if (new != old)
  1322. writel(new, hpriv->base + GPIO_PORT_CTL);
  1323. }
  1324. /**
  1325. * mv_bmdma_enable - set a magic bit on GEN_IIE to allow bmdma
  1326. * @ap: Port being initialized
  1327. *
  1328. * There are two DMA modes on these chips: basic DMA, and EDMA.
  1329. *
  1330. * Bit-0 of the "EDMA RESERVED" register enables/disables use
  1331. * of basic DMA on the GEN_IIE versions of the chips.
  1332. *
  1333. * This bit survives EDMA resets, and must be set for basic DMA
  1334. * to function, and should be cleared when EDMA is active.
  1335. */
  1336. static void mv_bmdma_enable_iie(struct ata_port *ap, int enable_bmdma)
  1337. {
  1338. struct mv_port_priv *pp = ap->private_data;
  1339. u32 new, *old = &pp->cached.unknown_rsvd;
  1340. if (enable_bmdma)
  1341. new = *old | 1;
  1342. else
  1343. new = *old & ~1;
  1344. mv_write_cached_reg(mv_ap_base(ap) + EDMA_UNKNOWN_RSVD, old, new);
  1345. }
  1346. /*
  1347. * SOC chips have an issue whereby the HDD LEDs don't always blink
  1348. * during I/O when NCQ is enabled. Enabling a special "LED blink" mode
  1349. * of the SOC takes care of it, generating a steady blink rate when
  1350. * any drive on the chip is active.
  1351. *
  1352. * Unfortunately, the blink mode is a global hardware setting for the SOC,
  1353. * so we must use it whenever at least one port on the SOC has NCQ enabled.
  1354. *
  1355. * We turn "LED blink" off when NCQ is not in use anywhere, because the normal
  1356. * LED operation works then, and provides better (more accurate) feedback.
  1357. *
  1358. * Note that this code assumes that an SOC never has more than one HC onboard.
  1359. */
  1360. static void mv_soc_led_blink_enable(struct ata_port *ap)
  1361. {
  1362. struct ata_host *host = ap->host;
  1363. struct mv_host_priv *hpriv = host->private_data;
  1364. void __iomem *hc_mmio;
  1365. u32 led_ctrl;
  1366. if (hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN)
  1367. return;
  1368. hpriv->hp_flags |= MV_HP_QUIRK_LED_BLINK_EN;
  1369. hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no);
  1370. led_ctrl = readl(hc_mmio + SOC_LED_CTRL);
  1371. writel(led_ctrl | SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL);
  1372. }
  1373. static void mv_soc_led_blink_disable(struct ata_port *ap)
  1374. {
  1375. struct ata_host *host = ap->host;
  1376. struct mv_host_priv *hpriv = host->private_data;
  1377. void __iomem *hc_mmio;
  1378. u32 led_ctrl;
  1379. unsigned int port;
  1380. if (!(hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN))
  1381. return;
  1382. /* disable led-blink only if no ports are using NCQ */
  1383. for (port = 0; port < hpriv->n_ports; port++) {
  1384. struct ata_port *this_ap = host->ports[port];
  1385. struct mv_port_priv *pp = this_ap->private_data;
  1386. if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
  1387. return;
  1388. }
  1389. hpriv->hp_flags &= ~MV_HP_QUIRK_LED_BLINK_EN;
  1390. hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no);
  1391. led_ctrl = readl(hc_mmio + SOC_LED_CTRL);
  1392. writel(led_ctrl & ~SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL);
  1393. }
  1394. static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma)
  1395. {
  1396. u32 cfg;
  1397. struct mv_port_priv *pp = ap->private_data;
  1398. struct mv_host_priv *hpriv = ap->host->private_data;
  1399. void __iomem *port_mmio = mv_ap_base(ap);
  1400. /* set up non-NCQ EDMA configuration */
  1401. cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */
  1402. pp->pp_flags &=
  1403. ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY);
  1404. if (IS_GEN_I(hpriv))
  1405. cfg |= (1 << 8); /* enab config burst size mask */
  1406. else if (IS_GEN_II(hpriv)) {
  1407. cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
  1408. mv_60x1_errata_sata25(ap, want_ncq);
  1409. } else if (IS_GEN_IIE(hpriv)) {
  1410. int want_fbs = sata_pmp_attached(ap);
  1411. /*
  1412. * Possible future enhancement:
  1413. *
  1414. * The chip can use FBS with non-NCQ, if we allow it,
  1415. * But first we need to have the error handling in place
  1416. * for this mode (datasheet section 7.3.15.4.2.3).
  1417. * So disallow non-NCQ FBS for now.
  1418. */
  1419. want_fbs &= want_ncq;
  1420. mv_config_fbs(ap, want_ncq, want_fbs);
  1421. if (want_fbs) {
  1422. pp->pp_flags |= MV_PP_FLAG_FBS_EN;
  1423. cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */
  1424. }
  1425. cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
  1426. if (want_edma) {
  1427. cfg |= (1 << 22); /* enab 4-entry host queue cache */
  1428. if (!IS_SOC(hpriv))
  1429. cfg |= (1 << 18); /* enab early completion */
  1430. }
  1431. if (hpriv->hp_flags & MV_HP_CUT_THROUGH)
  1432. cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */
  1433. mv_bmdma_enable_iie(ap, !want_edma);
  1434. if (IS_SOC(hpriv)) {
  1435. if (want_ncq)
  1436. mv_soc_led_blink_enable(ap);
  1437. else
  1438. mv_soc_led_blink_disable(ap);
  1439. }
  1440. }
  1441. if (want_ncq) {
  1442. cfg |= EDMA_CFG_NCQ;
  1443. pp->pp_flags |= MV_PP_FLAG_NCQ_EN;
  1444. }
  1445. writelfl(cfg, port_mmio + EDMA_CFG);
  1446. }
  1447. static void mv_port_free_dma_mem(struct ata_port *ap)
  1448. {
  1449. struct mv_host_priv *hpriv = ap->host->private_data;
  1450. struct mv_port_priv *pp = ap->private_data;
  1451. int tag;
  1452. if (pp->crqb) {
  1453. dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);
  1454. pp->crqb = NULL;
  1455. }
  1456. if (pp->crpb) {
  1457. dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);
  1458. pp->crpb = NULL;
  1459. }
  1460. /*
  1461. * For GEN_I, there's no NCQ, so we have only a single sg_tbl.
  1462. * For later hardware, we have one unique sg_tbl per NCQ tag.
  1463. */
  1464. for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
  1465. if (pp->sg_tbl[tag]) {
  1466. if (tag == 0 || !IS_GEN_I(hpriv))
  1467. dma_pool_free(hpriv->sg_tbl_pool,
  1468. pp->sg_tbl[tag],
  1469. pp->sg_tbl_dma[tag]);
  1470. pp->sg_tbl[tag] = NULL;
  1471. }
  1472. }
  1473. }
  1474. /**
  1475. * mv_port_start - Port specific init/start routine.
  1476. * @ap: ATA channel to manipulate
  1477. *
  1478. * Allocate and point to DMA memory, init port private memory,
  1479. * zero indices.
  1480. *
  1481. * LOCKING:
  1482. * Inherited from caller.
  1483. */
  1484. static int mv_port_start(struct ata_port *ap)
  1485. {
  1486. struct device *dev = ap->host->dev;
  1487. struct mv_host_priv *hpriv = ap->host->private_data;
  1488. struct mv_port_priv *pp;
  1489. unsigned long flags;
  1490. int tag;
  1491. pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
  1492. if (!pp)
  1493. return -ENOMEM;
  1494. ap->private_data = pp;
  1495. pp->crqb = dma_pool_zalloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);
  1496. if (!pp->crqb)
  1497. return -ENOMEM;
  1498. pp->crpb = dma_pool_zalloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);
  1499. if (!pp->crpb)
  1500. goto out_port_free_dma_mem;
  1501. /* 6041/6081 Rev. "C0" (and newer) are okay with async notify */
  1502. if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0)
  1503. ap->flags |= ATA_FLAG_AN;
  1504. /*
  1505. * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
  1506. * For later hardware, we need one unique sg_tbl per NCQ tag.
  1507. */
  1508. for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
  1509. if (tag == 0 || !IS_GEN_I(hpriv)) {
  1510. pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool,
  1511. GFP_KERNEL, &pp->sg_tbl_dma[tag]);
  1512. if (!pp->sg_tbl[tag])
  1513. goto out_port_free_dma_mem;
  1514. } else {
  1515. pp->sg_tbl[tag] = pp->sg_tbl[0];
  1516. pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0];
  1517. }
  1518. }
  1519. spin_lock_irqsave(ap->lock, flags);
  1520. mv_save_cached_regs(ap);
  1521. mv_edma_cfg(ap, 0, 0);
  1522. spin_unlock_irqrestore(ap->lock, flags);
  1523. return 0;
  1524. out_port_free_dma_mem:
  1525. mv_port_free_dma_mem(ap);
  1526. return -ENOMEM;
  1527. }
  1528. /**
  1529. * mv_port_stop - Port specific cleanup/stop routine.
  1530. * @ap: ATA channel to manipulate
  1531. *
  1532. * Stop DMA, cleanup port memory.
  1533. *
  1534. * LOCKING:
  1535. * This routine uses the host lock to protect the DMA stop.
  1536. */
  1537. static void mv_port_stop(struct ata_port *ap)
  1538. {
  1539. unsigned long flags;
  1540. spin_lock_irqsave(ap->lock, flags);
  1541. mv_stop_edma(ap);
  1542. mv_enable_port_irqs(ap, 0);
  1543. spin_unlock_irqrestore(ap->lock, flags);
  1544. mv_port_free_dma_mem(ap);
  1545. }
  1546. /**
  1547. * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
  1548. * @qc: queued command whose SG list to source from
  1549. *
  1550. * Populate the SG list and mark the last entry.
  1551. *
  1552. * LOCKING:
  1553. * Inherited from caller.
  1554. */
  1555. static void mv_fill_sg(struct ata_queued_cmd *qc)
  1556. {
  1557. struct mv_port_priv *pp = qc->ap->private_data;
  1558. struct scatterlist *sg;
  1559. struct mv_sg *mv_sg, *last_sg = NULL;
  1560. unsigned int si;
  1561. mv_sg = pp->sg_tbl[qc->hw_tag];
  1562. for_each_sg(qc->sg, sg, qc->n_elem, si) {
  1563. dma_addr_t addr = sg_dma_address(sg);
  1564. u32 sg_len = sg_dma_len(sg);
  1565. while (sg_len) {
  1566. u32 offset = addr & 0xffff;
  1567. u32 len = sg_len;
  1568. if (offset + len > 0x10000)
  1569. len = 0x10000 - offset;
  1570. mv_sg->addr = cpu_to_le32(addr & 0xffffffff);
  1571. mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
  1572. mv_sg->flags_size = cpu_to_le32(len & 0xffff);
  1573. mv_sg->reserved = 0;
  1574. sg_len -= len;
  1575. addr += len;
  1576. last_sg = mv_sg;
  1577. mv_sg++;
  1578. }
  1579. }
  1580. if (likely(last_sg))
  1581. last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
  1582. mb(); /* ensure data structure is visible to the chipset */
  1583. }
  1584. static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
  1585. {
  1586. u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
  1587. (last ? CRQB_CMD_LAST : 0);
  1588. *cmdw = cpu_to_le16(tmp);
  1589. }
  1590. /**
  1591. * mv_sff_irq_clear - Clear hardware interrupt after DMA.
  1592. * @ap: Port associated with this ATA transaction.
  1593. *
  1594. * We need this only for ATAPI bmdma transactions,
  1595. * as otherwise we experience spurious interrupts
  1596. * after libata-sff handles the bmdma interrupts.
  1597. */
  1598. static void mv_sff_irq_clear(struct ata_port *ap)
  1599. {
  1600. mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), ERR_IRQ);
  1601. }
  1602. /**
  1603. * mv_check_atapi_dma - Filter ATAPI cmds which are unsuitable for DMA.
  1604. * @qc: queued command to check for chipset/DMA compatibility.
  1605. *
  1606. * The bmdma engines cannot handle speculative data sizes
  1607. * (bytecount under/over flow). So only allow DMA for
  1608. * data transfer commands with known data sizes.
  1609. *
  1610. * LOCKING:
  1611. * Inherited from caller.
  1612. */
  1613. static int mv_check_atapi_dma(struct ata_queued_cmd *qc)
  1614. {
  1615. struct scsi_cmnd *scmd = qc->scsicmd;
  1616. if (scmd) {
  1617. switch (scmd->cmnd[0]) {
  1618. case READ_6:
  1619. case READ_10:
  1620. case READ_12:
  1621. case WRITE_6:
  1622. case WRITE_10:
  1623. case WRITE_12:
  1624. case GPCMD_READ_CD:
  1625. case GPCMD_SEND_DVD_STRUCTURE:
  1626. case GPCMD_SEND_CUE_SHEET:
  1627. return 0; /* DMA is safe */
  1628. }
  1629. }
  1630. return -EOPNOTSUPP; /* use PIO instead */
  1631. }
  1632. /**
  1633. * mv_bmdma_setup - Set up BMDMA transaction
  1634. * @qc: queued command to prepare DMA for.
  1635. *
  1636. * LOCKING:
  1637. * Inherited from caller.
  1638. */
  1639. static void mv_bmdma_setup(struct ata_queued_cmd *qc)
  1640. {
  1641. struct ata_port *ap = qc->ap;
  1642. void __iomem *port_mmio = mv_ap_base(ap);
  1643. struct mv_port_priv *pp = ap->private_data;
  1644. mv_fill_sg(qc);
  1645. /* clear all DMA cmd bits */
  1646. writel(0, port_mmio + BMDMA_CMD);
  1647. /* load PRD table addr. */
  1648. writel((pp->sg_tbl_dma[qc->hw_tag] >> 16) >> 16,
  1649. port_mmio + BMDMA_PRD_HIGH);
  1650. writelfl(pp->sg_tbl_dma[qc->hw_tag],
  1651. port_mmio + BMDMA_PRD_LOW);
  1652. /* issue r/w command */
  1653. ap->ops->sff_exec_command(ap, &qc->tf);
  1654. }
  1655. /**
  1656. * mv_bmdma_start - Start a BMDMA transaction
  1657. * @qc: queued command to start DMA on.
  1658. *
  1659. * LOCKING:
  1660. * Inherited from caller.
  1661. */
  1662. static void mv_bmdma_start(struct ata_queued_cmd *qc)
  1663. {
  1664. struct ata_port *ap = qc->ap;
  1665. void __iomem *port_mmio = mv_ap_base(ap);
  1666. unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
  1667. u32 cmd = (rw ? 0 : ATA_DMA_WR) | ATA_DMA_START;
  1668. /* start host DMA transaction */
  1669. writelfl(cmd, port_mmio + BMDMA_CMD);
  1670. }
  1671. /**
  1672. * mv_bmdma_stop - Stop BMDMA transfer
  1673. * @qc: queued command to stop DMA on.
  1674. *
  1675. * Clears the ATA_DMA_START flag in the bmdma control register
  1676. *
  1677. * LOCKING:
  1678. * Inherited from caller.
  1679. */
  1680. static void mv_bmdma_stop_ap(struct ata_port *ap)
  1681. {
  1682. void __iomem *port_mmio = mv_ap_base(ap);
  1683. u32 cmd;
  1684. /* clear start/stop bit */
  1685. cmd = readl(port_mmio + BMDMA_CMD);
  1686. if (cmd & ATA_DMA_START) {
  1687. cmd &= ~ATA_DMA_START;
  1688. writelfl(cmd, port_mmio + BMDMA_CMD);
  1689. /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
  1690. ata_sff_dma_pause(ap);
  1691. }
  1692. }
  1693. static void mv_bmdma_stop(struct ata_queued_cmd *qc)
  1694. {
  1695. mv_bmdma_stop_ap(qc->ap);
  1696. }
  1697. /**
  1698. * mv_bmdma_status - Read BMDMA status
  1699. * @ap: port for which to retrieve DMA status.
  1700. *
  1701. * Read and return equivalent of the sff BMDMA status register.
  1702. *
  1703. * LOCKING:
  1704. * Inherited from caller.
  1705. */
  1706. static u8 mv_bmdma_status(struct ata_port *ap)
  1707. {
  1708. void __iomem *port_mmio = mv_ap_base(ap);
  1709. u32 reg, status;
  1710. /*
  1711. * Other bits are valid only if ATA_DMA_ACTIVE==0,
  1712. * and the ATA_DMA_INTR bit doesn't exist.
  1713. */
  1714. reg = readl(port_mmio + BMDMA_STATUS);
  1715. if (reg & ATA_DMA_ACTIVE)
  1716. status = ATA_DMA_ACTIVE;
  1717. else if (reg & ATA_DMA_ERR)
  1718. status = (reg & ATA_DMA_ERR) | ATA_DMA_INTR;
  1719. else {
  1720. /*
  1721. * Just because DMA_ACTIVE is 0 (DMA completed),
  1722. * this does _not_ mean the device is "done".
  1723. * So we should not yet be signalling ATA_DMA_INTR
  1724. * in some cases. Eg. DSM/TRIM, and perhaps others.
  1725. */
  1726. mv_bmdma_stop_ap(ap);
  1727. if (ioread8(ap->ioaddr.altstatus_addr) & ATA_BUSY)
  1728. status = 0;
  1729. else
  1730. status = ATA_DMA_INTR;
  1731. }
  1732. return status;
  1733. }
  1734. static void mv_rw_multi_errata_sata24(struct ata_queued_cmd *qc)
  1735. {
  1736. struct ata_taskfile *tf = &qc->tf;
  1737. /*
  1738. * Workaround for 88SX60x1 FEr SATA#24.
  1739. *
  1740. * Chip may corrupt WRITEs if multi_count >= 4kB.
  1741. * Note that READs are unaffected.
  1742. *
  1743. * It's not clear if this errata really means "4K bytes",
  1744. * or if it always happens for multi_count > 7
  1745. * regardless of device sector_size.
  1746. *
  1747. * So, for safety, any write with multi_count > 7
  1748. * gets converted here into a regular PIO write instead:
  1749. */
  1750. if ((tf->flags & ATA_TFLAG_WRITE) && is_multi_taskfile(tf)) {
  1751. if (qc->dev->multi_count > 7) {
  1752. switch (tf->command) {
  1753. case ATA_CMD_WRITE_MULTI:
  1754. tf->command = ATA_CMD_PIO_WRITE;
  1755. break;
  1756. case ATA_CMD_WRITE_MULTI_FUA_EXT:
  1757. tf->flags &= ~ATA_TFLAG_FUA; /* ugh */
  1758. fallthrough;
  1759. case ATA_CMD_WRITE_MULTI_EXT:
  1760. tf->command = ATA_CMD_PIO_WRITE_EXT;
  1761. break;
  1762. }
  1763. }
  1764. }
  1765. }
  1766. /**
  1767. * mv_qc_prep - Host specific command preparation.
  1768. * @qc: queued command to prepare
  1769. *
  1770. * This routine simply redirects to the general purpose routine
  1771. * if command is not DMA. Else, it handles prep of the CRQB
  1772. * (command request block), does some sanity checking, and calls
  1773. * the SG load routine.
  1774. *
  1775. * LOCKING:
  1776. * Inherited from caller.
  1777. */
  1778. static enum ata_completion_errors mv_qc_prep(struct ata_queued_cmd *qc)
  1779. {
  1780. struct ata_port *ap = qc->ap;
  1781. struct mv_port_priv *pp = ap->private_data;
  1782. __le16 *cw;
  1783. struct ata_taskfile *tf = &qc->tf;
  1784. u16 flags = 0;
  1785. unsigned in_index;
  1786. switch (tf->protocol) {
  1787. case ATA_PROT_DMA:
  1788. if (tf->command == ATA_CMD_DSM)
  1789. return AC_ERR_OK;
  1790. fallthrough;
  1791. case ATA_PROT_NCQ:
  1792. break; /* continue below */
  1793. case ATA_PROT_PIO:
  1794. mv_rw_multi_errata_sata24(qc);
  1795. return AC_ERR_OK;
  1796. default:
  1797. return AC_ERR_OK;
  1798. }
  1799. /* Fill in command request block
  1800. */
  1801. if (!(tf->flags & ATA_TFLAG_WRITE))
  1802. flags |= CRQB_FLAG_READ;
  1803. WARN_ON(MV_MAX_Q_DEPTH <= qc->hw_tag);
  1804. flags |= qc->hw_tag << CRQB_TAG_SHIFT;
  1805. flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
  1806. /* get current queue index from software */
  1807. in_index = pp->req_idx;
  1808. pp->crqb[in_index].sg_addr =
  1809. cpu_to_le32(pp->sg_tbl_dma[qc->hw_tag] & 0xffffffff);
  1810. pp->crqb[in_index].sg_addr_hi =
  1811. cpu_to_le32((pp->sg_tbl_dma[qc->hw_tag] >> 16) >> 16);
  1812. pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
  1813. cw = &pp->crqb[in_index].ata_cmd[0];
  1814. /* Sadly, the CRQB cannot accommodate all registers--there are
  1815. * only 11 bytes...so we must pick and choose required
  1816. * registers based on the command. So, we drop feature and
  1817. * hob_feature for [RW] DMA commands, but they are needed for
  1818. * NCQ. NCQ will drop hob_nsect, which is not needed there
  1819. * (nsect is used only for the tag; feat/hob_feat hold true nsect).
  1820. */
  1821. switch (tf->command) {
  1822. case ATA_CMD_READ:
  1823. case ATA_CMD_READ_EXT:
  1824. case ATA_CMD_WRITE:
  1825. case ATA_CMD_WRITE_EXT:
  1826. case ATA_CMD_WRITE_FUA_EXT:
  1827. mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
  1828. break;
  1829. case ATA_CMD_FPDMA_READ:
  1830. case ATA_CMD_FPDMA_WRITE:
  1831. mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
  1832. mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
  1833. break;
  1834. default:
  1835. /* The only other commands EDMA supports in non-queued and
  1836. * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
  1837. * of which are defined/used by Linux. If we get here, this
  1838. * driver needs work.
  1839. */
  1840. ata_port_err(ap, "%s: unsupported command: %.2x\n", __func__,
  1841. tf->command);
  1842. return AC_ERR_INVALID;
  1843. }
  1844. mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
  1845. mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
  1846. mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
  1847. mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
  1848. mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
  1849. mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
  1850. mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
  1851. mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
  1852. mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
  1853. if (!(qc->flags & ATA_QCFLAG_DMAMAP))
  1854. return AC_ERR_OK;
  1855. mv_fill_sg(qc);
  1856. return AC_ERR_OK;
  1857. }
  1858. /**
  1859. * mv_qc_prep_iie - Host specific command preparation.
  1860. * @qc: queued command to prepare
  1861. *
  1862. * This routine simply redirects to the general purpose routine
  1863. * if command is not DMA. Else, it handles prep of the CRQB
  1864. * (command request block), does some sanity checking, and calls
  1865. * the SG load routine.
  1866. *
  1867. * LOCKING:
  1868. * Inherited from caller.
  1869. */
  1870. static enum ata_completion_errors mv_qc_prep_iie(struct ata_queued_cmd *qc)
  1871. {
  1872. struct ata_port *ap = qc->ap;
  1873. struct mv_port_priv *pp = ap->private_data;
  1874. struct mv_crqb_iie *crqb;
  1875. struct ata_taskfile *tf = &qc->tf;
  1876. unsigned in_index;
  1877. u32 flags = 0;
  1878. if ((tf->protocol != ATA_PROT_DMA) &&
  1879. (tf->protocol != ATA_PROT_NCQ))
  1880. return AC_ERR_OK;
  1881. if (tf->command == ATA_CMD_DSM)
  1882. return AC_ERR_OK; /* use bmdma for this */
  1883. /* Fill in Gen IIE command request block */
  1884. if (!(tf->flags & ATA_TFLAG_WRITE))
  1885. flags |= CRQB_FLAG_READ;
  1886. WARN_ON(MV_MAX_Q_DEPTH <= qc->hw_tag);
  1887. flags |= qc->hw_tag << CRQB_TAG_SHIFT;
  1888. flags |= qc->hw_tag << CRQB_HOSTQ_SHIFT;
  1889. flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
  1890. /* get current queue index from software */
  1891. in_index = pp->req_idx;
  1892. crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
  1893. crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->hw_tag] & 0xffffffff);
  1894. crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->hw_tag] >> 16) >> 16);
  1895. crqb->flags = cpu_to_le32(flags);
  1896. crqb->ata_cmd[0] = cpu_to_le32(
  1897. (tf->command << 16) |
  1898. (tf->feature << 24)
  1899. );
  1900. crqb->ata_cmd[1] = cpu_to_le32(
  1901. (tf->lbal << 0) |
  1902. (tf->lbam << 8) |
  1903. (tf->lbah << 16) |
  1904. (tf->device << 24)
  1905. );
  1906. crqb->ata_cmd[2] = cpu_to_le32(
  1907. (tf->hob_lbal << 0) |
  1908. (tf->hob_lbam << 8) |
  1909. (tf->hob_lbah << 16) |
  1910. (tf->hob_feature << 24)
  1911. );
  1912. crqb->ata_cmd[3] = cpu_to_le32(
  1913. (tf->nsect << 0) |
  1914. (tf->hob_nsect << 8)
  1915. );
  1916. if (!(qc->flags & ATA_QCFLAG_DMAMAP))
  1917. return AC_ERR_OK;
  1918. mv_fill_sg(qc);
  1919. return AC_ERR_OK;
  1920. }
  1921. /**
  1922. * mv_sff_check_status - fetch device status, if valid
  1923. * @ap: ATA port to fetch status from
  1924. *
  1925. * When using command issue via mv_qc_issue_fis(),
  1926. * the initial ATA_BUSY state does not show up in the
  1927. * ATA status (shadow) register. This can confuse libata!
  1928. *
  1929. * So we have a hook here to fake ATA_BUSY for that situation,
  1930. * until the first time a BUSY, DRQ, or ERR bit is seen.
  1931. *
  1932. * The rest of the time, it simply returns the ATA status register.
  1933. */
  1934. static u8 mv_sff_check_status(struct ata_port *ap)
  1935. {
  1936. u8 stat = ioread8(ap->ioaddr.status_addr);
  1937. struct mv_port_priv *pp = ap->private_data;
  1938. if (pp->pp_flags & MV_PP_FLAG_FAKE_ATA_BUSY) {
  1939. if (stat & (ATA_BUSY | ATA_DRQ | ATA_ERR))
  1940. pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY;
  1941. else
  1942. stat = ATA_BUSY;
  1943. }
  1944. return stat;
  1945. }
  1946. /**
  1947. * mv_send_fis - Send a FIS, using the "Vendor-Unique FIS" register
  1948. * @fis: fis to be sent
  1949. * @nwords: number of 32-bit words in the fis
  1950. */
  1951. static unsigned int mv_send_fis(struct ata_port *ap, u32 *fis, int nwords)
  1952. {
  1953. void __iomem *port_mmio = mv_ap_base(ap);
  1954. u32 ifctl, old_ifctl, ifstat;
  1955. int i, timeout = 200, final_word = nwords - 1;
  1956. /* Initiate FIS transmission mode */
  1957. old_ifctl = readl(port_mmio + SATA_IFCTL);
  1958. ifctl = 0x100 | (old_ifctl & 0xf);
  1959. writelfl(ifctl, port_mmio + SATA_IFCTL);
  1960. /* Send all words of the FIS except for the final word */
  1961. for (i = 0; i < final_word; ++i)
  1962. writel(fis[i], port_mmio + VENDOR_UNIQUE_FIS);
  1963. /* Flag end-of-transmission, and then send the final word */
  1964. writelfl(ifctl | 0x200, port_mmio + SATA_IFCTL);
  1965. writelfl(fis[final_word], port_mmio + VENDOR_UNIQUE_FIS);
  1966. /*
  1967. * Wait for FIS transmission to complete.
  1968. * This typically takes just a single iteration.
  1969. */
  1970. do {
  1971. ifstat = readl(port_mmio + SATA_IFSTAT);
  1972. } while (!(ifstat & 0x1000) && --timeout);
  1973. /* Restore original port configuration */
  1974. writelfl(old_ifctl, port_mmio + SATA_IFCTL);
  1975. /* See if it worked */
  1976. if ((ifstat & 0x3000) != 0x1000) {
  1977. ata_port_warn(ap, "%s transmission error, ifstat=%08x\n",
  1978. __func__, ifstat);
  1979. return AC_ERR_OTHER;
  1980. }
  1981. return 0;
  1982. }
  1983. /**
  1984. * mv_qc_issue_fis - Issue a command directly as a FIS
  1985. * @qc: queued command to start
  1986. *
  1987. * Note that the ATA shadow registers are not updated
  1988. * after command issue, so the device will appear "READY"
  1989. * if polled, even while it is BUSY processing the command.
  1990. *
  1991. * So we use a status hook to fake ATA_BUSY until the drive changes state.
  1992. *
  1993. * Note: we don't get updated shadow regs on *completion*
  1994. * of non-data commands. So avoid sending them via this function,
  1995. * as they will appear to have completed immediately.
  1996. *
  1997. * GEN_IIE has special registers that we could get the result tf from,
  1998. * but earlier chipsets do not. For now, we ignore those registers.
  1999. */
  2000. static unsigned int mv_qc_issue_fis(struct ata_queued_cmd *qc)
  2001. {
  2002. struct ata_port *ap = qc->ap;
  2003. struct mv_port_priv *pp = ap->private_data;
  2004. struct ata_link *link = qc->dev->link;
  2005. u32 fis[5];
  2006. int err = 0;
  2007. ata_tf_to_fis(&qc->tf, link->pmp, 1, (void *)fis);
  2008. err = mv_send_fis(ap, fis, ARRAY_SIZE(fis));
  2009. if (err)
  2010. return err;
  2011. switch (qc->tf.protocol) {
  2012. case ATAPI_PROT_PIO:
  2013. pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY;
  2014. fallthrough;
  2015. case ATAPI_PROT_NODATA:
  2016. ap->hsm_task_state = HSM_ST_FIRST;
  2017. break;
  2018. case ATA_PROT_PIO:
  2019. pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY;
  2020. if (qc->tf.flags & ATA_TFLAG_WRITE)
  2021. ap->hsm_task_state = HSM_ST_FIRST;
  2022. else
  2023. ap->hsm_task_state = HSM_ST;
  2024. break;
  2025. default:
  2026. ap->hsm_task_state = HSM_ST_LAST;
  2027. break;
  2028. }
  2029. if (qc->tf.flags & ATA_TFLAG_POLLING)
  2030. ata_sff_queue_pio_task(link, 0);
  2031. return 0;
  2032. }
  2033. /**
  2034. * mv_qc_issue - Initiate a command to the host
  2035. * @qc: queued command to start
  2036. *
  2037. * This routine simply redirects to the general purpose routine
  2038. * if command is not DMA. Else, it sanity checks our local
  2039. * caches of the request producer/consumer indices then enables
  2040. * DMA and bumps the request producer index.
  2041. *
  2042. * LOCKING:
  2043. * Inherited from caller.
  2044. */
  2045. static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
  2046. {
  2047. static int limit_warnings = 10;
  2048. struct ata_port *ap = qc->ap;
  2049. void __iomem *port_mmio = mv_ap_base(ap);
  2050. struct mv_port_priv *pp = ap->private_data;
  2051. u32 in_index;
  2052. unsigned int port_irqs;
  2053. pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; /* paranoia */
  2054. switch (qc->tf.protocol) {
  2055. case ATA_PROT_DMA:
  2056. if (qc->tf.command == ATA_CMD_DSM) {
  2057. if (!ap->ops->bmdma_setup) /* no bmdma on GEN_I */
  2058. return AC_ERR_OTHER;
  2059. break; /* use bmdma for this */
  2060. }
  2061. fallthrough;
  2062. case ATA_PROT_NCQ:
  2063. mv_start_edma(ap, port_mmio, pp, qc->tf.protocol);
  2064. pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;
  2065. in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
  2066. /* Write the request in pointer to kick the EDMA to life */
  2067. writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index,
  2068. port_mmio + EDMA_REQ_Q_IN_PTR);
  2069. return 0;
  2070. case ATA_PROT_PIO:
  2071. /*
  2072. * Errata SATA#16, SATA#24: warn if multiple DRQs expected.
  2073. *
  2074. * Someday, we might implement special polling workarounds
  2075. * for these, but it all seems rather unnecessary since we
  2076. * normally use only DMA for commands which transfer more
  2077. * than a single block of data.
  2078. *
  2079. * Much of the time, this could just work regardless.
  2080. * So for now, just log the incident, and allow the attempt.
  2081. */
  2082. if (limit_warnings > 0 && (qc->nbytes / qc->sect_size) > 1) {
  2083. --limit_warnings;
  2084. ata_link_warn(qc->dev->link, DRV_NAME
  2085. ": attempting PIO w/multiple DRQ: "
  2086. "this may fail due to h/w errata\n");
  2087. }
  2088. fallthrough;
  2089. case ATA_PROT_NODATA:
  2090. case ATAPI_PROT_PIO:
  2091. case ATAPI_PROT_NODATA:
  2092. if (ap->flags & ATA_FLAG_PIO_POLLING)
  2093. qc->tf.flags |= ATA_TFLAG_POLLING;
  2094. break;
  2095. }
  2096. if (qc->tf.flags & ATA_TFLAG_POLLING)
  2097. port_irqs = ERR_IRQ; /* mask device interrupt when polling */
  2098. else
  2099. port_irqs = ERR_IRQ | DONE_IRQ; /* unmask all interrupts */
  2100. /*
  2101. * We're about to send a non-EDMA capable command to the
  2102. * port. Turn off EDMA so there won't be problems accessing
  2103. * shadow block, etc registers.
  2104. */
  2105. mv_stop_edma(ap);
  2106. mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), port_irqs);
  2107. mv_pmp_select(ap, qc->dev->link->pmp);
  2108. if (qc->tf.command == ATA_CMD_READ_LOG_EXT) {
  2109. struct mv_host_priv *hpriv = ap->host->private_data;
  2110. /*
  2111. * Workaround for 88SX60x1 FEr SATA#25 (part 2).
  2112. *
  2113. * After any NCQ error, the READ_LOG_EXT command
  2114. * from libata-eh *must* use mv_qc_issue_fis().
  2115. * Otherwise it might fail, due to chip errata.
  2116. *
  2117. * Rather than special-case it, we'll just *always*
  2118. * use this method here for READ_LOG_EXT, making for
  2119. * easier testing.
  2120. */
  2121. if (IS_GEN_II(hpriv))
  2122. return mv_qc_issue_fis(qc);
  2123. }
  2124. return ata_bmdma_qc_issue(qc);
  2125. }
  2126. static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap)
  2127. {
  2128. struct mv_port_priv *pp = ap->private_data;
  2129. struct ata_queued_cmd *qc;
  2130. if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
  2131. return NULL;
  2132. qc = ata_qc_from_tag(ap, ap->link.active_tag);
  2133. if (qc && !(qc->tf.flags & ATA_TFLAG_POLLING))
  2134. return qc;
  2135. return NULL;
  2136. }
  2137. static void mv_pmp_error_handler(struct ata_port *ap)
  2138. {
  2139. unsigned int pmp, pmp_map;
  2140. struct mv_port_priv *pp = ap->private_data;
  2141. if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) {
  2142. /*
  2143. * Perform NCQ error analysis on failed PMPs
  2144. * before we freeze the port entirely.
  2145. *
  2146. * The failed PMPs are marked earlier by mv_pmp_eh_prep().
  2147. */
  2148. pmp_map = pp->delayed_eh_pmp_map;
  2149. pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH;
  2150. for (pmp = 0; pmp_map != 0; pmp++) {
  2151. unsigned int this_pmp = (1 << pmp);
  2152. if (pmp_map & this_pmp) {
  2153. struct ata_link *link = &ap->pmp_link[pmp];
  2154. pmp_map &= ~this_pmp;
  2155. ata_eh_analyze_ncq_error(link);
  2156. }
  2157. }
  2158. ata_port_freeze(ap);
  2159. }
  2160. sata_pmp_error_handler(ap);
  2161. }
  2162. static unsigned int mv_get_err_pmp_map(struct ata_port *ap)
  2163. {
  2164. void __iomem *port_mmio = mv_ap_base(ap);
  2165. return readl(port_mmio + SATA_TESTCTL) >> 16;
  2166. }
  2167. static void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map)
  2168. {
  2169. unsigned int pmp;
  2170. /*
  2171. * Initialize EH info for PMPs which saw device errors
  2172. */
  2173. for (pmp = 0; pmp_map != 0; pmp++) {
  2174. unsigned int this_pmp = (1 << pmp);
  2175. if (pmp_map & this_pmp) {
  2176. struct ata_link *link = &ap->pmp_link[pmp];
  2177. struct ata_eh_info *ehi = &link->eh_info;
  2178. pmp_map &= ~this_pmp;
  2179. ata_ehi_clear_desc(ehi);
  2180. ata_ehi_push_desc(ehi, "dev err");
  2181. ehi->err_mask |= AC_ERR_DEV;
  2182. ehi->action |= ATA_EH_RESET;
  2183. ata_link_abort(link);
  2184. }
  2185. }
  2186. }
  2187. static int mv_req_q_empty(struct ata_port *ap)
  2188. {
  2189. void __iomem *port_mmio = mv_ap_base(ap);
  2190. u32 in_ptr, out_ptr;
  2191. in_ptr = (readl(port_mmio + EDMA_REQ_Q_IN_PTR)
  2192. >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
  2193. out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR)
  2194. >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
  2195. return (in_ptr == out_ptr); /* 1 == queue_is_empty */
  2196. }
  2197. static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap)
  2198. {
  2199. struct mv_port_priv *pp = ap->private_data;
  2200. int failed_links;
  2201. unsigned int old_map, new_map;
  2202. /*
  2203. * Device error during FBS+NCQ operation:
  2204. *
  2205. * Set a port flag to prevent further I/O being enqueued.
  2206. * Leave the EDMA running to drain outstanding commands from this port.
  2207. * Perform the post-mortem/EH only when all responses are complete.
  2208. * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2).
  2209. */
  2210. if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) {
  2211. pp->pp_flags |= MV_PP_FLAG_DELAYED_EH;
  2212. pp->delayed_eh_pmp_map = 0;
  2213. }
  2214. old_map = pp->delayed_eh_pmp_map;
  2215. new_map = old_map | mv_get_err_pmp_map(ap);
  2216. if (old_map != new_map) {
  2217. pp->delayed_eh_pmp_map = new_map;
  2218. mv_pmp_eh_prep(ap, new_map & ~old_map);
  2219. }
  2220. failed_links = hweight16(new_map);
  2221. ata_port_info(ap,
  2222. "%s: pmp_map=%04x qc_map=%04llx failed_links=%d nr_active_links=%d\n",
  2223. __func__, pp->delayed_eh_pmp_map,
  2224. ap->qc_active, failed_links,
  2225. ap->nr_active_links);
  2226. if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) {
  2227. mv_process_crpb_entries(ap, pp);
  2228. mv_stop_edma(ap);
  2229. mv_eh_freeze(ap);
  2230. ata_port_info(ap, "%s: done\n", __func__);
  2231. return 1; /* handled */
  2232. }
  2233. ata_port_info(ap, "%s: waiting\n", __func__);
  2234. return 1; /* handled */
  2235. }
  2236. static int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap)
  2237. {
  2238. /*
  2239. * Possible future enhancement:
  2240. *
  2241. * FBS+non-NCQ operation is not yet implemented.
  2242. * See related notes in mv_edma_cfg().
  2243. *
  2244. * Device error during FBS+non-NCQ operation:
  2245. *
  2246. * We need to snapshot the shadow registers for each failed command.
  2247. * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3).
  2248. */
  2249. return 0; /* not handled */
  2250. }
  2251. static int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause)
  2252. {
  2253. struct mv_port_priv *pp = ap->private_data;
  2254. if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
  2255. return 0; /* EDMA was not active: not handled */
  2256. if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN))
  2257. return 0; /* FBS was not active: not handled */
  2258. if (!(edma_err_cause & EDMA_ERR_DEV))
  2259. return 0; /* non DEV error: not handled */
  2260. edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT;
  2261. if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS))
  2262. return 0; /* other problems: not handled */
  2263. if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
  2264. /*
  2265. * EDMA should NOT have self-disabled for this case.
  2266. * If it did, then something is wrong elsewhere,
  2267. * and we cannot handle it here.
  2268. */
  2269. if (edma_err_cause & EDMA_ERR_SELF_DIS) {
  2270. ata_port_warn(ap, "%s: err_cause=0x%x pp_flags=0x%x\n",
  2271. __func__, edma_err_cause, pp->pp_flags);
  2272. return 0; /* not handled */
  2273. }
  2274. return mv_handle_fbs_ncq_dev_err(ap);
  2275. } else {
  2276. /*
  2277. * EDMA should have self-disabled for this case.
  2278. * If it did not, then something is wrong elsewhere,
  2279. * and we cannot handle it here.
  2280. */
  2281. if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) {
  2282. ata_port_warn(ap, "%s: err_cause=0x%x pp_flags=0x%x\n",
  2283. __func__, edma_err_cause, pp->pp_flags);
  2284. return 0; /* not handled */
  2285. }
  2286. return mv_handle_fbs_non_ncq_dev_err(ap);
  2287. }
  2288. return 0; /* not handled */
  2289. }
  2290. static void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled)
  2291. {
  2292. struct ata_eh_info *ehi = &ap->link.eh_info;
  2293. char *when = "idle";
  2294. ata_ehi_clear_desc(ehi);
  2295. if (edma_was_enabled) {
  2296. when = "EDMA enabled";
  2297. } else {
  2298. struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
  2299. if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
  2300. when = "polling";
  2301. }
  2302. ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when);
  2303. ehi->err_mask |= AC_ERR_OTHER;
  2304. ehi->action |= ATA_EH_RESET;
  2305. ata_port_freeze(ap);
  2306. }
  2307. /**
  2308. * mv_err_intr - Handle error interrupts on the port
  2309. * @ap: ATA channel to manipulate
  2310. *
  2311. * Most cases require a full reset of the chip's state machine,
  2312. * which also performs a COMRESET.
  2313. * Also, if the port disabled DMA, update our cached copy to match.
  2314. *
  2315. * LOCKING:
  2316. * Inherited from caller.
  2317. */
  2318. static void mv_err_intr(struct ata_port *ap)
  2319. {
  2320. void __iomem *port_mmio = mv_ap_base(ap);
  2321. u32 edma_err_cause, eh_freeze_mask, serr = 0;
  2322. u32 fis_cause = 0;
  2323. struct mv_port_priv *pp = ap->private_data;
  2324. struct mv_host_priv *hpriv = ap->host->private_data;
  2325. unsigned int action = 0, err_mask = 0;
  2326. struct ata_eh_info *ehi = &ap->link.eh_info;
  2327. struct ata_queued_cmd *qc;
  2328. int abort = 0;
  2329. /*
  2330. * Read and clear the SError and err_cause bits.
  2331. * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear
  2332. * the FIS_IRQ_CAUSE register before clearing edma_err_cause.
  2333. */
  2334. sata_scr_read(&ap->link, SCR_ERROR, &serr);
  2335. sata_scr_write_flush(&ap->link, SCR_ERROR, serr);
  2336. edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE);
  2337. if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
  2338. fis_cause = readl(port_mmio + FIS_IRQ_CAUSE);
  2339. writelfl(~fis_cause, port_mmio + FIS_IRQ_CAUSE);
  2340. }
  2341. writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE);
  2342. if (edma_err_cause & EDMA_ERR_DEV) {
  2343. /*
  2344. * Device errors during FIS-based switching operation
  2345. * require special handling.
  2346. */
  2347. if (mv_handle_dev_err(ap, edma_err_cause))
  2348. return;
  2349. }
  2350. qc = mv_get_active_qc(ap);
  2351. ata_ehi_clear_desc(ehi);
  2352. ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x",
  2353. edma_err_cause, pp->pp_flags);
  2354. if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
  2355. ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause);
  2356. if (fis_cause & FIS_IRQ_CAUSE_AN) {
  2357. u32 ec = edma_err_cause &
  2358. ~(EDMA_ERR_TRANS_IRQ_7 | EDMA_ERR_IRQ_TRANSIENT);
  2359. sata_async_notification(ap);
  2360. if (!ec)
  2361. return; /* Just an AN; no need for the nukes */
  2362. ata_ehi_push_desc(ehi, "SDB notify");
  2363. }
  2364. }
  2365. /*
  2366. * All generations share these EDMA error cause bits:
  2367. */
  2368. if (edma_err_cause & EDMA_ERR_DEV) {
  2369. err_mask |= AC_ERR_DEV;
  2370. action |= ATA_EH_RESET;
  2371. ata_ehi_push_desc(ehi, "dev error");
  2372. }
  2373. if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
  2374. EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR |
  2375. EDMA_ERR_INTRL_PAR)) {
  2376. err_mask |= AC_ERR_ATA_BUS;
  2377. action |= ATA_EH_RESET;
  2378. ata_ehi_push_desc(ehi, "parity error");
  2379. }
  2380. if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) {
  2381. ata_ehi_hotplugged(ehi);
  2382. ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ?
  2383. "dev disconnect" : "dev connect");
  2384. action |= ATA_EH_RESET;
  2385. }
  2386. /*
  2387. * Gen-I has a different SELF_DIS bit,
  2388. * different FREEZE bits, and no SERR bit:
  2389. */
  2390. if (IS_GEN_I(hpriv)) {
  2391. eh_freeze_mask = EDMA_EH_FREEZE_5;
  2392. if (edma_err_cause & EDMA_ERR_SELF_DIS_5) {
  2393. pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
  2394. ata_ehi_push_desc(ehi, "EDMA self-disable");
  2395. }
  2396. } else {
  2397. eh_freeze_mask = EDMA_EH_FREEZE;
  2398. if (edma_err_cause & EDMA_ERR_SELF_DIS) {
  2399. pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
  2400. ata_ehi_push_desc(ehi, "EDMA self-disable");
  2401. }
  2402. if (edma_err_cause & EDMA_ERR_SERR) {
  2403. ata_ehi_push_desc(ehi, "SError=%08x", serr);
  2404. err_mask |= AC_ERR_ATA_BUS;
  2405. action |= ATA_EH_RESET;
  2406. }
  2407. }
  2408. if (!err_mask) {
  2409. err_mask = AC_ERR_OTHER;
  2410. action |= ATA_EH_RESET;
  2411. }
  2412. ehi->serror |= serr;
  2413. ehi->action |= action;
  2414. if (qc)
  2415. qc->err_mask |= err_mask;
  2416. else
  2417. ehi->err_mask |= err_mask;
  2418. if (err_mask == AC_ERR_DEV) {
  2419. /*
  2420. * Cannot do ata_port_freeze() here,
  2421. * because it would kill PIO access,
  2422. * which is needed for further diagnosis.
  2423. */
  2424. mv_eh_freeze(ap);
  2425. abort = 1;
  2426. } else if (edma_err_cause & eh_freeze_mask) {
  2427. /*
  2428. * Note to self: ata_port_freeze() calls ata_port_abort()
  2429. */
  2430. ata_port_freeze(ap);
  2431. } else {
  2432. abort = 1;
  2433. }
  2434. if (abort) {
  2435. if (qc)
  2436. ata_link_abort(qc->dev->link);
  2437. else
  2438. ata_port_abort(ap);
  2439. }
  2440. }
  2441. static bool mv_process_crpb_response(struct ata_port *ap,
  2442. struct mv_crpb *response, unsigned int tag, int ncq_enabled)
  2443. {
  2444. u8 ata_status;
  2445. u16 edma_status = le16_to_cpu(response->flags);
  2446. /*
  2447. * edma_status from a response queue entry:
  2448. * LSB is from EDMA_ERR_IRQ_CAUSE (non-NCQ only).
  2449. * MSB is saved ATA status from command completion.
  2450. */
  2451. if (!ncq_enabled) {
  2452. u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
  2453. if (err_cause) {
  2454. /*
  2455. * Error will be seen/handled by
  2456. * mv_err_intr(). So do nothing at all here.
  2457. */
  2458. return false;
  2459. }
  2460. }
  2461. ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
  2462. if (!ac_err_mask(ata_status))
  2463. return true;
  2464. /* else: leave it for mv_err_intr() */
  2465. return false;
  2466. }
  2467. static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp)
  2468. {
  2469. void __iomem *port_mmio = mv_ap_base(ap);
  2470. struct mv_host_priv *hpriv = ap->host->private_data;
  2471. u32 in_index;
  2472. bool work_done = false;
  2473. u32 done_mask = 0;
  2474. int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN);
  2475. /* Get the hardware queue position index */
  2476. in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR)
  2477. >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
  2478. /* Process new responses from since the last time we looked */
  2479. while (in_index != pp->resp_idx) {
  2480. unsigned int tag;
  2481. struct mv_crpb *response = &pp->crpb[pp->resp_idx];
  2482. pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK;
  2483. if (IS_GEN_I(hpriv)) {
  2484. /* 50xx: no NCQ, only one command active at a time */
  2485. tag = ap->link.active_tag;
  2486. } else {
  2487. /* Gen II/IIE: get command tag from CRPB entry */
  2488. tag = le16_to_cpu(response->id) & 0x1f;
  2489. }
  2490. if (mv_process_crpb_response(ap, response, tag, ncq_enabled))
  2491. done_mask |= 1 << tag;
  2492. work_done = true;
  2493. }
  2494. if (work_done) {
  2495. ata_qc_complete_multiple(ap, ata_qc_get_active(ap) ^ done_mask);
  2496. /* Update the software queue position index in hardware */
  2497. writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) |
  2498. (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT),
  2499. port_mmio + EDMA_RSP_Q_OUT_PTR);
  2500. }
  2501. }
  2502. static void mv_port_intr(struct ata_port *ap, u32 port_cause)
  2503. {
  2504. struct mv_port_priv *pp;
  2505. int edma_was_enabled;
  2506. /*
  2507. * Grab a snapshot of the EDMA_EN flag setting,
  2508. * so that we have a consistent view for this port,
  2509. * even if something we call of our routines changes it.
  2510. */
  2511. pp = ap->private_data;
  2512. edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN);
  2513. /*
  2514. * Process completed CRPB response(s) before other events.
  2515. */
  2516. if (edma_was_enabled && (port_cause & DONE_IRQ)) {
  2517. mv_process_crpb_entries(ap, pp);
  2518. if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
  2519. mv_handle_fbs_ncq_dev_err(ap);
  2520. }
  2521. /*
  2522. * Handle chip-reported errors, or continue on to handle PIO.
  2523. */
  2524. if (unlikely(port_cause & ERR_IRQ)) {
  2525. mv_err_intr(ap);
  2526. } else if (!edma_was_enabled) {
  2527. struct ata_queued_cmd *qc = mv_get_active_qc(ap);
  2528. if (qc)
  2529. ata_bmdma_port_intr(ap, qc);
  2530. else
  2531. mv_unexpected_intr(ap, edma_was_enabled);
  2532. }
  2533. }
  2534. /**
  2535. * mv_host_intr - Handle all interrupts on the given host controller
  2536. * @host: host specific structure
  2537. * @main_irq_cause: Main interrupt cause register for the chip.
  2538. *
  2539. * LOCKING:
  2540. * Inherited from caller.
  2541. */
  2542. static int mv_host_intr(struct ata_host *host, u32 main_irq_cause)
  2543. {
  2544. struct mv_host_priv *hpriv = host->private_data;
  2545. void __iomem *mmio = hpriv->base, *hc_mmio;
  2546. unsigned int handled = 0, port;
  2547. /* If asserted, clear the "all ports" IRQ coalescing bit */
  2548. if (main_irq_cause & ALL_PORTS_COAL_DONE)
  2549. writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE);
  2550. for (port = 0; port < hpriv->n_ports; port++) {
  2551. struct ata_port *ap = host->ports[port];
  2552. unsigned int p, shift, hardport, port_cause;
  2553. MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
  2554. /*
  2555. * Each hc within the host has its own hc_irq_cause register,
  2556. * where the interrupting ports bits get ack'd.
  2557. */
  2558. if (hardport == 0) { /* first port on this hc ? */
  2559. u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND;
  2560. u32 port_mask, ack_irqs;
  2561. /*
  2562. * Skip this entire hc if nothing pending for any ports
  2563. */
  2564. if (!hc_cause) {
  2565. port += MV_PORTS_PER_HC - 1;
  2566. continue;
  2567. }
  2568. /*
  2569. * We don't need/want to read the hc_irq_cause register,
  2570. * because doing so hurts performance, and
  2571. * main_irq_cause already gives us everything we need.
  2572. *
  2573. * But we do have to *write* to the hc_irq_cause to ack
  2574. * the ports that we are handling this time through.
  2575. *
  2576. * This requires that we create a bitmap for those
  2577. * ports which interrupted us, and use that bitmap
  2578. * to ack (only) those ports via hc_irq_cause.
  2579. */
  2580. ack_irqs = 0;
  2581. if (hc_cause & PORTS_0_3_COAL_DONE)
  2582. ack_irqs = HC_COAL_IRQ;
  2583. for (p = 0; p < MV_PORTS_PER_HC; ++p) {
  2584. if ((port + p) >= hpriv->n_ports)
  2585. break;
  2586. port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2);
  2587. if (hc_cause & port_mask)
  2588. ack_irqs |= (DMA_IRQ | DEV_IRQ) << p;
  2589. }
  2590. hc_mmio = mv_hc_base_from_port(mmio, port);
  2591. writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE);
  2592. handled = 1;
  2593. }
  2594. /*
  2595. * Handle interrupts signalled for this port:
  2596. */
  2597. port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ);
  2598. if (port_cause)
  2599. mv_port_intr(ap, port_cause);
  2600. }
  2601. return handled;
  2602. }
  2603. static int mv_pci_error(struct ata_host *host, void __iomem *mmio)
  2604. {
  2605. struct mv_host_priv *hpriv = host->private_data;
  2606. struct ata_port *ap;
  2607. struct ata_queued_cmd *qc;
  2608. struct ata_eh_info *ehi;
  2609. unsigned int i, err_mask, printed = 0;
  2610. u32 err_cause;
  2611. err_cause = readl(mmio + hpriv->irq_cause_offset);
  2612. dev_err(host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n", err_cause);
  2613. DPRINTK("All regs @ PCI error\n");
  2614. mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
  2615. writelfl(0, mmio + hpriv->irq_cause_offset);
  2616. for (i = 0; i < host->n_ports; i++) {
  2617. ap = host->ports[i];
  2618. if (!ata_link_offline(&ap->link)) {
  2619. ehi = &ap->link.eh_info;
  2620. ata_ehi_clear_desc(ehi);
  2621. if (!printed++)
  2622. ata_ehi_push_desc(ehi,
  2623. "PCI err cause 0x%08x", err_cause);
  2624. err_mask = AC_ERR_HOST_BUS;
  2625. ehi->action = ATA_EH_RESET;
  2626. qc = ata_qc_from_tag(ap, ap->link.active_tag);
  2627. if (qc)
  2628. qc->err_mask |= err_mask;
  2629. else
  2630. ehi->err_mask |= err_mask;
  2631. ata_port_freeze(ap);
  2632. }
  2633. }
  2634. return 1; /* handled */
  2635. }
  2636. /**
  2637. * mv_interrupt - Main interrupt event handler
  2638. * @irq: unused
  2639. * @dev_instance: private data; in this case the host structure
  2640. *
  2641. * Read the read only register to determine if any host
  2642. * controllers have pending interrupts. If so, call lower level
  2643. * routine to handle. Also check for PCI errors which are only
  2644. * reported here.
  2645. *
  2646. * LOCKING:
  2647. * This routine holds the host lock while processing pending
  2648. * interrupts.
  2649. */
  2650. static irqreturn_t mv_interrupt(int irq, void *dev_instance)
  2651. {
  2652. struct ata_host *host = dev_instance;
  2653. struct mv_host_priv *hpriv = host->private_data;
  2654. unsigned int handled = 0;
  2655. int using_msi = hpriv->hp_flags & MV_HP_FLAG_MSI;
  2656. u32 main_irq_cause, pending_irqs;
  2657. spin_lock(&host->lock);
  2658. /* for MSI: block new interrupts while in here */
  2659. if (using_msi)
  2660. mv_write_main_irq_mask(0, hpriv);
  2661. main_irq_cause = readl(hpriv->main_irq_cause_addr);
  2662. pending_irqs = main_irq_cause & hpriv->main_irq_mask;
  2663. /*
  2664. * Deal with cases where we either have nothing pending, or have read
  2665. * a bogus register value which can indicate HW removal or PCI fault.
  2666. */
  2667. if (pending_irqs && main_irq_cause != 0xffffffffU) {
  2668. if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv)))
  2669. handled = mv_pci_error(host, hpriv->base);
  2670. else
  2671. handled = mv_host_intr(host, pending_irqs);
  2672. }
  2673. /* for MSI: unmask; interrupt cause bits will retrigger now */
  2674. if (using_msi)
  2675. mv_write_main_irq_mask(hpriv->main_irq_mask, hpriv);
  2676. spin_unlock(&host->lock);
  2677. return IRQ_RETVAL(handled);
  2678. }
  2679. static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
  2680. {
  2681. unsigned int ofs;
  2682. switch (sc_reg_in) {
  2683. case SCR_STATUS:
  2684. case SCR_ERROR:
  2685. case SCR_CONTROL:
  2686. ofs = sc_reg_in * sizeof(u32);
  2687. break;
  2688. default:
  2689. ofs = 0xffffffffU;
  2690. break;
  2691. }
  2692. return ofs;
  2693. }
  2694. static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
  2695. {
  2696. struct mv_host_priv *hpriv = link->ap->host->private_data;
  2697. void __iomem *mmio = hpriv->base;
  2698. void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
  2699. unsigned int ofs = mv5_scr_offset(sc_reg_in);
  2700. if (ofs != 0xffffffffU) {
  2701. *val = readl(addr + ofs);
  2702. return 0;
  2703. } else
  2704. return -EINVAL;
  2705. }
  2706. static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
  2707. {
  2708. struct mv_host_priv *hpriv = link->ap->host->private_data;
  2709. void __iomem *mmio = hpriv->base;
  2710. void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
  2711. unsigned int ofs = mv5_scr_offset(sc_reg_in);
  2712. if (ofs != 0xffffffffU) {
  2713. writelfl(val, addr + ofs);
  2714. return 0;
  2715. } else
  2716. return -EINVAL;
  2717. }
  2718. static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio)
  2719. {
  2720. struct pci_dev *pdev = to_pci_dev(host->dev);
  2721. int early_5080;
  2722. early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0);
  2723. if (!early_5080) {
  2724. u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
  2725. tmp |= (1 << 0);
  2726. writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
  2727. }
  2728. mv_reset_pci_bus(host, mmio);
  2729. }
  2730. static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
  2731. {
  2732. writel(0x0fcfffff, mmio + FLASH_CTL);
  2733. }
  2734. static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
  2735. void __iomem *mmio)
  2736. {
  2737. void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
  2738. u32 tmp;
  2739. tmp = readl(phy_mmio + MV5_PHY_MODE);
  2740. hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
  2741. hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
  2742. }
  2743. static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
  2744. {
  2745. u32 tmp;
  2746. writel(0, mmio + GPIO_PORT_CTL);
  2747. /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
  2748. tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
  2749. tmp |= ~(1 << 0);
  2750. writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
  2751. }
  2752. static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
  2753. unsigned int port)
  2754. {
  2755. void __iomem *phy_mmio = mv5_phy_base(mmio, port);
  2756. const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
  2757. u32 tmp;
  2758. int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
  2759. if (fix_apm_sq) {
  2760. tmp = readl(phy_mmio + MV5_LTMODE);
  2761. tmp |= (1 << 19);
  2762. writel(tmp, phy_mmio + MV5_LTMODE);
  2763. tmp = readl(phy_mmio + MV5_PHY_CTL);
  2764. tmp &= ~0x3;
  2765. tmp |= 0x1;
  2766. writel(tmp, phy_mmio + MV5_PHY_CTL);
  2767. }
  2768. tmp = readl(phy_mmio + MV5_PHY_MODE);
  2769. tmp &= ~mask;
  2770. tmp |= hpriv->signal[port].pre;
  2771. tmp |= hpriv->signal[port].amps;
  2772. writel(tmp, phy_mmio + MV5_PHY_MODE);
  2773. }
  2774. #undef ZERO
  2775. #define ZERO(reg) writel(0, port_mmio + (reg))
  2776. static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
  2777. unsigned int port)
  2778. {
  2779. void __iomem *port_mmio = mv_port_base(mmio, port);
  2780. mv_reset_channel(hpriv, mmio, port);
  2781. ZERO(0x028); /* command */
  2782. writel(0x11f, port_mmio + EDMA_CFG);
  2783. ZERO(0x004); /* timer */
  2784. ZERO(0x008); /* irq err cause */
  2785. ZERO(0x00c); /* irq err mask */
  2786. ZERO(0x010); /* rq bah */
  2787. ZERO(0x014); /* rq inp */
  2788. ZERO(0x018); /* rq outp */
  2789. ZERO(0x01c); /* respq bah */
  2790. ZERO(0x024); /* respq outp */
  2791. ZERO(0x020); /* respq inp */
  2792. ZERO(0x02c); /* test control */
  2793. writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
  2794. }
  2795. #undef ZERO
  2796. #define ZERO(reg) writel(0, hc_mmio + (reg))
  2797. static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
  2798. unsigned int hc)
  2799. {
  2800. void __iomem *hc_mmio = mv_hc_base(mmio, hc);
  2801. u32 tmp;
  2802. ZERO(0x00c);
  2803. ZERO(0x010);
  2804. ZERO(0x014);
  2805. ZERO(0x018);
  2806. tmp = readl(hc_mmio + 0x20);
  2807. tmp &= 0x1c1c1c1c;
  2808. tmp |= 0x03030303;
  2809. writel(tmp, hc_mmio + 0x20);
  2810. }
  2811. #undef ZERO
  2812. static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
  2813. unsigned int n_hc)
  2814. {
  2815. unsigned int hc, port;
  2816. for (hc = 0; hc < n_hc; hc++) {
  2817. for (port = 0; port < MV_PORTS_PER_HC; port++)
  2818. mv5_reset_hc_port(hpriv, mmio,
  2819. (hc * MV_PORTS_PER_HC) + port);
  2820. mv5_reset_one_hc(hpriv, mmio, hc);
  2821. }
  2822. return 0;
  2823. }
  2824. #undef ZERO
  2825. #define ZERO(reg) writel(0, mmio + (reg))
  2826. static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio)
  2827. {
  2828. struct mv_host_priv *hpriv = host->private_data;
  2829. u32 tmp;
  2830. tmp = readl(mmio + MV_PCI_MODE);
  2831. tmp &= 0xff00ffff;
  2832. writel(tmp, mmio + MV_PCI_MODE);
  2833. ZERO(MV_PCI_DISC_TIMER);
  2834. ZERO(MV_PCI_MSI_TRIGGER);
  2835. writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT);
  2836. ZERO(MV_PCI_SERR_MASK);
  2837. ZERO(hpriv->irq_cause_offset);
  2838. ZERO(hpriv->irq_mask_offset);
  2839. ZERO(MV_PCI_ERR_LOW_ADDRESS);
  2840. ZERO(MV_PCI_ERR_HIGH_ADDRESS);
  2841. ZERO(MV_PCI_ERR_ATTRIBUTE);
  2842. ZERO(MV_PCI_ERR_COMMAND);
  2843. }
  2844. #undef ZERO
  2845. static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
  2846. {
  2847. u32 tmp;
  2848. mv5_reset_flash(hpriv, mmio);
  2849. tmp = readl(mmio + GPIO_PORT_CTL);
  2850. tmp &= 0x3;
  2851. tmp |= (1 << 5) | (1 << 6);
  2852. writel(tmp, mmio + GPIO_PORT_CTL);
  2853. }
  2854. /**
  2855. * mv6_reset_hc - Perform the 6xxx global soft reset
  2856. * @mmio: base address of the HBA
  2857. *
  2858. * This routine only applies to 6xxx parts.
  2859. *
  2860. * LOCKING:
  2861. * Inherited from caller.
  2862. */
  2863. static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
  2864. unsigned int n_hc)
  2865. {
  2866. void __iomem *reg = mmio + PCI_MAIN_CMD_STS;
  2867. int i, rc = 0;
  2868. u32 t;
  2869. /* Following procedure defined in PCI "main command and status
  2870. * register" table.
  2871. */
  2872. t = readl(reg);
  2873. writel(t | STOP_PCI_MASTER, reg);
  2874. for (i = 0; i < 1000; i++) {
  2875. udelay(1);
  2876. t = readl(reg);
  2877. if (PCI_MASTER_EMPTY & t)
  2878. break;
  2879. }
  2880. if (!(PCI_MASTER_EMPTY & t)) {
  2881. printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
  2882. rc = 1;
  2883. goto done;
  2884. }
  2885. /* set reset */
  2886. i = 5;
  2887. do {
  2888. writel(t | GLOB_SFT_RST, reg);
  2889. t = readl(reg);
  2890. udelay(1);
  2891. } while (!(GLOB_SFT_RST & t) && (i-- > 0));
  2892. if (!(GLOB_SFT_RST & t)) {
  2893. printk(KERN_ERR DRV_NAME ": can't set global reset\n");
  2894. rc = 1;
  2895. goto done;
  2896. }
  2897. /* clear reset and *reenable the PCI master* (not mentioned in spec) */
  2898. i = 5;
  2899. do {
  2900. writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
  2901. t = readl(reg);
  2902. udelay(1);
  2903. } while ((GLOB_SFT_RST & t) && (i-- > 0));
  2904. if (GLOB_SFT_RST & t) {
  2905. printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
  2906. rc = 1;
  2907. }
  2908. done:
  2909. return rc;
  2910. }
  2911. static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
  2912. void __iomem *mmio)
  2913. {
  2914. void __iomem *port_mmio;
  2915. u32 tmp;
  2916. tmp = readl(mmio + RESET_CFG);
  2917. if ((tmp & (1 << 0)) == 0) {
  2918. hpriv->signal[idx].amps = 0x7 << 8;
  2919. hpriv->signal[idx].pre = 0x1 << 5;
  2920. return;
  2921. }
  2922. port_mmio = mv_port_base(mmio, idx);
  2923. tmp = readl(port_mmio + PHY_MODE2);
  2924. hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
  2925. hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
  2926. }
  2927. static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
  2928. {
  2929. writel(0x00000060, mmio + GPIO_PORT_CTL);
  2930. }
  2931. static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
  2932. unsigned int port)
  2933. {
  2934. void __iomem *port_mmio = mv_port_base(mmio, port);
  2935. u32 hp_flags = hpriv->hp_flags;
  2936. int fix_phy_mode2 =
  2937. hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
  2938. int fix_phy_mode4 =
  2939. hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
  2940. u32 m2, m3;
  2941. if (fix_phy_mode2) {
  2942. m2 = readl(port_mmio + PHY_MODE2);
  2943. m2 &= ~(1 << 16);
  2944. m2 |= (1 << 31);
  2945. writel(m2, port_mmio + PHY_MODE2);
  2946. udelay(200);
  2947. m2 = readl(port_mmio + PHY_MODE2);
  2948. m2 &= ~((1 << 16) | (1 << 31));
  2949. writel(m2, port_mmio + PHY_MODE2);
  2950. udelay(200);
  2951. }
  2952. /*
  2953. * Gen-II/IIe PHY_MODE3 errata RM#2:
  2954. * Achieves better receiver noise performance than the h/w default:
  2955. */
  2956. m3 = readl(port_mmio + PHY_MODE3);
  2957. m3 = (m3 & 0x1f) | (0x5555601 << 5);
  2958. /* Guideline 88F5182 (GL# SATA-S11) */
  2959. if (IS_SOC(hpriv))
  2960. m3 &= ~0x1c;
  2961. if (fix_phy_mode4) {
  2962. u32 m4 = readl(port_mmio + PHY_MODE4);
  2963. /*
  2964. * Enforce reserved-bit restrictions on GenIIe devices only.
  2965. * For earlier chipsets, force only the internal config field
  2966. * (workaround for errata FEr SATA#10 part 1).
  2967. */
  2968. if (IS_GEN_IIE(hpriv))
  2969. m4 = (m4 & ~PHY_MODE4_RSVD_ZEROS) | PHY_MODE4_RSVD_ONES;
  2970. else
  2971. m4 = (m4 & ~PHY_MODE4_CFG_MASK) | PHY_MODE4_CFG_VALUE;
  2972. writel(m4, port_mmio + PHY_MODE4);
  2973. }
  2974. /*
  2975. * Workaround for 60x1-B2 errata SATA#13:
  2976. * Any write to PHY_MODE4 (above) may corrupt PHY_MODE3,
  2977. * so we must always rewrite PHY_MODE3 after PHY_MODE4.
  2978. * Or ensure we use writelfl() when writing PHY_MODE4.
  2979. */
  2980. writel(m3, port_mmio + PHY_MODE3);
  2981. /* Revert values of pre-emphasis and signal amps to the saved ones */
  2982. m2 = readl(port_mmio + PHY_MODE2);
  2983. m2 &= ~MV_M2_PREAMP_MASK;
  2984. m2 |= hpriv->signal[port].amps;
  2985. m2 |= hpriv->signal[port].pre;
  2986. m2 &= ~(1 << 16);
  2987. /* according to mvSata 3.6.1, some IIE values are fixed */
  2988. if (IS_GEN_IIE(hpriv)) {
  2989. m2 &= ~0xC30FF01F;
  2990. m2 |= 0x0000900F;
  2991. }
  2992. writel(m2, port_mmio + PHY_MODE2);
  2993. }
  2994. /* TODO: use the generic LED interface to configure the SATA Presence */
  2995. /* & Acitivy LEDs on the board */
  2996. static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
  2997. void __iomem *mmio)
  2998. {
  2999. return;
  3000. }
  3001. static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
  3002. void __iomem *mmio)
  3003. {
  3004. void __iomem *port_mmio;
  3005. u32 tmp;
  3006. port_mmio = mv_port_base(mmio, idx);
  3007. tmp = readl(port_mmio + PHY_MODE2);
  3008. hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
  3009. hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
  3010. }
  3011. #undef ZERO
  3012. #define ZERO(reg) writel(0, port_mmio + (reg))
  3013. static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
  3014. void __iomem *mmio, unsigned int port)
  3015. {
  3016. void __iomem *port_mmio = mv_port_base(mmio, port);
  3017. mv_reset_channel(hpriv, mmio, port);
  3018. ZERO(0x028); /* command */
  3019. writel(0x101f, port_mmio + EDMA_CFG);
  3020. ZERO(0x004); /* timer */
  3021. ZERO(0x008); /* irq err cause */
  3022. ZERO(0x00c); /* irq err mask */
  3023. ZERO(0x010); /* rq bah */
  3024. ZERO(0x014); /* rq inp */
  3025. ZERO(0x018); /* rq outp */
  3026. ZERO(0x01c); /* respq bah */
  3027. ZERO(0x024); /* respq outp */
  3028. ZERO(0x020); /* respq inp */
  3029. ZERO(0x02c); /* test control */
  3030. writel(0x800, port_mmio + EDMA_IORDY_TMOUT);
  3031. }
  3032. #undef ZERO
  3033. #define ZERO(reg) writel(0, hc_mmio + (reg))
  3034. static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,
  3035. void __iomem *mmio)
  3036. {
  3037. void __iomem *hc_mmio = mv_hc_base(mmio, 0);
  3038. ZERO(0x00c);
  3039. ZERO(0x010);
  3040. ZERO(0x014);
  3041. }
  3042. #undef ZERO
  3043. static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
  3044. void __iomem *mmio, unsigned int n_hc)
  3045. {
  3046. unsigned int port;
  3047. for (port = 0; port < hpriv->n_ports; port++)
  3048. mv_soc_reset_hc_port(hpriv, mmio, port);
  3049. mv_soc_reset_one_hc(hpriv, mmio);
  3050. return 0;
  3051. }
  3052. static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
  3053. void __iomem *mmio)
  3054. {
  3055. return;
  3056. }
  3057. static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
  3058. {
  3059. return;
  3060. }
  3061. static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,
  3062. void __iomem *mmio, unsigned int port)
  3063. {
  3064. void __iomem *port_mmio = mv_port_base(mmio, port);
  3065. u32 reg;
  3066. reg = readl(port_mmio + PHY_MODE3);
  3067. reg &= ~(0x3 << 27); /* SELMUPF (bits 28:27) to 1 */
  3068. reg |= (0x1 << 27);
  3069. reg &= ~(0x3 << 29); /* SELMUPI (bits 30:29) to 1 */
  3070. reg |= (0x1 << 29);
  3071. writel(reg, port_mmio + PHY_MODE3);
  3072. reg = readl(port_mmio + PHY_MODE4);
  3073. reg &= ~0x1; /* SATU_OD8 (bit 0) to 0, reserved bit 16 must be set */
  3074. reg |= (0x1 << 16);
  3075. writel(reg, port_mmio + PHY_MODE4);
  3076. reg = readl(port_mmio + PHY_MODE9_GEN2);
  3077. reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */
  3078. reg |= 0x8;
  3079. reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */
  3080. writel(reg, port_mmio + PHY_MODE9_GEN2);
  3081. reg = readl(port_mmio + PHY_MODE9_GEN1);
  3082. reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */
  3083. reg |= 0x8;
  3084. reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */
  3085. writel(reg, port_mmio + PHY_MODE9_GEN1);
  3086. }
  3087. /**
  3088. * soc_is_65 - check if the soc is 65 nano device
  3089. *
  3090. * Detect the type of the SoC, this is done by reading the PHYCFG_OFS
  3091. * register, this register should contain non-zero value and it exists only
  3092. * in the 65 nano devices, when reading it from older devices we get 0.
  3093. */
  3094. static bool soc_is_65n(struct mv_host_priv *hpriv)
  3095. {
  3096. void __iomem *port0_mmio = mv_port_base(hpriv->base, 0);
  3097. if (readl(port0_mmio + PHYCFG_OFS))
  3098. return true;
  3099. return false;
  3100. }
  3101. static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)
  3102. {
  3103. u32 ifcfg = readl(port_mmio + SATA_IFCFG);
  3104. ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */
  3105. if (want_gen2i)
  3106. ifcfg |= (1 << 7); /* enable gen2i speed */
  3107. writelfl(ifcfg, port_mmio + SATA_IFCFG);
  3108. }
  3109. static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
  3110. unsigned int port_no)
  3111. {
  3112. void __iomem *port_mmio = mv_port_base(mmio, port_no);
  3113. /*
  3114. * The datasheet warns against setting EDMA_RESET when EDMA is active
  3115. * (but doesn't say what the problem might be). So we first try
  3116. * to disable the EDMA engine before doing the EDMA_RESET operation.
  3117. */
  3118. mv_stop_edma_engine(port_mmio);
  3119. writelfl(EDMA_RESET, port_mmio + EDMA_CMD);
  3120. if (!IS_GEN_I(hpriv)) {
  3121. /* Enable 3.0gb/s link speed: this survives EDMA_RESET */
  3122. mv_setup_ifcfg(port_mmio, 1);
  3123. }
  3124. /*
  3125. * Strobing EDMA_RESET here causes a hard reset of the SATA transport,
  3126. * link, and physical layers. It resets all SATA interface registers
  3127. * (except for SATA_IFCFG), and issues a COMRESET to the dev.
  3128. */
  3129. writelfl(EDMA_RESET, port_mmio + EDMA_CMD);
  3130. udelay(25); /* allow reset propagation */
  3131. writelfl(0, port_mmio + EDMA_CMD);
  3132. hpriv->ops->phy_errata(hpriv, mmio, port_no);
  3133. if (IS_GEN_I(hpriv))
  3134. usleep_range(500, 1000);
  3135. }
  3136. static void mv_pmp_select(struct ata_port *ap, int pmp)
  3137. {
  3138. if (sata_pmp_supported(ap)) {
  3139. void __iomem *port_mmio = mv_ap_base(ap);
  3140. u32 reg = readl(port_mmio + SATA_IFCTL);
  3141. int old = reg & 0xf;
  3142. if (old != pmp) {
  3143. reg = (reg & ~0xf) | pmp;
  3144. writelfl(reg, port_mmio + SATA_IFCTL);
  3145. }
  3146. }
  3147. }
  3148. static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
  3149. unsigned long deadline)
  3150. {
  3151. mv_pmp_select(link->ap, sata_srst_pmp(link));
  3152. return sata_std_hardreset(link, class, deadline);
  3153. }
  3154. static int mv_softreset(struct ata_link *link, unsigned int *class,
  3155. unsigned long deadline)
  3156. {
  3157. mv_pmp_select(link->ap, sata_srst_pmp(link));
  3158. return ata_sff_softreset(link, class, deadline);
  3159. }
  3160. static int mv_hardreset(struct ata_link *link, unsigned int *class,
  3161. unsigned long deadline)
  3162. {
  3163. struct ata_port *ap = link->ap;
  3164. struct mv_host_priv *hpriv = ap->host->private_data;
  3165. struct mv_port_priv *pp = ap->private_data;
  3166. void __iomem *mmio = hpriv->base;
  3167. int rc, attempts = 0, extra = 0;
  3168. u32 sstatus;
  3169. bool online;
  3170. mv_reset_channel(hpriv, mmio, ap->port_no);
  3171. pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
  3172. pp->pp_flags &=
  3173. ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY);
  3174. /* Workaround for errata FEr SATA#10 (part 2) */
  3175. do {
  3176. const unsigned long *timing =
  3177. sata_ehc_deb_timing(&link->eh_context);
  3178. rc = sata_link_hardreset(link, timing, deadline + extra,
  3179. &online, NULL);
  3180. rc = online ? -EAGAIN : rc;
  3181. if (rc)
  3182. return rc;
  3183. sata_scr_read(link, SCR_STATUS, &sstatus);
  3184. if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {
  3185. /* Force 1.5gb/s link speed and try again */
  3186. mv_setup_ifcfg(mv_ap_base(ap), 0);
  3187. if (time_after(jiffies + HZ, deadline))
  3188. extra = HZ; /* only extend it once, max */
  3189. }
  3190. } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123);
  3191. mv_save_cached_regs(ap);
  3192. mv_edma_cfg(ap, 0, 0);
  3193. return rc;
  3194. }
  3195. static void mv_eh_freeze(struct ata_port *ap)
  3196. {
  3197. mv_stop_edma(ap);
  3198. mv_enable_port_irqs(ap, 0);
  3199. }
  3200. static void mv_eh_thaw(struct ata_port *ap)
  3201. {
  3202. struct mv_host_priv *hpriv = ap->host->private_data;
  3203. unsigned int port = ap->port_no;
  3204. unsigned int hardport = mv_hardport_from_port(port);
  3205. void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);
  3206. void __iomem *port_mmio = mv_ap_base(ap);
  3207. u32 hc_irq_cause;
  3208. /* clear EDMA errors on this port */
  3209. writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
  3210. /* clear pending irq events */
  3211. hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
  3212. writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE);
  3213. mv_enable_port_irqs(ap, ERR_IRQ);
  3214. }
  3215. /**
  3216. * mv_port_init - Perform some early initialization on a single port.
  3217. * @port: libata data structure storing shadow register addresses
  3218. * @port_mmio: base address of the port
  3219. *
  3220. * Initialize shadow register mmio addresses, clear outstanding
  3221. * interrupts on the port, and unmask interrupts for the future
  3222. * start of the port.
  3223. *
  3224. * LOCKING:
  3225. * Inherited from caller.
  3226. */
  3227. static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
  3228. {
  3229. void __iomem *serr, *shd_base = port_mmio + SHD_BLK;
  3230. /* PIO related setup
  3231. */
  3232. port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
  3233. port->error_addr =
  3234. port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
  3235. port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
  3236. port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
  3237. port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
  3238. port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
  3239. port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
  3240. port->status_addr =
  3241. port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
  3242. /* special case: control/altstatus doesn't have ATA_REG_ address */
  3243. port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST;
  3244. /* Clear any currently outstanding port interrupt conditions */
  3245. serr = port_mmio + mv_scr_offset(SCR_ERROR);
  3246. writelfl(readl(serr), serr);
  3247. writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
  3248. /* unmask all non-transient EDMA error interrupts */
  3249. writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK);
  3250. VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
  3251. readl(port_mmio + EDMA_CFG),
  3252. readl(port_mmio + EDMA_ERR_IRQ_CAUSE),
  3253. readl(port_mmio + EDMA_ERR_IRQ_MASK));
  3254. }
  3255. static unsigned int mv_in_pcix_mode(struct ata_host *host)
  3256. {
  3257. struct mv_host_priv *hpriv = host->private_data;
  3258. void __iomem *mmio = hpriv->base;
  3259. u32 reg;
  3260. if (IS_SOC(hpriv) || !IS_PCIE(hpriv))
  3261. return 0; /* not PCI-X capable */
  3262. reg = readl(mmio + MV_PCI_MODE);
  3263. if ((reg & MV_PCI_MODE_MASK) == 0)
  3264. return 0; /* conventional PCI mode */
  3265. return 1; /* chip is in PCI-X mode */
  3266. }
  3267. static int mv_pci_cut_through_okay(struct ata_host *host)
  3268. {
  3269. struct mv_host_priv *hpriv = host->private_data;
  3270. void __iomem *mmio = hpriv->base;
  3271. u32 reg;
  3272. if (!mv_in_pcix_mode(host)) {
  3273. reg = readl(mmio + MV_PCI_COMMAND);
  3274. if (reg & MV_PCI_COMMAND_MRDTRIG)
  3275. return 0; /* not okay */
  3276. }
  3277. return 1; /* okay */
  3278. }
  3279. static void mv_60x1b2_errata_pci7(struct ata_host *host)
  3280. {
  3281. struct mv_host_priv *hpriv = host->private_data;
  3282. void __iomem *mmio = hpriv->base;
  3283. /* workaround for 60x1-B2 errata PCI#7 */
  3284. if (mv_in_pcix_mode(host)) {
  3285. u32 reg = readl(mmio + MV_PCI_COMMAND);
  3286. writelfl(reg & ~MV_PCI_COMMAND_MWRCOM, mmio + MV_PCI_COMMAND);
  3287. }
  3288. }
  3289. static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
  3290. {
  3291. struct pci_dev *pdev = to_pci_dev(host->dev);
  3292. struct mv_host_priv *hpriv = host->private_data;
  3293. u32 hp_flags = hpriv->hp_flags;
  3294. switch (board_idx) {
  3295. case chip_5080:
  3296. hpriv->ops = &mv5xxx_ops;
  3297. hp_flags |= MV_HP_GEN_I;
  3298. switch (pdev->revision) {
  3299. case 0x1:
  3300. hp_flags |= MV_HP_ERRATA_50XXB0;
  3301. break;
  3302. case 0x3:
  3303. hp_flags |= MV_HP_ERRATA_50XXB2;
  3304. break;
  3305. default:
  3306. dev_warn(&pdev->dev,
  3307. "Applying 50XXB2 workarounds to unknown rev\n");
  3308. hp_flags |= MV_HP_ERRATA_50XXB2;
  3309. break;
  3310. }
  3311. break;
  3312. case chip_504x:
  3313. case chip_508x:
  3314. hpriv->ops = &mv5xxx_ops;
  3315. hp_flags |= MV_HP_GEN_I;
  3316. switch (pdev->revision) {
  3317. case 0x0:
  3318. hp_flags |= MV_HP_ERRATA_50XXB0;
  3319. break;
  3320. case 0x3:
  3321. hp_flags |= MV_HP_ERRATA_50XXB2;
  3322. break;
  3323. default:
  3324. dev_warn(&pdev->dev,
  3325. "Applying B2 workarounds to unknown rev\n");
  3326. hp_flags |= MV_HP_ERRATA_50XXB2;
  3327. break;
  3328. }
  3329. break;
  3330. case chip_604x:
  3331. case chip_608x:
  3332. hpriv->ops = &mv6xxx_ops;
  3333. hp_flags |= MV_HP_GEN_II;
  3334. switch (pdev->revision) {
  3335. case 0x7:
  3336. mv_60x1b2_errata_pci7(host);
  3337. hp_flags |= MV_HP_ERRATA_60X1B2;
  3338. break;
  3339. case 0x9:
  3340. hp_flags |= MV_HP_ERRATA_60X1C0;
  3341. break;
  3342. default:
  3343. dev_warn(&pdev->dev,
  3344. "Applying B2 workarounds to unknown rev\n");
  3345. hp_flags |= MV_HP_ERRATA_60X1B2;
  3346. break;
  3347. }
  3348. break;
  3349. case chip_7042:
  3350. hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH;
  3351. if (pdev->vendor == PCI_VENDOR_ID_TTI &&
  3352. (pdev->device == 0x2300 || pdev->device == 0x2310))
  3353. {
  3354. /*
  3355. * Highpoint RocketRAID PCIe 23xx series cards:
  3356. *
  3357. * Unconfigured drives are treated as "Legacy"
  3358. * by the BIOS, and it overwrites sector 8 with
  3359. * a "Lgcy" metadata block prior to Linux boot.
  3360. *
  3361. * Configured drives (RAID or JBOD) leave sector 8
  3362. * alone, but instead overwrite a high numbered
  3363. * sector for the RAID metadata. This sector can
  3364. * be determined exactly, by truncating the physical
  3365. * drive capacity to a nice even GB value.
  3366. *
  3367. * RAID metadata is at: (dev->n_sectors & ~0xfffff)
  3368. *
  3369. * Warn the user, lest they think we're just buggy.
  3370. */
  3371. printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID"
  3372. " BIOS CORRUPTS DATA on all attached drives,"
  3373. " regardless of if/how they are configured."
  3374. " BEWARE!\n");
  3375. printk(KERN_WARNING DRV_NAME ": For data safety, do not"
  3376. " use sectors 8-9 on \"Legacy\" drives,"
  3377. " and avoid the final two gigabytes on"
  3378. " all RocketRAID BIOS initialized drives.\n");
  3379. }
  3380. fallthrough;
  3381. case chip_6042:
  3382. hpriv->ops = &mv6xxx_ops;
  3383. hp_flags |= MV_HP_GEN_IIE;
  3384. if (board_idx == chip_6042 && mv_pci_cut_through_okay(host))
  3385. hp_flags |= MV_HP_CUT_THROUGH;
  3386. switch (pdev->revision) {
  3387. case 0x2: /* Rev.B0: the first/only public release */
  3388. hp_flags |= MV_HP_ERRATA_60X1C0;
  3389. break;
  3390. default:
  3391. dev_warn(&pdev->dev,
  3392. "Applying 60X1C0 workarounds to unknown rev\n");
  3393. hp_flags |= MV_HP_ERRATA_60X1C0;
  3394. break;
  3395. }
  3396. break;
  3397. case chip_soc:
  3398. if (soc_is_65n(hpriv))
  3399. hpriv->ops = &mv_soc_65n_ops;
  3400. else
  3401. hpriv->ops = &mv_soc_ops;
  3402. hp_flags |= MV_HP_FLAG_SOC | MV_HP_GEN_IIE |
  3403. MV_HP_ERRATA_60X1C0;
  3404. break;
  3405. default:
  3406. dev_alert(host->dev, "BUG: invalid board index %u\n", board_idx);
  3407. return -EINVAL;
  3408. }
  3409. hpriv->hp_flags = hp_flags;
  3410. if (hp_flags & MV_HP_PCIE) {
  3411. hpriv->irq_cause_offset = PCIE_IRQ_CAUSE;
  3412. hpriv->irq_mask_offset = PCIE_IRQ_MASK;
  3413. hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS;
  3414. } else {
  3415. hpriv->irq_cause_offset = PCI_IRQ_CAUSE;
  3416. hpriv->irq_mask_offset = PCI_IRQ_MASK;
  3417. hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS;
  3418. }
  3419. return 0;
  3420. }
  3421. /**
  3422. * mv_init_host - Perform some early initialization of the host.
  3423. * @host: ATA host to initialize
  3424. *
  3425. * If possible, do an early global reset of the host. Then do
  3426. * our port init and clear/unmask all/relevant host interrupts.
  3427. *
  3428. * LOCKING:
  3429. * Inherited from caller.
  3430. */
  3431. static int mv_init_host(struct ata_host *host)
  3432. {
  3433. int rc = 0, n_hc, port, hc;
  3434. struct mv_host_priv *hpriv = host->private_data;
  3435. void __iomem *mmio = hpriv->base;
  3436. rc = mv_chip_id(host, hpriv->board_idx);
  3437. if (rc)
  3438. goto done;
  3439. if (IS_SOC(hpriv)) {
  3440. hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE;
  3441. hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK;
  3442. } else {
  3443. hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE;
  3444. hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK;
  3445. }
  3446. /* initialize shadow irq mask with register's value */
  3447. hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr);
  3448. /* global interrupt mask: 0 == mask everything */
  3449. mv_set_main_irq_mask(host, ~0, 0);
  3450. n_hc = mv_get_hc_count(host->ports[0]->flags);
  3451. for (port = 0; port < host->n_ports; port++)
  3452. if (hpriv->ops->read_preamp)
  3453. hpriv->ops->read_preamp(hpriv, port, mmio);
  3454. rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
  3455. if (rc)
  3456. goto done;
  3457. hpriv->ops->reset_flash(hpriv, mmio);
  3458. hpriv->ops->reset_bus(host, mmio);
  3459. hpriv->ops->enable_leds(hpriv, mmio);
  3460. for (port = 0; port < host->n_ports; port++) {
  3461. struct ata_port *ap = host->ports[port];
  3462. void __iomem *port_mmio = mv_port_base(mmio, port);
  3463. mv_port_init(&ap->ioaddr, port_mmio);
  3464. }
  3465. for (hc = 0; hc < n_hc; hc++) {
  3466. void __iomem *hc_mmio = mv_hc_base(mmio, hc);
  3467. VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
  3468. "(before clear)=0x%08x\n", hc,
  3469. readl(hc_mmio + HC_CFG),
  3470. readl(hc_mmio + HC_IRQ_CAUSE));
  3471. /* Clear any currently outstanding hc interrupt conditions */
  3472. writelfl(0, hc_mmio + HC_IRQ_CAUSE);
  3473. }
  3474. if (!IS_SOC(hpriv)) {
  3475. /* Clear any currently outstanding host interrupt conditions */
  3476. writelfl(0, mmio + hpriv->irq_cause_offset);
  3477. /* and unmask interrupt generation for host regs */
  3478. writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_offset);
  3479. }
  3480. /*
  3481. * enable only global host interrupts for now.
  3482. * The per-port interrupts get done later as ports are set up.
  3483. */
  3484. mv_set_main_irq_mask(host, 0, PCI_ERR);
  3485. mv_set_irq_coalescing(host, irq_coalescing_io_count,
  3486. irq_coalescing_usecs);
  3487. done:
  3488. return rc;
  3489. }
  3490. static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)
  3491. {
  3492. hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,
  3493. MV_CRQB_Q_SZ, 0);
  3494. if (!hpriv->crqb_pool)
  3495. return -ENOMEM;
  3496. hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,
  3497. MV_CRPB_Q_SZ, 0);
  3498. if (!hpriv->crpb_pool)
  3499. return -ENOMEM;
  3500. hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,
  3501. MV_SG_TBL_SZ, 0);
  3502. if (!hpriv->sg_tbl_pool)
  3503. return -ENOMEM;
  3504. return 0;
  3505. }
  3506. static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
  3507. const struct mbus_dram_target_info *dram)
  3508. {
  3509. int i;
  3510. for (i = 0; i < 4; i++) {
  3511. writel(0, hpriv->base + WINDOW_CTRL(i));
  3512. writel(0, hpriv->base + WINDOW_BASE(i));
  3513. }
  3514. for (i = 0; i < dram->num_cs; i++) {
  3515. const struct mbus_dram_window *cs = dram->cs + i;
  3516. writel(((cs->size - 1) & 0xffff0000) |
  3517. (cs->mbus_attr << 8) |
  3518. (dram->mbus_dram_target_id << 4) | 1,
  3519. hpriv->base + WINDOW_CTRL(i));
  3520. writel(cs->base, hpriv->base + WINDOW_BASE(i));
  3521. }
  3522. }
  3523. /**
  3524. * mv_platform_probe - handle a positive probe of an soc Marvell
  3525. * host
  3526. * @pdev: platform device found
  3527. *
  3528. * LOCKING:
  3529. * Inherited from caller.
  3530. */
  3531. static int mv_platform_probe(struct platform_device *pdev)
  3532. {
  3533. const struct mv_sata_platform_data *mv_platform_data;
  3534. const struct mbus_dram_target_info *dram;
  3535. const struct ata_port_info *ppi[] =
  3536. { &mv_port_info[chip_soc], NULL };
  3537. struct ata_host *host;
  3538. struct mv_host_priv *hpriv;
  3539. struct resource *res;
  3540. int n_ports = 0, irq = 0;
  3541. int rc;
  3542. int port;
  3543. ata_print_version_once(&pdev->dev, DRV_VERSION);
  3544. /*
  3545. * Simple resource validation ..
  3546. */
  3547. if (unlikely(pdev->num_resources != 2)) {
  3548. dev_err(&pdev->dev, "invalid number of resources\n");
  3549. return -EINVAL;
  3550. }
  3551. /*
  3552. * Get the register base first
  3553. */
  3554. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  3555. if (res == NULL)
  3556. return -EINVAL;
  3557. /* allocate host */
  3558. if (pdev->dev.of_node) {
  3559. rc = of_property_read_u32(pdev->dev.of_node, "nr-ports",
  3560. &n_ports);
  3561. if (rc) {
  3562. dev_err(&pdev->dev,
  3563. "error parsing nr-ports property: %d\n", rc);
  3564. return rc;
  3565. }
  3566. if (n_ports <= 0) {
  3567. dev_err(&pdev->dev, "nr-ports must be positive: %d\n",
  3568. n_ports);
  3569. return -EINVAL;
  3570. }
  3571. irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
  3572. } else {
  3573. mv_platform_data = dev_get_platdata(&pdev->dev);
  3574. n_ports = mv_platform_data->n_ports;
  3575. irq = platform_get_irq(pdev, 0);
  3576. }
  3577. if (irq < 0)
  3578. return irq;
  3579. if (!irq)
  3580. return -EINVAL;
  3581. host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
  3582. hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
  3583. if (!host || !hpriv)
  3584. return -ENOMEM;
  3585. hpriv->port_clks = devm_kcalloc(&pdev->dev,
  3586. n_ports, sizeof(struct clk *),
  3587. GFP_KERNEL);
  3588. if (!hpriv->port_clks)
  3589. return -ENOMEM;
  3590. hpriv->port_phys = devm_kcalloc(&pdev->dev,
  3591. n_ports, sizeof(struct phy *),
  3592. GFP_KERNEL);
  3593. if (!hpriv->port_phys)
  3594. return -ENOMEM;
  3595. host->private_data = hpriv;
  3596. hpriv->board_idx = chip_soc;
  3597. host->iomap = NULL;
  3598. hpriv->base = devm_ioremap(&pdev->dev, res->start,
  3599. resource_size(res));
  3600. if (!hpriv->base)
  3601. return -ENOMEM;
  3602. hpriv->base -= SATAHC0_REG_BASE;
  3603. hpriv->clk = clk_get(&pdev->dev, NULL);
  3604. if (IS_ERR(hpriv->clk))
  3605. dev_notice(&pdev->dev, "cannot get optional clkdev\n");
  3606. else
  3607. clk_prepare_enable(hpriv->clk);
  3608. for (port = 0; port < n_ports; port++) {
  3609. char port_number[16];
  3610. sprintf(port_number, "%d", port);
  3611. hpriv->port_clks[port] = clk_get(&pdev->dev, port_number);
  3612. if (!IS_ERR(hpriv->port_clks[port]))
  3613. clk_prepare_enable(hpriv->port_clks[port]);
  3614. sprintf(port_number, "port%d", port);
  3615. hpriv->port_phys[port] = devm_phy_optional_get(&pdev->dev,
  3616. port_number);
  3617. if (IS_ERR(hpriv->port_phys[port])) {
  3618. rc = PTR_ERR(hpriv->port_phys[port]);
  3619. hpriv->port_phys[port] = NULL;
  3620. if (rc != -EPROBE_DEFER)
  3621. dev_warn(&pdev->dev, "error getting phy %d", rc);
  3622. /* Cleanup only the initialized ports */
  3623. hpriv->n_ports = port;
  3624. goto err;
  3625. } else
  3626. phy_power_on(hpriv->port_phys[port]);
  3627. }
  3628. /* All the ports have been initialized */
  3629. hpriv->n_ports = n_ports;
  3630. /*
  3631. * (Re-)program MBUS remapping windows if we are asked to.
  3632. */
  3633. dram = mv_mbus_dram_info();
  3634. if (dram)
  3635. mv_conf_mbus_windows(hpriv, dram);
  3636. rc = mv_create_dma_pools(hpriv, &pdev->dev);
  3637. if (rc)
  3638. goto err;
  3639. /*
  3640. * To allow disk hotplug on Armada 370/XP SoCs, the PHY speed must be
  3641. * updated in the LP_PHY_CTL register.
  3642. */
  3643. if (pdev->dev.of_node &&
  3644. of_device_is_compatible(pdev->dev.of_node,
  3645. "marvell,armada-370-sata"))
  3646. hpriv->hp_flags |= MV_HP_FIX_LP_PHY_CTL;
  3647. /* initialize adapter */
  3648. rc = mv_init_host(host);
  3649. if (rc)
  3650. goto err;
  3651. dev_info(&pdev->dev, "slots %u ports %d\n",
  3652. (unsigned)MV_MAX_Q_DEPTH, host->n_ports);
  3653. rc = ata_host_activate(host, irq, mv_interrupt, IRQF_SHARED, &mv6_sht);
  3654. if (!rc)
  3655. return 0;
  3656. err:
  3657. if (!IS_ERR(hpriv->clk)) {
  3658. clk_disable_unprepare(hpriv->clk);
  3659. clk_put(hpriv->clk);
  3660. }
  3661. for (port = 0; port < hpriv->n_ports; port++) {
  3662. if (!IS_ERR(hpriv->port_clks[port])) {
  3663. clk_disable_unprepare(hpriv->port_clks[port]);
  3664. clk_put(hpriv->port_clks[port]);
  3665. }
  3666. phy_power_off(hpriv->port_phys[port]);
  3667. }
  3668. return rc;
  3669. }
  3670. /*
  3671. *
  3672. * mv_platform_remove - unplug a platform interface
  3673. * @pdev: platform device
  3674. *
  3675. * A platform bus SATA device has been unplugged. Perform the needed
  3676. * cleanup. Also called on module unload for any active devices.
  3677. */
  3678. static int mv_platform_remove(struct platform_device *pdev)
  3679. {
  3680. struct ata_host *host = platform_get_drvdata(pdev);
  3681. struct mv_host_priv *hpriv = host->private_data;
  3682. int port;
  3683. ata_host_detach(host);
  3684. if (!IS_ERR(hpriv->clk)) {
  3685. clk_disable_unprepare(hpriv->clk);
  3686. clk_put(hpriv->clk);
  3687. }
  3688. for (port = 0; port < host->n_ports; port++) {
  3689. if (!IS_ERR(hpriv->port_clks[port])) {
  3690. clk_disable_unprepare(hpriv->port_clks[port]);
  3691. clk_put(hpriv->port_clks[port]);
  3692. }
  3693. phy_power_off(hpriv->port_phys[port]);
  3694. }
  3695. return 0;
  3696. }
  3697. #ifdef CONFIG_PM_SLEEP
  3698. static int mv_platform_suspend(struct platform_device *pdev, pm_message_t state)
  3699. {
  3700. struct ata_host *host = platform_get_drvdata(pdev);
  3701. if (host)
  3702. return ata_host_suspend(host, state);
  3703. else
  3704. return 0;
  3705. }
  3706. static int mv_platform_resume(struct platform_device *pdev)
  3707. {
  3708. struct ata_host *host = platform_get_drvdata(pdev);
  3709. const struct mbus_dram_target_info *dram;
  3710. int ret;
  3711. if (host) {
  3712. struct mv_host_priv *hpriv = host->private_data;
  3713. /*
  3714. * (Re-)program MBUS remapping windows if we are asked to.
  3715. */
  3716. dram = mv_mbus_dram_info();
  3717. if (dram)
  3718. mv_conf_mbus_windows(hpriv, dram);
  3719. /* initialize adapter */
  3720. ret = mv_init_host(host);
  3721. if (ret) {
  3722. printk(KERN_ERR DRV_NAME ": Error during HW init\n");
  3723. return ret;
  3724. }
  3725. ata_host_resume(host);
  3726. }
  3727. return 0;
  3728. }
  3729. #else
  3730. #define mv_platform_suspend NULL
  3731. #define mv_platform_resume NULL
  3732. #endif
  3733. #ifdef CONFIG_OF
  3734. static const struct of_device_id mv_sata_dt_ids[] = {
  3735. { .compatible = "marvell,armada-370-sata", },
  3736. { .compatible = "marvell,orion-sata", },
  3737. {},
  3738. };
  3739. MODULE_DEVICE_TABLE(of, mv_sata_dt_ids);
  3740. #endif
  3741. static struct platform_driver mv_platform_driver = {
  3742. .probe = mv_platform_probe,
  3743. .remove = mv_platform_remove,
  3744. .suspend = mv_platform_suspend,
  3745. .resume = mv_platform_resume,
  3746. .driver = {
  3747. .name = DRV_NAME,
  3748. .of_match_table = of_match_ptr(mv_sata_dt_ids),
  3749. },
  3750. };
  3751. #ifdef CONFIG_PCI
  3752. static int mv_pci_init_one(struct pci_dev *pdev,
  3753. const struct pci_device_id *ent);
  3754. #ifdef CONFIG_PM_SLEEP
  3755. static int mv_pci_device_resume(struct pci_dev *pdev);
  3756. #endif
  3757. static struct pci_driver mv_pci_driver = {
  3758. .name = DRV_NAME,
  3759. .id_table = mv_pci_tbl,
  3760. .probe = mv_pci_init_one,
  3761. .remove = ata_pci_remove_one,
  3762. #ifdef CONFIG_PM_SLEEP
  3763. .suspend = ata_pci_device_suspend,
  3764. .resume = mv_pci_device_resume,
  3765. #endif
  3766. };
  3767. /**
  3768. * mv_print_info - Dump key info to kernel log for perusal.
  3769. * @host: ATA host to print info about
  3770. *
  3771. * FIXME: complete this.
  3772. *
  3773. * LOCKING:
  3774. * Inherited from caller.
  3775. */
  3776. static void mv_print_info(struct ata_host *host)
  3777. {
  3778. struct pci_dev *pdev = to_pci_dev(host->dev);
  3779. struct mv_host_priv *hpriv = host->private_data;
  3780. u8 scc;
  3781. const char *scc_s, *gen;
  3782. /* Use this to determine the HW stepping of the chip so we know
  3783. * what errata to workaround
  3784. */
  3785. pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
  3786. if (scc == 0)
  3787. scc_s = "SCSI";
  3788. else if (scc == 0x01)
  3789. scc_s = "RAID";
  3790. else
  3791. scc_s = "?";
  3792. if (IS_GEN_I(hpriv))
  3793. gen = "I";
  3794. else if (IS_GEN_II(hpriv))
  3795. gen = "II";
  3796. else if (IS_GEN_IIE(hpriv))
  3797. gen = "IIE";
  3798. else
  3799. gen = "?";
  3800. dev_info(&pdev->dev, "Gen-%s %u slots %u ports %s mode IRQ via %s\n",
  3801. gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
  3802. scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
  3803. }
  3804. /**
  3805. * mv_pci_init_one - handle a positive probe of a PCI Marvell host
  3806. * @pdev: PCI device found
  3807. * @ent: PCI device ID entry for the matched host
  3808. *
  3809. * LOCKING:
  3810. * Inherited from caller.
  3811. */
  3812. static int mv_pci_init_one(struct pci_dev *pdev,
  3813. const struct pci_device_id *ent)
  3814. {
  3815. unsigned int board_idx = (unsigned int)ent->driver_data;
  3816. const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL };
  3817. struct ata_host *host;
  3818. struct mv_host_priv *hpriv;
  3819. int n_ports, port, rc;
  3820. ata_print_version_once(&pdev->dev, DRV_VERSION);
  3821. /* allocate host */
  3822. n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC;
  3823. host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
  3824. hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
  3825. if (!host || !hpriv)
  3826. return -ENOMEM;
  3827. host->private_data = hpriv;
  3828. hpriv->n_ports = n_ports;
  3829. hpriv->board_idx = board_idx;
  3830. /* acquire resources */
  3831. rc = pcim_enable_device(pdev);
  3832. if (rc)
  3833. return rc;
  3834. rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
  3835. if (rc == -EBUSY)
  3836. pcim_pin_device(pdev);
  3837. if (rc)
  3838. return rc;
  3839. host->iomap = pcim_iomap_table(pdev);
  3840. hpriv->base = host->iomap[MV_PRIMARY_BAR];
  3841. rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
  3842. if (rc) {
  3843. dev_err(&pdev->dev, "DMA enable failed\n");
  3844. return rc;
  3845. }
  3846. rc = mv_create_dma_pools(hpriv, &pdev->dev);
  3847. if (rc)
  3848. return rc;
  3849. for (port = 0; port < host->n_ports; port++) {
  3850. struct ata_port *ap = host->ports[port];
  3851. void __iomem *port_mmio = mv_port_base(hpriv->base, port);
  3852. unsigned int offset = port_mmio - hpriv->base;
  3853. ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");
  3854. ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");
  3855. }
  3856. /* initialize adapter */
  3857. rc = mv_init_host(host);
  3858. if (rc)
  3859. return rc;
  3860. /* Enable message-switched interrupts, if requested */
  3861. if (msi && pci_enable_msi(pdev) == 0)
  3862. hpriv->hp_flags |= MV_HP_FLAG_MSI;
  3863. mv_dump_pci_cfg(pdev, 0x68);
  3864. mv_print_info(host);
  3865. pci_set_master(pdev);
  3866. pci_try_set_mwi(pdev);
  3867. return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,
  3868. IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);
  3869. }
  3870. #ifdef CONFIG_PM_SLEEP
  3871. static int mv_pci_device_resume(struct pci_dev *pdev)
  3872. {
  3873. struct ata_host *host = pci_get_drvdata(pdev);
  3874. int rc;
  3875. rc = ata_pci_device_do_resume(pdev);
  3876. if (rc)
  3877. return rc;
  3878. /* initialize adapter */
  3879. rc = mv_init_host(host);
  3880. if (rc)
  3881. return rc;
  3882. ata_host_resume(host);
  3883. return 0;
  3884. }
  3885. #endif
  3886. #endif
  3887. static int __init mv_init(void)
  3888. {
  3889. int rc = -ENODEV;
  3890. #ifdef CONFIG_PCI
  3891. rc = pci_register_driver(&mv_pci_driver);
  3892. if (rc < 0)
  3893. return rc;
  3894. #endif
  3895. rc = platform_driver_register(&mv_platform_driver);
  3896. #ifdef CONFIG_PCI
  3897. if (rc < 0)
  3898. pci_unregister_driver(&mv_pci_driver);
  3899. #endif
  3900. return rc;
  3901. }
  3902. static void __exit mv_exit(void)
  3903. {
  3904. #ifdef CONFIG_PCI
  3905. pci_unregister_driver(&mv_pci_driver);
  3906. #endif
  3907. platform_driver_unregister(&mv_platform_driver);
  3908. }
  3909. MODULE_AUTHOR("Brett Russ");
  3910. MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
  3911. MODULE_LICENSE("GPL v2");
  3912. MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
  3913. MODULE_VERSION(DRV_VERSION);
  3914. MODULE_ALIAS("platform:" DRV_NAME);
  3915. module_init(mv_init);
  3916. module_exit(mv_exit);