sata_inic162x.c 24 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * sata_inic162x.c - Driver for Initio 162x SATA controllers
  4. *
  5. * Copyright 2006 SUSE Linux Products GmbH
  6. * Copyright 2006 Tejun Heo <teheo@novell.com>
  7. *
  8. * **** WARNING ****
  9. *
  10. * This driver never worked properly and unfortunately data corruption is
  11. * relatively common. There isn't anyone working on the driver and there's
  12. * no support from the vendor. Do not use this driver in any production
  13. * environment.
  14. *
  15. * http://thread.gmane.org/gmane.linux.debian.devel.bugs.rc/378525/focus=54491
  16. * https://bugzilla.kernel.org/show_bug.cgi?id=60565
  17. *
  18. * *****************
  19. *
  20. * This controller is eccentric and easily locks up if something isn't
  21. * right. Documentation is available at initio's website but it only
  22. * documents registers (not programming model).
  23. *
  24. * This driver has interesting history. The first version was written
  25. * from the documentation and a 2.4 IDE driver posted on a Taiwan
  26. * company, which didn't use any IDMA features and couldn't handle
  27. * LBA48. The resulting driver couldn't handle LBA48 devices either
  28. * making it pretty useless.
  29. *
  30. * After a while, initio picked the driver up, renamed it to
  31. * sata_initio162x, updated it to use IDMA for ATA DMA commands and
  32. * posted it on their website. It only used ATA_PROT_DMA for IDMA and
  33. * attaching both devices and issuing IDMA and !IDMA commands
  34. * simultaneously broke it due to PIRQ masking interaction but it did
  35. * show how to use the IDMA (ADMA + some initio specific twists)
  36. * engine.
  37. *
  38. * Then, I picked up their changes again and here's the usable driver
  39. * which uses IDMA for everything. Everything works now including
  40. * LBA48, CD/DVD burning, suspend/resume and hotplug. There are some
  41. * issues tho. Result Tf is not resported properly, NCQ isn't
  42. * supported yet and CD/DVD writing works with DMA assisted PIO
  43. * protocol (which, for native SATA devices, shouldn't cause any
  44. * noticeable difference).
  45. *
  46. * Anyways, so, here's finally a working driver for inic162x. Enjoy!
  47. *
  48. * initio: If you guys wanna improve the driver regarding result TF
  49. * access and other stuff, please feel free to contact me. I'll be
  50. * happy to assist.
  51. */
  52. #include <linux/gfp.h>
  53. #include <linux/kernel.h>
  54. #include <linux/module.h>
  55. #include <linux/pci.h>
  56. #include <scsi/scsi_host.h>
  57. #include <linux/libata.h>
  58. #include <linux/blkdev.h>
  59. #include <scsi/scsi_device.h>
  60. #define DRV_NAME "sata_inic162x"
  61. #define DRV_VERSION "0.4"
  62. enum {
  63. MMIO_BAR_PCI = 5,
  64. MMIO_BAR_CARDBUS = 1,
  65. NR_PORTS = 2,
  66. IDMA_CPB_TBL_SIZE = 4 * 32,
  67. INIC_DMA_BOUNDARY = 0xffffff,
  68. HOST_ACTRL = 0x08,
  69. HOST_CTL = 0x7c,
  70. HOST_STAT = 0x7e,
  71. HOST_IRQ_STAT = 0xbc,
  72. HOST_IRQ_MASK = 0xbe,
  73. PORT_SIZE = 0x40,
  74. /* registers for ATA TF operation */
  75. PORT_TF_DATA = 0x00,
  76. PORT_TF_FEATURE = 0x01,
  77. PORT_TF_NSECT = 0x02,
  78. PORT_TF_LBAL = 0x03,
  79. PORT_TF_LBAM = 0x04,
  80. PORT_TF_LBAH = 0x05,
  81. PORT_TF_DEVICE = 0x06,
  82. PORT_TF_COMMAND = 0x07,
  83. PORT_TF_ALT_STAT = 0x08,
  84. PORT_IRQ_STAT = 0x09,
  85. PORT_IRQ_MASK = 0x0a,
  86. PORT_PRD_CTL = 0x0b,
  87. PORT_PRD_ADDR = 0x0c,
  88. PORT_PRD_XFERLEN = 0x10,
  89. PORT_CPB_CPBLAR = 0x18,
  90. PORT_CPB_PTQFIFO = 0x1c,
  91. /* IDMA register */
  92. PORT_IDMA_CTL = 0x14,
  93. PORT_IDMA_STAT = 0x16,
  94. PORT_RPQ_FIFO = 0x1e,
  95. PORT_RPQ_CNT = 0x1f,
  96. PORT_SCR = 0x20,
  97. /* HOST_CTL bits */
  98. HCTL_LEDEN = (1 << 3), /* enable LED operation */
  99. HCTL_IRQOFF = (1 << 8), /* global IRQ off */
  100. HCTL_FTHD0 = (1 << 10), /* fifo threshold 0 */
  101. HCTL_FTHD1 = (1 << 11), /* fifo threshold 1*/
  102. HCTL_PWRDWN = (1 << 12), /* power down PHYs */
  103. HCTL_SOFTRST = (1 << 13), /* global reset (no phy reset) */
  104. HCTL_RPGSEL = (1 << 15), /* register page select */
  105. HCTL_KNOWN_BITS = HCTL_IRQOFF | HCTL_PWRDWN | HCTL_SOFTRST |
  106. HCTL_RPGSEL,
  107. /* HOST_IRQ_(STAT|MASK) bits */
  108. HIRQ_PORT0 = (1 << 0),
  109. HIRQ_PORT1 = (1 << 1),
  110. HIRQ_SOFT = (1 << 14),
  111. HIRQ_GLOBAL = (1 << 15), /* STAT only */
  112. /* PORT_IRQ_(STAT|MASK) bits */
  113. PIRQ_OFFLINE = (1 << 0), /* device unplugged */
  114. PIRQ_ONLINE = (1 << 1), /* device plugged */
  115. PIRQ_COMPLETE = (1 << 2), /* completion interrupt */
  116. PIRQ_FATAL = (1 << 3), /* fatal error */
  117. PIRQ_ATA = (1 << 4), /* ATA interrupt */
  118. PIRQ_REPLY = (1 << 5), /* reply FIFO not empty */
  119. PIRQ_PENDING = (1 << 7), /* port IRQ pending (STAT only) */
  120. PIRQ_ERR = PIRQ_OFFLINE | PIRQ_ONLINE | PIRQ_FATAL,
  121. PIRQ_MASK_DEFAULT = PIRQ_REPLY | PIRQ_ATA,
  122. PIRQ_MASK_FREEZE = 0xff,
  123. /* PORT_PRD_CTL bits */
  124. PRD_CTL_START = (1 << 0),
  125. PRD_CTL_WR = (1 << 3),
  126. PRD_CTL_DMAEN = (1 << 7), /* DMA enable */
  127. /* PORT_IDMA_CTL bits */
  128. IDMA_CTL_RST_ATA = (1 << 2), /* hardreset ATA bus */
  129. IDMA_CTL_RST_IDMA = (1 << 5), /* reset IDMA machinery */
  130. IDMA_CTL_GO = (1 << 7), /* IDMA mode go */
  131. IDMA_CTL_ATA_NIEN = (1 << 8), /* ATA IRQ disable */
  132. /* PORT_IDMA_STAT bits */
  133. IDMA_STAT_PERR = (1 << 0), /* PCI ERROR MODE */
  134. IDMA_STAT_CPBERR = (1 << 1), /* ADMA CPB error */
  135. IDMA_STAT_LGCY = (1 << 3), /* ADMA legacy */
  136. IDMA_STAT_UIRQ = (1 << 4), /* ADMA unsolicited irq */
  137. IDMA_STAT_STPD = (1 << 5), /* ADMA stopped */
  138. IDMA_STAT_PSD = (1 << 6), /* ADMA pause */
  139. IDMA_STAT_DONE = (1 << 7), /* ADMA done */
  140. IDMA_STAT_ERR = IDMA_STAT_PERR | IDMA_STAT_CPBERR,
  141. /* CPB Control Flags*/
  142. CPB_CTL_VALID = (1 << 0), /* CPB valid */
  143. CPB_CTL_QUEUED = (1 << 1), /* queued command */
  144. CPB_CTL_DATA = (1 << 2), /* data, rsvd in datasheet */
  145. CPB_CTL_IEN = (1 << 3), /* PCI interrupt enable */
  146. CPB_CTL_DEVDIR = (1 << 4), /* device direction control */
  147. /* CPB Response Flags */
  148. CPB_RESP_DONE = (1 << 0), /* ATA command complete */
  149. CPB_RESP_REL = (1 << 1), /* ATA release */
  150. CPB_RESP_IGNORED = (1 << 2), /* CPB ignored */
  151. CPB_RESP_ATA_ERR = (1 << 3), /* ATA command error */
  152. CPB_RESP_SPURIOUS = (1 << 4), /* ATA spurious interrupt error */
  153. CPB_RESP_UNDERFLOW = (1 << 5), /* APRD deficiency length error */
  154. CPB_RESP_OVERFLOW = (1 << 6), /* APRD exccess length error */
  155. CPB_RESP_CPB_ERR = (1 << 7), /* CPB error flag */
  156. /* PRD Control Flags */
  157. PRD_DRAIN = (1 << 1), /* ignore data excess */
  158. PRD_CDB = (1 << 2), /* atapi packet command pointer */
  159. PRD_DIRECT_INTR = (1 << 3), /* direct interrupt */
  160. PRD_DMA = (1 << 4), /* data transfer method */
  161. PRD_WRITE = (1 << 5), /* data dir, rsvd in datasheet */
  162. PRD_IOM = (1 << 6), /* io/memory transfer */
  163. PRD_END = (1 << 7), /* APRD chain end */
  164. };
  165. /* Comman Parameter Block */
  166. struct inic_cpb {
  167. u8 resp_flags; /* Response Flags */
  168. u8 error; /* ATA Error */
  169. u8 status; /* ATA Status */
  170. u8 ctl_flags; /* Control Flags */
  171. __le32 len; /* Total Transfer Length */
  172. __le32 prd; /* First PRD pointer */
  173. u8 rsvd[4];
  174. /* 16 bytes */
  175. u8 feature; /* ATA Feature */
  176. u8 hob_feature; /* ATA Ex. Feature */
  177. u8 device; /* ATA Device/Head */
  178. u8 mirctl; /* Mirror Control */
  179. u8 nsect; /* ATA Sector Count */
  180. u8 hob_nsect; /* ATA Ex. Sector Count */
  181. u8 lbal; /* ATA Sector Number */
  182. u8 hob_lbal; /* ATA Ex. Sector Number */
  183. u8 lbam; /* ATA Cylinder Low */
  184. u8 hob_lbam; /* ATA Ex. Cylinder Low */
  185. u8 lbah; /* ATA Cylinder High */
  186. u8 hob_lbah; /* ATA Ex. Cylinder High */
  187. u8 command; /* ATA Command */
  188. u8 ctl; /* ATA Control */
  189. u8 slave_error; /* Slave ATA Error */
  190. u8 slave_status; /* Slave ATA Status */
  191. /* 32 bytes */
  192. } __packed;
  193. /* Physical Region Descriptor */
  194. struct inic_prd {
  195. __le32 mad; /* Physical Memory Address */
  196. __le16 len; /* Transfer Length */
  197. u8 rsvd;
  198. u8 flags; /* Control Flags */
  199. } __packed;
  200. struct inic_pkt {
  201. struct inic_cpb cpb;
  202. struct inic_prd prd[LIBATA_MAX_PRD + 1]; /* + 1 for cdb */
  203. u8 cdb[ATAPI_CDB_LEN];
  204. } __packed;
  205. struct inic_host_priv {
  206. void __iomem *mmio_base;
  207. u16 cached_hctl;
  208. };
  209. struct inic_port_priv {
  210. struct inic_pkt *pkt;
  211. dma_addr_t pkt_dma;
  212. u32 *cpb_tbl;
  213. dma_addr_t cpb_tbl_dma;
  214. };
  215. static struct scsi_host_template inic_sht = {
  216. ATA_BASE_SHT(DRV_NAME),
  217. .sg_tablesize = LIBATA_MAX_PRD, /* maybe it can be larger? */
  218. /*
  219. * This controller is braindamaged. dma_boundary is 0xffff like others
  220. * but it will lock up the whole machine HARD if 65536 byte PRD entry
  221. * is fed. Reduce maximum segment size.
  222. */
  223. .dma_boundary = INIC_DMA_BOUNDARY,
  224. .max_segment_size = 65536 - 512,
  225. };
  226. static const int scr_map[] = {
  227. [SCR_STATUS] = 0,
  228. [SCR_ERROR] = 1,
  229. [SCR_CONTROL] = 2,
  230. };
  231. static void __iomem *inic_port_base(struct ata_port *ap)
  232. {
  233. struct inic_host_priv *hpriv = ap->host->private_data;
  234. return hpriv->mmio_base + ap->port_no * PORT_SIZE;
  235. }
  236. static void inic_reset_port(void __iomem *port_base)
  237. {
  238. void __iomem *idma_ctl = port_base + PORT_IDMA_CTL;
  239. /* stop IDMA engine */
  240. readw(idma_ctl); /* flush */
  241. msleep(1);
  242. /* mask IRQ and assert reset */
  243. writew(IDMA_CTL_RST_IDMA, idma_ctl);
  244. readw(idma_ctl); /* flush */
  245. msleep(1);
  246. /* release reset */
  247. writew(0, idma_ctl);
  248. /* clear irq */
  249. writeb(0xff, port_base + PORT_IRQ_STAT);
  250. }
  251. static int inic_scr_read(struct ata_link *link, unsigned sc_reg, u32 *val)
  252. {
  253. void __iomem *scr_addr = inic_port_base(link->ap) + PORT_SCR;
  254. if (unlikely(sc_reg >= ARRAY_SIZE(scr_map)))
  255. return -EINVAL;
  256. *val = readl(scr_addr + scr_map[sc_reg] * 4);
  257. /* this controller has stuck DIAG.N, ignore it */
  258. if (sc_reg == SCR_ERROR)
  259. *val &= ~SERR_PHYRDY_CHG;
  260. return 0;
  261. }
  262. static int inic_scr_write(struct ata_link *link, unsigned sc_reg, u32 val)
  263. {
  264. void __iomem *scr_addr = inic_port_base(link->ap) + PORT_SCR;
  265. if (unlikely(sc_reg >= ARRAY_SIZE(scr_map)))
  266. return -EINVAL;
  267. writel(val, scr_addr + scr_map[sc_reg] * 4);
  268. return 0;
  269. }
  270. static void inic_stop_idma(struct ata_port *ap)
  271. {
  272. void __iomem *port_base = inic_port_base(ap);
  273. readb(port_base + PORT_RPQ_FIFO);
  274. readb(port_base + PORT_RPQ_CNT);
  275. writew(0, port_base + PORT_IDMA_CTL);
  276. }
  277. static void inic_host_err_intr(struct ata_port *ap, u8 irq_stat, u16 idma_stat)
  278. {
  279. struct ata_eh_info *ehi = &ap->link.eh_info;
  280. struct inic_port_priv *pp = ap->private_data;
  281. struct inic_cpb *cpb = &pp->pkt->cpb;
  282. bool freeze = false;
  283. ata_ehi_clear_desc(ehi);
  284. ata_ehi_push_desc(ehi, "irq_stat=0x%x idma_stat=0x%x",
  285. irq_stat, idma_stat);
  286. inic_stop_idma(ap);
  287. if (irq_stat & (PIRQ_OFFLINE | PIRQ_ONLINE)) {
  288. ata_ehi_push_desc(ehi, "hotplug");
  289. ata_ehi_hotplugged(ehi);
  290. freeze = true;
  291. }
  292. if (idma_stat & IDMA_STAT_PERR) {
  293. ata_ehi_push_desc(ehi, "PCI error");
  294. freeze = true;
  295. }
  296. if (idma_stat & IDMA_STAT_CPBERR) {
  297. ata_ehi_push_desc(ehi, "CPB error");
  298. if (cpb->resp_flags & CPB_RESP_IGNORED) {
  299. __ata_ehi_push_desc(ehi, " ignored");
  300. ehi->err_mask |= AC_ERR_INVALID;
  301. freeze = true;
  302. }
  303. if (cpb->resp_flags & CPB_RESP_ATA_ERR)
  304. ehi->err_mask |= AC_ERR_DEV;
  305. if (cpb->resp_flags & CPB_RESP_SPURIOUS) {
  306. __ata_ehi_push_desc(ehi, " spurious-intr");
  307. ehi->err_mask |= AC_ERR_HSM;
  308. freeze = true;
  309. }
  310. if (cpb->resp_flags &
  311. (CPB_RESP_UNDERFLOW | CPB_RESP_OVERFLOW)) {
  312. __ata_ehi_push_desc(ehi, " data-over/underflow");
  313. ehi->err_mask |= AC_ERR_HSM;
  314. freeze = true;
  315. }
  316. }
  317. if (freeze)
  318. ata_port_freeze(ap);
  319. else
  320. ata_port_abort(ap);
  321. }
  322. static void inic_host_intr(struct ata_port *ap)
  323. {
  324. void __iomem *port_base = inic_port_base(ap);
  325. struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
  326. u8 irq_stat;
  327. u16 idma_stat;
  328. /* read and clear IRQ status */
  329. irq_stat = readb(port_base + PORT_IRQ_STAT);
  330. writeb(irq_stat, port_base + PORT_IRQ_STAT);
  331. idma_stat = readw(port_base + PORT_IDMA_STAT);
  332. if (unlikely((irq_stat & PIRQ_ERR) || (idma_stat & IDMA_STAT_ERR)))
  333. inic_host_err_intr(ap, irq_stat, idma_stat);
  334. if (unlikely(!qc))
  335. goto spurious;
  336. if (likely(idma_stat & IDMA_STAT_DONE)) {
  337. inic_stop_idma(ap);
  338. /* Depending on circumstances, device error
  339. * isn't reported by IDMA, check it explicitly.
  340. */
  341. if (unlikely(readb(port_base + PORT_TF_COMMAND) &
  342. (ATA_DF | ATA_ERR)))
  343. qc->err_mask |= AC_ERR_DEV;
  344. ata_qc_complete(qc);
  345. return;
  346. }
  347. spurious:
  348. ata_port_warn(ap, "unhandled interrupt: cmd=0x%x irq_stat=0x%x idma_stat=0x%x\n",
  349. qc ? qc->tf.command : 0xff, irq_stat, idma_stat);
  350. }
  351. static irqreturn_t inic_interrupt(int irq, void *dev_instance)
  352. {
  353. struct ata_host *host = dev_instance;
  354. struct inic_host_priv *hpriv = host->private_data;
  355. u16 host_irq_stat;
  356. int i, handled = 0;
  357. host_irq_stat = readw(hpriv->mmio_base + HOST_IRQ_STAT);
  358. if (unlikely(!(host_irq_stat & HIRQ_GLOBAL)))
  359. goto out;
  360. spin_lock(&host->lock);
  361. for (i = 0; i < NR_PORTS; i++)
  362. if (host_irq_stat & (HIRQ_PORT0 << i)) {
  363. inic_host_intr(host->ports[i]);
  364. handled++;
  365. }
  366. spin_unlock(&host->lock);
  367. out:
  368. return IRQ_RETVAL(handled);
  369. }
  370. static int inic_check_atapi_dma(struct ata_queued_cmd *qc)
  371. {
  372. /* For some reason ATAPI_PROT_DMA doesn't work for some
  373. * commands including writes and other misc ops. Use PIO
  374. * protocol instead, which BTW is driven by the DMA engine
  375. * anyway, so it shouldn't make much difference for native
  376. * SATA devices.
  377. */
  378. if (atapi_cmd_type(qc->cdb[0]) == READ)
  379. return 0;
  380. return 1;
  381. }
  382. static void inic_fill_sg(struct inic_prd *prd, struct ata_queued_cmd *qc)
  383. {
  384. struct scatterlist *sg;
  385. unsigned int si;
  386. u8 flags = 0;
  387. if (qc->tf.flags & ATA_TFLAG_WRITE)
  388. flags |= PRD_WRITE;
  389. if (ata_is_dma(qc->tf.protocol))
  390. flags |= PRD_DMA;
  391. for_each_sg(qc->sg, sg, qc->n_elem, si) {
  392. prd->mad = cpu_to_le32(sg_dma_address(sg));
  393. prd->len = cpu_to_le16(sg_dma_len(sg));
  394. prd->flags = flags;
  395. prd++;
  396. }
  397. WARN_ON(!si);
  398. prd[-1].flags |= PRD_END;
  399. }
  400. static enum ata_completion_errors inic_qc_prep(struct ata_queued_cmd *qc)
  401. {
  402. struct inic_port_priv *pp = qc->ap->private_data;
  403. struct inic_pkt *pkt = pp->pkt;
  404. struct inic_cpb *cpb = &pkt->cpb;
  405. struct inic_prd *prd = pkt->prd;
  406. bool is_atapi = ata_is_atapi(qc->tf.protocol);
  407. bool is_data = ata_is_data(qc->tf.protocol);
  408. unsigned int cdb_len = 0;
  409. VPRINTK("ENTER\n");
  410. if (is_atapi)
  411. cdb_len = qc->dev->cdb_len;
  412. /* prepare packet, based on initio driver */
  413. memset(pkt, 0, sizeof(struct inic_pkt));
  414. cpb->ctl_flags = CPB_CTL_VALID | CPB_CTL_IEN;
  415. if (is_atapi || is_data)
  416. cpb->ctl_flags |= CPB_CTL_DATA;
  417. cpb->len = cpu_to_le32(qc->nbytes + cdb_len);
  418. cpb->prd = cpu_to_le32(pp->pkt_dma + offsetof(struct inic_pkt, prd));
  419. cpb->device = qc->tf.device;
  420. cpb->feature = qc->tf.feature;
  421. cpb->nsect = qc->tf.nsect;
  422. cpb->lbal = qc->tf.lbal;
  423. cpb->lbam = qc->tf.lbam;
  424. cpb->lbah = qc->tf.lbah;
  425. if (qc->tf.flags & ATA_TFLAG_LBA48) {
  426. cpb->hob_feature = qc->tf.hob_feature;
  427. cpb->hob_nsect = qc->tf.hob_nsect;
  428. cpb->hob_lbal = qc->tf.hob_lbal;
  429. cpb->hob_lbam = qc->tf.hob_lbam;
  430. cpb->hob_lbah = qc->tf.hob_lbah;
  431. }
  432. cpb->command = qc->tf.command;
  433. /* don't load ctl - dunno why. it's like that in the initio driver */
  434. /* setup PRD for CDB */
  435. if (is_atapi) {
  436. memcpy(pkt->cdb, qc->cdb, ATAPI_CDB_LEN);
  437. prd->mad = cpu_to_le32(pp->pkt_dma +
  438. offsetof(struct inic_pkt, cdb));
  439. prd->len = cpu_to_le16(cdb_len);
  440. prd->flags = PRD_CDB | PRD_WRITE;
  441. if (!is_data)
  442. prd->flags |= PRD_END;
  443. prd++;
  444. }
  445. /* setup sg table */
  446. if (is_data)
  447. inic_fill_sg(prd, qc);
  448. pp->cpb_tbl[0] = pp->pkt_dma;
  449. return AC_ERR_OK;
  450. }
  451. static unsigned int inic_qc_issue(struct ata_queued_cmd *qc)
  452. {
  453. struct ata_port *ap = qc->ap;
  454. void __iomem *port_base = inic_port_base(ap);
  455. /* fire up the ADMA engine */
  456. writew(HCTL_FTHD0 | HCTL_LEDEN, port_base + HOST_CTL);
  457. writew(IDMA_CTL_GO, port_base + PORT_IDMA_CTL);
  458. writeb(0, port_base + PORT_CPB_PTQFIFO);
  459. return 0;
  460. }
  461. static void inic_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
  462. {
  463. void __iomem *port_base = inic_port_base(ap);
  464. tf->feature = readb(port_base + PORT_TF_FEATURE);
  465. tf->nsect = readb(port_base + PORT_TF_NSECT);
  466. tf->lbal = readb(port_base + PORT_TF_LBAL);
  467. tf->lbam = readb(port_base + PORT_TF_LBAM);
  468. tf->lbah = readb(port_base + PORT_TF_LBAH);
  469. tf->device = readb(port_base + PORT_TF_DEVICE);
  470. tf->command = readb(port_base + PORT_TF_COMMAND);
  471. }
  472. static bool inic_qc_fill_rtf(struct ata_queued_cmd *qc)
  473. {
  474. struct ata_taskfile *rtf = &qc->result_tf;
  475. struct ata_taskfile tf;
  476. /* FIXME: Except for status and error, result TF access
  477. * doesn't work. I tried reading from BAR0/2, CPB and BAR5.
  478. * None works regardless of which command interface is used.
  479. * For now return true iff status indicates device error.
  480. * This means that we're reporting bogus sector for RW
  481. * failures. Eeekk....
  482. */
  483. inic_tf_read(qc->ap, &tf);
  484. if (!(tf.command & ATA_ERR))
  485. return false;
  486. rtf->command = tf.command;
  487. rtf->feature = tf.feature;
  488. return true;
  489. }
  490. static void inic_freeze(struct ata_port *ap)
  491. {
  492. void __iomem *port_base = inic_port_base(ap);
  493. writeb(PIRQ_MASK_FREEZE, port_base + PORT_IRQ_MASK);
  494. writeb(0xff, port_base + PORT_IRQ_STAT);
  495. }
  496. static void inic_thaw(struct ata_port *ap)
  497. {
  498. void __iomem *port_base = inic_port_base(ap);
  499. writeb(0xff, port_base + PORT_IRQ_STAT);
  500. writeb(PIRQ_MASK_DEFAULT, port_base + PORT_IRQ_MASK);
  501. }
  502. static int inic_check_ready(struct ata_link *link)
  503. {
  504. void __iomem *port_base = inic_port_base(link->ap);
  505. return ata_check_ready(readb(port_base + PORT_TF_COMMAND));
  506. }
  507. /*
  508. * SRST and SControl hardreset don't give valid signature on this
  509. * controller. Only controller specific hardreset mechanism works.
  510. */
  511. static int inic_hardreset(struct ata_link *link, unsigned int *class,
  512. unsigned long deadline)
  513. {
  514. struct ata_port *ap = link->ap;
  515. void __iomem *port_base = inic_port_base(ap);
  516. void __iomem *idma_ctl = port_base + PORT_IDMA_CTL;
  517. const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
  518. int rc;
  519. /* hammer it into sane state */
  520. inic_reset_port(port_base);
  521. writew(IDMA_CTL_RST_ATA, idma_ctl);
  522. readw(idma_ctl); /* flush */
  523. ata_msleep(ap, 1);
  524. writew(0, idma_ctl);
  525. rc = sata_link_resume(link, timing, deadline);
  526. if (rc) {
  527. ata_link_warn(link,
  528. "failed to resume link after reset (errno=%d)\n",
  529. rc);
  530. return rc;
  531. }
  532. *class = ATA_DEV_NONE;
  533. if (ata_link_online(link)) {
  534. struct ata_taskfile tf;
  535. /* wait for link to become ready */
  536. rc = ata_wait_after_reset(link, deadline, inic_check_ready);
  537. /* link occupied, -ENODEV too is an error */
  538. if (rc) {
  539. ata_link_warn(link,
  540. "device not ready after hardreset (errno=%d)\n",
  541. rc);
  542. return rc;
  543. }
  544. inic_tf_read(ap, &tf);
  545. *class = ata_dev_classify(&tf);
  546. }
  547. return 0;
  548. }
  549. static void inic_error_handler(struct ata_port *ap)
  550. {
  551. void __iomem *port_base = inic_port_base(ap);
  552. inic_reset_port(port_base);
  553. ata_std_error_handler(ap);
  554. }
  555. static void inic_post_internal_cmd(struct ata_queued_cmd *qc)
  556. {
  557. /* make DMA engine forget about the failed command */
  558. if (qc->flags & ATA_QCFLAG_FAILED)
  559. inic_reset_port(inic_port_base(qc->ap));
  560. }
  561. static void init_port(struct ata_port *ap)
  562. {
  563. void __iomem *port_base = inic_port_base(ap);
  564. struct inic_port_priv *pp = ap->private_data;
  565. /* clear packet and CPB table */
  566. memset(pp->pkt, 0, sizeof(struct inic_pkt));
  567. memset(pp->cpb_tbl, 0, IDMA_CPB_TBL_SIZE);
  568. /* setup CPB lookup table addresses */
  569. writel(pp->cpb_tbl_dma, port_base + PORT_CPB_CPBLAR);
  570. }
  571. static int inic_port_resume(struct ata_port *ap)
  572. {
  573. init_port(ap);
  574. return 0;
  575. }
  576. static int inic_port_start(struct ata_port *ap)
  577. {
  578. struct device *dev = ap->host->dev;
  579. struct inic_port_priv *pp;
  580. /* alloc and initialize private data */
  581. pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
  582. if (!pp)
  583. return -ENOMEM;
  584. ap->private_data = pp;
  585. /* Alloc resources */
  586. pp->pkt = dmam_alloc_coherent(dev, sizeof(struct inic_pkt),
  587. &pp->pkt_dma, GFP_KERNEL);
  588. if (!pp->pkt)
  589. return -ENOMEM;
  590. pp->cpb_tbl = dmam_alloc_coherent(dev, IDMA_CPB_TBL_SIZE,
  591. &pp->cpb_tbl_dma, GFP_KERNEL);
  592. if (!pp->cpb_tbl)
  593. return -ENOMEM;
  594. init_port(ap);
  595. return 0;
  596. }
  597. static struct ata_port_operations inic_port_ops = {
  598. .inherits = &sata_port_ops,
  599. .check_atapi_dma = inic_check_atapi_dma,
  600. .qc_prep = inic_qc_prep,
  601. .qc_issue = inic_qc_issue,
  602. .qc_fill_rtf = inic_qc_fill_rtf,
  603. .freeze = inic_freeze,
  604. .thaw = inic_thaw,
  605. .hardreset = inic_hardreset,
  606. .error_handler = inic_error_handler,
  607. .post_internal_cmd = inic_post_internal_cmd,
  608. .scr_read = inic_scr_read,
  609. .scr_write = inic_scr_write,
  610. .port_resume = inic_port_resume,
  611. .port_start = inic_port_start,
  612. };
  613. static const struct ata_port_info inic_port_info = {
  614. .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
  615. .pio_mask = ATA_PIO4,
  616. .mwdma_mask = ATA_MWDMA2,
  617. .udma_mask = ATA_UDMA6,
  618. .port_ops = &inic_port_ops
  619. };
  620. static int init_controller(void __iomem *mmio_base, u16 hctl)
  621. {
  622. int i;
  623. u16 val;
  624. hctl &= ~HCTL_KNOWN_BITS;
  625. /* Soft reset whole controller. Spec says reset duration is 3
  626. * PCI clocks, be generous and give it 10ms.
  627. */
  628. writew(hctl | HCTL_SOFTRST, mmio_base + HOST_CTL);
  629. readw(mmio_base + HOST_CTL); /* flush */
  630. for (i = 0; i < 10; i++) {
  631. msleep(1);
  632. val = readw(mmio_base + HOST_CTL);
  633. if (!(val & HCTL_SOFTRST))
  634. break;
  635. }
  636. if (val & HCTL_SOFTRST)
  637. return -EIO;
  638. /* mask all interrupts and reset ports */
  639. for (i = 0; i < NR_PORTS; i++) {
  640. void __iomem *port_base = mmio_base + i * PORT_SIZE;
  641. writeb(0xff, port_base + PORT_IRQ_MASK);
  642. inic_reset_port(port_base);
  643. }
  644. /* port IRQ is masked now, unmask global IRQ */
  645. writew(hctl & ~HCTL_IRQOFF, mmio_base + HOST_CTL);
  646. val = readw(mmio_base + HOST_IRQ_MASK);
  647. val &= ~(HIRQ_PORT0 | HIRQ_PORT1);
  648. writew(val, mmio_base + HOST_IRQ_MASK);
  649. return 0;
  650. }
  651. #ifdef CONFIG_PM_SLEEP
  652. static int inic_pci_device_resume(struct pci_dev *pdev)
  653. {
  654. struct ata_host *host = pci_get_drvdata(pdev);
  655. struct inic_host_priv *hpriv = host->private_data;
  656. int rc;
  657. rc = ata_pci_device_do_resume(pdev);
  658. if (rc)
  659. return rc;
  660. if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
  661. rc = init_controller(hpriv->mmio_base, hpriv->cached_hctl);
  662. if (rc)
  663. return rc;
  664. }
  665. ata_host_resume(host);
  666. return 0;
  667. }
  668. #endif
  669. static int inic_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
  670. {
  671. const struct ata_port_info *ppi[] = { &inic_port_info, NULL };
  672. struct ata_host *host;
  673. struct inic_host_priv *hpriv;
  674. void __iomem * const *iomap;
  675. int mmio_bar;
  676. int i, rc;
  677. ata_print_version_once(&pdev->dev, DRV_VERSION);
  678. dev_alert(&pdev->dev, "inic162x support is broken with common data corruption issues and will be disabled by default, contact linux-ide@vger.kernel.org if in production use\n");
  679. /* alloc host */
  680. host = ata_host_alloc_pinfo(&pdev->dev, ppi, NR_PORTS);
  681. hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
  682. if (!host || !hpriv)
  683. return -ENOMEM;
  684. host->private_data = hpriv;
  685. /* Acquire resources and fill host. Note that PCI and cardbus
  686. * use different BARs.
  687. */
  688. rc = pcim_enable_device(pdev);
  689. if (rc)
  690. return rc;
  691. if (pci_resource_flags(pdev, MMIO_BAR_PCI) & IORESOURCE_MEM)
  692. mmio_bar = MMIO_BAR_PCI;
  693. else
  694. mmio_bar = MMIO_BAR_CARDBUS;
  695. rc = pcim_iomap_regions(pdev, 1 << mmio_bar, DRV_NAME);
  696. if (rc)
  697. return rc;
  698. host->iomap = iomap = pcim_iomap_table(pdev);
  699. hpriv->mmio_base = iomap[mmio_bar];
  700. hpriv->cached_hctl = readw(hpriv->mmio_base + HOST_CTL);
  701. for (i = 0; i < NR_PORTS; i++) {
  702. struct ata_port *ap = host->ports[i];
  703. ata_port_pbar_desc(ap, mmio_bar, -1, "mmio");
  704. ata_port_pbar_desc(ap, mmio_bar, i * PORT_SIZE, "port");
  705. }
  706. /* Set dma_mask. This devices doesn't support 64bit addressing. */
  707. rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
  708. if (rc) {
  709. dev_err(&pdev->dev, "32-bit DMA enable failed\n");
  710. return rc;
  711. }
  712. rc = init_controller(hpriv->mmio_base, hpriv->cached_hctl);
  713. if (rc) {
  714. dev_err(&pdev->dev, "failed to initialize controller\n");
  715. return rc;
  716. }
  717. pci_set_master(pdev);
  718. return ata_host_activate(host, pdev->irq, inic_interrupt, IRQF_SHARED,
  719. &inic_sht);
  720. }
  721. static const struct pci_device_id inic_pci_tbl[] = {
  722. { PCI_VDEVICE(INIT, 0x1622), },
  723. { },
  724. };
  725. static struct pci_driver inic_pci_driver = {
  726. .name = DRV_NAME,
  727. .id_table = inic_pci_tbl,
  728. #ifdef CONFIG_PM_SLEEP
  729. .suspend = ata_pci_device_suspend,
  730. .resume = inic_pci_device_resume,
  731. #endif
  732. .probe = inic_init_one,
  733. .remove = ata_pci_remove_one,
  734. };
  735. module_pci_driver(inic_pci_driver);
  736. MODULE_AUTHOR("Tejun Heo");
  737. MODULE_DESCRIPTION("low-level driver for Initio 162x SATA");
  738. MODULE_LICENSE("GPL v2");
  739. MODULE_DEVICE_TABLE(pci, inic_pci_tbl);
  740. MODULE_VERSION(DRV_VERSION);