pata_sis.c 24 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * pata_sis.c - SiS ATA driver
  4. *
  5. * (C) 2005 Red Hat
  6. * (C) 2007,2009 Bartlomiej Zolnierkiewicz
  7. *
  8. * Based upon linux/drivers/ide/pci/sis5513.c
  9. * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org>
  10. * Copyright (C) 2002 Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer
  11. * Copyright (C) 2003 Vojtech Pavlik <vojtech@suse.cz>
  12. * SiS Taiwan : for direct support and hardware.
  13. * Daniela Engert : for initial ATA100 advices and numerous others.
  14. * John Fremlin, Manfred Spraul, Dave Morgan, Peter Kjellerstedt :
  15. * for checking code correctness, providing patches.
  16. * Original tests and design on the SiS620 chipset.
  17. * ATA100 tests and design on the SiS735 chipset.
  18. * ATA16/33 support from specs
  19. * ATA133 support for SiS961/962 by L.C. Chang <lcchang@sis.com.tw>
  20. *
  21. *
  22. * TODO
  23. * Check MWDMA on drives that don't support MWDMA speed pio cycles ?
  24. * More Testing
  25. */
  26. #include <linux/kernel.h>
  27. #include <linux/module.h>
  28. #include <linux/pci.h>
  29. #include <linux/blkdev.h>
  30. #include <linux/delay.h>
  31. #include <linux/device.h>
  32. #include <scsi/scsi_host.h>
  33. #include <linux/libata.h>
  34. #include <linux/ata.h>
  35. #include "sis.h"
  36. #define DRV_NAME "pata_sis"
  37. #define DRV_VERSION "0.5.2"
  38. struct sis_chipset {
  39. u16 device; /* PCI host ID */
  40. const struct ata_port_info *info; /* Info block */
  41. /* Probably add family, cable detect type etc here to clean
  42. up code later */
  43. };
  44. struct sis_laptop {
  45. u16 device;
  46. u16 subvendor;
  47. u16 subdevice;
  48. };
  49. static const struct sis_laptop sis_laptop[] = {
  50. /* devid, subvendor, subdev */
  51. { 0x5513, 0x1043, 0x1107 }, /* ASUS A6K */
  52. { 0x5513, 0x1734, 0x105F }, /* FSC Amilo A1630 */
  53. { 0x5513, 0x1071, 0x8640 }, /* EasyNote K5305 */
  54. /* end marker */
  55. { 0, }
  56. };
  57. static int sis_short_ata40(struct pci_dev *dev)
  58. {
  59. const struct sis_laptop *lap = &sis_laptop[0];
  60. while (lap->device) {
  61. if (lap->device == dev->device &&
  62. lap->subvendor == dev->subsystem_vendor &&
  63. lap->subdevice == dev->subsystem_device)
  64. return 1;
  65. lap++;
  66. }
  67. return 0;
  68. }
  69. /**
  70. * sis_old_port_base - return PCI configuration base for dev
  71. * @adev: device
  72. *
  73. * Returns the base of the PCI configuration registers for this port
  74. * number.
  75. */
  76. static int sis_old_port_base(struct ata_device *adev)
  77. {
  78. return 0x40 + (4 * adev->link->ap->port_no) + (2 * adev->devno);
  79. }
  80. /**
  81. * sis_port_base - return PCI configuration base for dev
  82. * @adev: device
  83. *
  84. * Returns the base of the PCI configuration registers for this port
  85. * number.
  86. */
  87. static int sis_port_base(struct ata_device *adev)
  88. {
  89. struct ata_port *ap = adev->link->ap;
  90. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  91. int port = 0x40;
  92. u32 reg54;
  93. /* If bit 30 is set then the registers are mapped at 0x70 not 0x40 */
  94. pci_read_config_dword(pdev, 0x54, &reg54);
  95. if (reg54 & 0x40000000)
  96. port = 0x70;
  97. return port + (8 * ap->port_no) + (4 * adev->devno);
  98. }
  99. /**
  100. * sis_133_cable_detect - check for 40/80 pin
  101. * @ap: Port
  102. * @deadline: deadline jiffies for the operation
  103. *
  104. * Perform cable detection for the later UDMA133 capable
  105. * SiS chipset.
  106. */
  107. static int sis_133_cable_detect(struct ata_port *ap)
  108. {
  109. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  110. u16 tmp;
  111. /* The top bit of this register is the cable detect bit */
  112. pci_read_config_word(pdev, 0x50 + 2 * ap->port_no, &tmp);
  113. if ((tmp & 0x8000) && !sis_short_ata40(pdev))
  114. return ATA_CBL_PATA40;
  115. return ATA_CBL_PATA80;
  116. }
  117. /**
  118. * sis_66_cable_detect - check for 40/80 pin
  119. * @ap: Port
  120. *
  121. * Perform cable detection on the UDMA66, UDMA100 and early UDMA133
  122. * SiS IDE controllers.
  123. */
  124. static int sis_66_cable_detect(struct ata_port *ap)
  125. {
  126. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  127. u8 tmp;
  128. /* Older chips keep cable detect in bits 4/5 of reg 0x48 */
  129. pci_read_config_byte(pdev, 0x48, &tmp);
  130. tmp >>= ap->port_no;
  131. if ((tmp & 0x10) && !sis_short_ata40(pdev))
  132. return ATA_CBL_PATA40;
  133. return ATA_CBL_PATA80;
  134. }
  135. /**
  136. * sis_pre_reset - probe begin
  137. * @link: ATA link
  138. * @deadline: deadline jiffies for the operation
  139. *
  140. * Set up cable type and use generic probe init
  141. */
  142. static int sis_pre_reset(struct ata_link *link, unsigned long deadline)
  143. {
  144. static const struct pci_bits sis_enable_bits[] = {
  145. { 0x4aU, 1U, 0x02UL, 0x02UL }, /* port 0 */
  146. { 0x4aU, 1U, 0x04UL, 0x04UL }, /* port 1 */
  147. };
  148. struct ata_port *ap = link->ap;
  149. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  150. if (!pci_test_config_bits(pdev, &sis_enable_bits[ap->port_no]))
  151. return -ENOENT;
  152. /* Clear the FIFO settings. We can't enable the FIFO until
  153. we know we are poking at a disk */
  154. pci_write_config_byte(pdev, 0x4B, 0);
  155. return ata_sff_prereset(link, deadline);
  156. }
  157. /**
  158. * sis_set_fifo - Set RWP fifo bits for this device
  159. * @ap: Port
  160. * @adev: Device
  161. *
  162. * SIS chipsets implement prefetch/postwrite bits for each device
  163. * on both channels. This functionality is not ATAPI compatible and
  164. * must be configured according to the class of device present
  165. */
  166. static void sis_set_fifo(struct ata_port *ap, struct ata_device *adev)
  167. {
  168. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  169. u8 fifoctrl;
  170. u8 mask = 0x11;
  171. mask <<= (2 * ap->port_no);
  172. mask <<= adev->devno;
  173. /* This holds various bits including the FIFO control */
  174. pci_read_config_byte(pdev, 0x4B, &fifoctrl);
  175. fifoctrl &= ~mask;
  176. /* Enable for ATA (disk) only */
  177. if (adev->class == ATA_DEV_ATA)
  178. fifoctrl |= mask;
  179. pci_write_config_byte(pdev, 0x4B, fifoctrl);
  180. }
  181. /**
  182. * sis_old_set_piomode - Initialize host controller PATA PIO timings
  183. * @ap: Port whose timings we are configuring
  184. * @adev: Device we are configuring for.
  185. *
  186. * Set PIO mode for device, in host controller PCI config space. This
  187. * function handles PIO set up for all chips that are pre ATA100 and
  188. * also early ATA100 devices.
  189. *
  190. * LOCKING:
  191. * None (inherited from caller).
  192. */
  193. static void sis_old_set_piomode (struct ata_port *ap, struct ata_device *adev)
  194. {
  195. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  196. int port = sis_old_port_base(adev);
  197. u8 t1, t2;
  198. int speed = adev->pio_mode - XFER_PIO_0;
  199. static const u8 active[] = { 0x00, 0x07, 0x04, 0x03, 0x01 };
  200. static const u8 recovery[] = { 0x00, 0x06, 0x04, 0x03, 0x03 };
  201. sis_set_fifo(ap, adev);
  202. pci_read_config_byte(pdev, port, &t1);
  203. pci_read_config_byte(pdev, port + 1, &t2);
  204. t1 &= ~0x0F; /* Clear active/recovery timings */
  205. t2 &= ~0x07;
  206. t1 |= active[speed];
  207. t2 |= recovery[speed];
  208. pci_write_config_byte(pdev, port, t1);
  209. pci_write_config_byte(pdev, port + 1, t2);
  210. }
  211. /**
  212. * sis_100_set_piomode - Initialize host controller PATA PIO timings
  213. * @ap: Port whose timings we are configuring
  214. * @adev: Device we are configuring for.
  215. *
  216. * Set PIO mode for device, in host controller PCI config space. This
  217. * function handles PIO set up for ATA100 devices and early ATA133.
  218. *
  219. * LOCKING:
  220. * None (inherited from caller).
  221. */
  222. static void sis_100_set_piomode (struct ata_port *ap, struct ata_device *adev)
  223. {
  224. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  225. int port = sis_old_port_base(adev);
  226. int speed = adev->pio_mode - XFER_PIO_0;
  227. static const u8 actrec[] = { 0x00, 0x67, 0x44, 0x33, 0x31 };
  228. sis_set_fifo(ap, adev);
  229. pci_write_config_byte(pdev, port, actrec[speed]);
  230. }
  231. /**
  232. * sis_133_set_piomode - Initialize host controller PATA PIO timings
  233. * @ap: Port whose timings we are configuring
  234. * @adev: Device we are configuring for.
  235. *
  236. * Set PIO mode for device, in host controller PCI config space. This
  237. * function handles PIO set up for the later ATA133 devices.
  238. *
  239. * LOCKING:
  240. * None (inherited from caller).
  241. */
  242. static void sis_133_set_piomode (struct ata_port *ap, struct ata_device *adev)
  243. {
  244. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  245. int port;
  246. u32 t1;
  247. int speed = adev->pio_mode - XFER_PIO_0;
  248. static const u32 timing133[] = {
  249. 0x28269000, /* Recovery << 24 | Act << 16 | Ini << 12 */
  250. 0x0C266000,
  251. 0x04263000,
  252. 0x0C0A3000,
  253. 0x05093000
  254. };
  255. static const u32 timing100[] = {
  256. 0x1E1C6000, /* Recovery << 24 | Act << 16 | Ini << 12 */
  257. 0x091C4000,
  258. 0x031C2000,
  259. 0x09072000,
  260. 0x04062000
  261. };
  262. sis_set_fifo(ap, adev);
  263. port = sis_port_base(adev);
  264. pci_read_config_dword(pdev, port, &t1);
  265. t1 &= 0xC0C00FFF; /* Mask out timing */
  266. if (t1 & 0x08) /* 100 or 133 ? */
  267. t1 |= timing133[speed];
  268. else
  269. t1 |= timing100[speed];
  270. pci_write_config_byte(pdev, port, t1);
  271. }
  272. /**
  273. * sis_old_set_dmamode - Initialize host controller PATA DMA timings
  274. * @ap: Port whose timings we are configuring
  275. * @adev: Device to program
  276. *
  277. * Set UDMA/MWDMA mode for device, in host controller PCI config space.
  278. * Handles pre UDMA and UDMA33 devices. Supports MWDMA as well unlike
  279. * the old ide/pci driver.
  280. *
  281. * LOCKING:
  282. * None (inherited from caller).
  283. */
  284. static void sis_old_set_dmamode (struct ata_port *ap, struct ata_device *adev)
  285. {
  286. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  287. int speed = adev->dma_mode - XFER_MW_DMA_0;
  288. int drive_pci = sis_old_port_base(adev);
  289. u16 timing;
  290. static const u16 mwdma_bits[] = { 0x008, 0x302, 0x301 };
  291. static const u16 udma_bits[] = { 0xE000, 0xC000, 0xA000 };
  292. pci_read_config_word(pdev, drive_pci, &timing);
  293. if (adev->dma_mode < XFER_UDMA_0) {
  294. /* bits 3-0 hold recovery timing bits 8-10 active timing and
  295. the higher bits are dependent on the device */
  296. timing &= ~0x870F;
  297. timing |= mwdma_bits[speed];
  298. } else {
  299. /* Bit 15 is UDMA on/off, bit 13-14 are cycle time */
  300. speed = adev->dma_mode - XFER_UDMA_0;
  301. timing &= ~0x6000;
  302. timing |= udma_bits[speed];
  303. }
  304. pci_write_config_word(pdev, drive_pci, timing);
  305. }
  306. /**
  307. * sis_66_set_dmamode - Initialize host controller PATA DMA timings
  308. * @ap: Port whose timings we are configuring
  309. * @adev: Device to program
  310. *
  311. * Set UDMA/MWDMA mode for device, in host controller PCI config space.
  312. * Handles UDMA66 and early UDMA100 devices. Supports MWDMA as well unlike
  313. * the old ide/pci driver.
  314. *
  315. * LOCKING:
  316. * None (inherited from caller).
  317. */
  318. static void sis_66_set_dmamode (struct ata_port *ap, struct ata_device *adev)
  319. {
  320. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  321. int speed = adev->dma_mode - XFER_MW_DMA_0;
  322. int drive_pci = sis_old_port_base(adev);
  323. u16 timing;
  324. /* MWDMA 0-2 and UDMA 0-5 */
  325. static const u16 mwdma_bits[] = { 0x008, 0x302, 0x301 };
  326. static const u16 udma_bits[] = { 0xF000, 0xD000, 0xB000, 0xA000, 0x9000, 0x8000 };
  327. pci_read_config_word(pdev, drive_pci, &timing);
  328. if (adev->dma_mode < XFER_UDMA_0) {
  329. /* bits 3-0 hold recovery timing bits 8-10 active timing and
  330. the higher bits are dependent on the device, bit 15 udma */
  331. timing &= ~0x870F;
  332. timing |= mwdma_bits[speed];
  333. } else {
  334. /* Bit 15 is UDMA on/off, bit 12-14 are cycle time */
  335. speed = adev->dma_mode - XFER_UDMA_0;
  336. timing &= ~0xF000;
  337. timing |= udma_bits[speed];
  338. }
  339. pci_write_config_word(pdev, drive_pci, timing);
  340. }
  341. /**
  342. * sis_100_set_dmamode - Initialize host controller PATA DMA timings
  343. * @ap: Port whose timings we are configuring
  344. * @adev: Device to program
  345. *
  346. * Set UDMA/MWDMA mode for device, in host controller PCI config space.
  347. * Handles UDMA66 and early UDMA100 devices.
  348. *
  349. * LOCKING:
  350. * None (inherited from caller).
  351. */
  352. static void sis_100_set_dmamode (struct ata_port *ap, struct ata_device *adev)
  353. {
  354. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  355. int speed = adev->dma_mode - XFER_MW_DMA_0;
  356. int drive_pci = sis_old_port_base(adev);
  357. u8 timing;
  358. static const u8 udma_bits[] = { 0x8B, 0x87, 0x85, 0x83, 0x82, 0x81};
  359. pci_read_config_byte(pdev, drive_pci + 1, &timing);
  360. if (adev->dma_mode < XFER_UDMA_0) {
  361. /* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */
  362. } else {
  363. /* Bit 7 is UDMA on/off, bit 0-3 are cycle time */
  364. speed = adev->dma_mode - XFER_UDMA_0;
  365. timing &= ~0x8F;
  366. timing |= udma_bits[speed];
  367. }
  368. pci_write_config_byte(pdev, drive_pci + 1, timing);
  369. }
  370. /**
  371. * sis_133_early_set_dmamode - Initialize host controller PATA DMA timings
  372. * @ap: Port whose timings we are configuring
  373. * @adev: Device to program
  374. *
  375. * Set UDMA/MWDMA mode for device, in host controller PCI config space.
  376. * Handles early SiS 961 bridges.
  377. *
  378. * LOCKING:
  379. * None (inherited from caller).
  380. */
  381. static void sis_133_early_set_dmamode (struct ata_port *ap, struct ata_device *adev)
  382. {
  383. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  384. int speed = adev->dma_mode - XFER_MW_DMA_0;
  385. int drive_pci = sis_old_port_base(adev);
  386. u8 timing;
  387. /* Low 4 bits are timing */
  388. static const u8 udma_bits[] = { 0x8F, 0x8A, 0x87, 0x85, 0x83, 0x82, 0x81};
  389. pci_read_config_byte(pdev, drive_pci + 1, &timing);
  390. if (adev->dma_mode < XFER_UDMA_0) {
  391. /* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */
  392. } else {
  393. /* Bit 7 is UDMA on/off, bit 0-3 are cycle time */
  394. speed = adev->dma_mode - XFER_UDMA_0;
  395. timing &= ~0x8F;
  396. timing |= udma_bits[speed];
  397. }
  398. pci_write_config_byte(pdev, drive_pci + 1, timing);
  399. }
  400. /**
  401. * sis_133_set_dmamode - Initialize host controller PATA DMA timings
  402. * @ap: Port whose timings we are configuring
  403. * @adev: Device to program
  404. *
  405. * Set UDMA/MWDMA mode for device, in host controller PCI config space.
  406. *
  407. * LOCKING:
  408. * None (inherited from caller).
  409. */
  410. static void sis_133_set_dmamode (struct ata_port *ap, struct ata_device *adev)
  411. {
  412. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  413. int port;
  414. u32 t1;
  415. port = sis_port_base(adev);
  416. pci_read_config_dword(pdev, port, &t1);
  417. if (adev->dma_mode < XFER_UDMA_0) {
  418. /* Recovery << 24 | Act << 16 | Ini << 12, like PIO modes */
  419. static const u32 timing_u100[] = { 0x19154000, 0x06072000, 0x04062000 };
  420. static const u32 timing_u133[] = { 0x221C6000, 0x0C0A3000, 0x05093000 };
  421. int speed = adev->dma_mode - XFER_MW_DMA_0;
  422. t1 &= 0xC0C00FFF;
  423. /* disable UDMA */
  424. t1 &= ~0x00000004;
  425. if (t1 & 0x08)
  426. t1 |= timing_u133[speed];
  427. else
  428. t1 |= timing_u100[speed];
  429. } else {
  430. /* bits 4- cycle time 8 - cvs time */
  431. static const u32 timing_u100[] = { 0x6B0, 0x470, 0x350, 0x140, 0x120, 0x110, 0x000 };
  432. static const u32 timing_u133[] = { 0x9F0, 0x6A0, 0x470, 0x250, 0x230, 0x220, 0x210 };
  433. int speed = adev->dma_mode - XFER_UDMA_0;
  434. t1 &= ~0x00000FF0;
  435. /* enable UDMA */
  436. t1 |= 0x00000004;
  437. if (t1 & 0x08)
  438. t1 |= timing_u133[speed];
  439. else
  440. t1 |= timing_u100[speed];
  441. }
  442. pci_write_config_dword(pdev, port, t1);
  443. }
  444. /**
  445. * sis_133_mode_filter - mode selection filter
  446. * @adev: ATA device
  447. *
  448. * Block UDMA6 on devices that do not support it.
  449. */
  450. static unsigned long sis_133_mode_filter(struct ata_device *adev, unsigned long mask)
  451. {
  452. struct ata_port *ap = adev->link->ap;
  453. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  454. int port = sis_port_base(adev);
  455. u32 t1;
  456. pci_read_config_dword(pdev, port, &t1);
  457. /* if ATA133 is disabled, mask it out */
  458. if (!(t1 & 0x08))
  459. mask &= ~(0xC0 << ATA_SHIFT_UDMA);
  460. return mask;
  461. }
  462. static struct scsi_host_template sis_sht = {
  463. ATA_BMDMA_SHT(DRV_NAME),
  464. };
  465. static struct ata_port_operations sis_133_for_sata_ops = {
  466. .inherits = &ata_bmdma_port_ops,
  467. .set_piomode = sis_133_set_piomode,
  468. .set_dmamode = sis_133_set_dmamode,
  469. .cable_detect = sis_133_cable_detect,
  470. };
  471. static struct ata_port_operations sis_base_ops = {
  472. .inherits = &ata_bmdma_port_ops,
  473. .prereset = sis_pre_reset,
  474. };
  475. static struct ata_port_operations sis_133_ops = {
  476. .inherits = &sis_base_ops,
  477. .set_piomode = sis_133_set_piomode,
  478. .set_dmamode = sis_133_set_dmamode,
  479. .cable_detect = sis_133_cable_detect,
  480. .mode_filter = sis_133_mode_filter,
  481. };
  482. static struct ata_port_operations sis_133_early_ops = {
  483. .inherits = &sis_base_ops,
  484. .set_piomode = sis_100_set_piomode,
  485. .set_dmamode = sis_133_early_set_dmamode,
  486. .cable_detect = sis_66_cable_detect,
  487. };
  488. static struct ata_port_operations sis_100_ops = {
  489. .inherits = &sis_base_ops,
  490. .set_piomode = sis_100_set_piomode,
  491. .set_dmamode = sis_100_set_dmamode,
  492. .cable_detect = sis_66_cable_detect,
  493. };
  494. static struct ata_port_operations sis_66_ops = {
  495. .inherits = &sis_base_ops,
  496. .set_piomode = sis_old_set_piomode,
  497. .set_dmamode = sis_66_set_dmamode,
  498. .cable_detect = sis_66_cable_detect,
  499. };
  500. static struct ata_port_operations sis_old_ops = {
  501. .inherits = &sis_base_ops,
  502. .set_piomode = sis_old_set_piomode,
  503. .set_dmamode = sis_old_set_dmamode,
  504. .cable_detect = ata_cable_40wire,
  505. };
  506. static const struct ata_port_info sis_info = {
  507. .flags = ATA_FLAG_SLAVE_POSS,
  508. .pio_mask = ATA_PIO4,
  509. .mwdma_mask = ATA_MWDMA2,
  510. /* No UDMA */
  511. .port_ops = &sis_old_ops,
  512. };
  513. static const struct ata_port_info sis_info33 = {
  514. .flags = ATA_FLAG_SLAVE_POSS,
  515. .pio_mask = ATA_PIO4,
  516. .mwdma_mask = ATA_MWDMA2,
  517. .udma_mask = ATA_UDMA2,
  518. .port_ops = &sis_old_ops,
  519. };
  520. static const struct ata_port_info sis_info66 = {
  521. .flags = ATA_FLAG_SLAVE_POSS,
  522. .pio_mask = ATA_PIO4,
  523. /* No MWDMA */
  524. .udma_mask = ATA_UDMA4,
  525. .port_ops = &sis_66_ops,
  526. };
  527. static const struct ata_port_info sis_info100 = {
  528. .flags = ATA_FLAG_SLAVE_POSS,
  529. .pio_mask = ATA_PIO4,
  530. /* No MWDMA */
  531. .udma_mask = ATA_UDMA5,
  532. .port_ops = &sis_100_ops,
  533. };
  534. static const struct ata_port_info sis_info100_early = {
  535. .flags = ATA_FLAG_SLAVE_POSS,
  536. .pio_mask = ATA_PIO4,
  537. /* No MWDMA */
  538. .udma_mask = ATA_UDMA5,
  539. .port_ops = &sis_66_ops,
  540. };
  541. static const struct ata_port_info sis_info133 = {
  542. .flags = ATA_FLAG_SLAVE_POSS,
  543. .pio_mask = ATA_PIO4,
  544. .mwdma_mask = ATA_MWDMA2,
  545. .udma_mask = ATA_UDMA6,
  546. .port_ops = &sis_133_ops,
  547. };
  548. const struct ata_port_info sis_info133_for_sata = {
  549. .flags = ATA_FLAG_SLAVE_POSS,
  550. .pio_mask = ATA_PIO4,
  551. /* No MWDMA */
  552. .udma_mask = ATA_UDMA6,
  553. .port_ops = &sis_133_for_sata_ops,
  554. };
  555. static const struct ata_port_info sis_info133_early = {
  556. .flags = ATA_FLAG_SLAVE_POSS,
  557. .pio_mask = ATA_PIO4,
  558. /* No MWDMA */
  559. .udma_mask = ATA_UDMA6,
  560. .port_ops = &sis_133_early_ops,
  561. };
  562. /* Privately shared with the SiS180 SATA driver, not for use elsewhere */
  563. EXPORT_SYMBOL_GPL(sis_info133_for_sata);
  564. static void sis_fixup(struct pci_dev *pdev, struct sis_chipset *sis)
  565. {
  566. u16 regw;
  567. u8 reg;
  568. if (sis->info == &sis_info133) {
  569. pci_read_config_word(pdev, 0x50, &regw);
  570. if (regw & 0x08)
  571. pci_write_config_word(pdev, 0x50, regw & ~0x08);
  572. pci_read_config_word(pdev, 0x52, &regw);
  573. if (regw & 0x08)
  574. pci_write_config_word(pdev, 0x52, regw & ~0x08);
  575. return;
  576. }
  577. if (sis->info == &sis_info133_early || sis->info == &sis_info100) {
  578. /* Fix up latency */
  579. pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
  580. /* Set compatibility bit */
  581. pci_read_config_byte(pdev, 0x49, &reg);
  582. if (!(reg & 0x01))
  583. pci_write_config_byte(pdev, 0x49, reg | 0x01);
  584. return;
  585. }
  586. if (sis->info == &sis_info66 || sis->info == &sis_info100_early) {
  587. /* Fix up latency */
  588. pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
  589. /* Set compatibility bit */
  590. pci_read_config_byte(pdev, 0x52, &reg);
  591. if (!(reg & 0x04))
  592. pci_write_config_byte(pdev, 0x52, reg | 0x04);
  593. return;
  594. }
  595. if (sis->info == &sis_info33) {
  596. pci_read_config_byte(pdev, PCI_CLASS_PROG, &reg);
  597. if (( reg & 0x0F ) != 0x00)
  598. pci_write_config_byte(pdev, PCI_CLASS_PROG, reg & 0xF0);
  599. /* Fall through to ATA16 fixup below */
  600. }
  601. if (sis->info == &sis_info || sis->info == &sis_info33) {
  602. /* force per drive recovery and active timings
  603. needed on ATA_33 and below chips */
  604. pci_read_config_byte(pdev, 0x52, &reg);
  605. if (!(reg & 0x08))
  606. pci_write_config_byte(pdev, 0x52, reg|0x08);
  607. return;
  608. }
  609. BUG();
  610. }
  611. /**
  612. * sis_init_one - Register SiS ATA PCI device with kernel services
  613. * @pdev: PCI device to register
  614. * @ent: Entry in sis_pci_tbl matching with @pdev
  615. *
  616. * Called from kernel PCI layer. We probe for combined mode (sigh),
  617. * and then hand over control to libata, for it to do the rest.
  618. *
  619. * LOCKING:
  620. * Inherited from PCI layer (may sleep).
  621. *
  622. * RETURNS:
  623. * Zero on success, or -ERRNO value.
  624. */
  625. static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
  626. {
  627. const struct ata_port_info *ppi[] = { NULL, NULL };
  628. struct pci_dev *host = NULL;
  629. struct sis_chipset *chipset = NULL;
  630. struct sis_chipset *sets;
  631. int rc;
  632. static struct sis_chipset sis_chipsets[] = {
  633. { 0x0968, &sis_info133 },
  634. { 0x0966, &sis_info133 },
  635. { 0x0965, &sis_info133 },
  636. { 0x0745, &sis_info100 },
  637. { 0x0735, &sis_info100 },
  638. { 0x0733, &sis_info100 },
  639. { 0x0635, &sis_info100 },
  640. { 0x0633, &sis_info100 },
  641. { 0x0730, &sis_info100_early }, /* 100 with ATA 66 layout */
  642. { 0x0550, &sis_info100_early }, /* 100 with ATA 66 layout */
  643. { 0x0640, &sis_info66 },
  644. { 0x0630, &sis_info66 },
  645. { 0x0620, &sis_info66 },
  646. { 0x0540, &sis_info66 },
  647. { 0x0530, &sis_info66 },
  648. { 0x5600, &sis_info33 },
  649. { 0x5598, &sis_info33 },
  650. { 0x5597, &sis_info33 },
  651. { 0x5591, &sis_info33 },
  652. { 0x5582, &sis_info33 },
  653. { 0x5581, &sis_info33 },
  654. { 0x5596, &sis_info },
  655. { 0x5571, &sis_info },
  656. { 0x5517, &sis_info },
  657. { 0x5511, &sis_info },
  658. {0}
  659. };
  660. static struct sis_chipset sis133_early = {
  661. 0x0, &sis_info133_early
  662. };
  663. static struct sis_chipset sis133 = {
  664. 0x0, &sis_info133
  665. };
  666. static struct sis_chipset sis100_early = {
  667. 0x0, &sis_info100_early
  668. };
  669. static struct sis_chipset sis100 = {
  670. 0x0, &sis_info100
  671. };
  672. ata_print_version_once(&pdev->dev, DRV_VERSION);
  673. rc = pcim_enable_device(pdev);
  674. if (rc)
  675. return rc;
  676. /* We have to find the bridge first */
  677. for (sets = &sis_chipsets[0]; sets->device; sets++) {
  678. host = pci_get_device(PCI_VENDOR_ID_SI, sets->device, NULL);
  679. if (host != NULL) {
  680. chipset = sets; /* Match found */
  681. if (sets->device == 0x630) { /* SIS630 */
  682. if (host->revision >= 0x30) /* 630 ET */
  683. chipset = &sis100_early;
  684. }
  685. break;
  686. }
  687. }
  688. /* Look for concealed bridges */
  689. if (chipset == NULL) {
  690. /* Second check */
  691. u32 idemisc;
  692. u16 trueid;
  693. /* Disable ID masking and register remapping then
  694. see what the real ID is */
  695. pci_read_config_dword(pdev, 0x54, &idemisc);
  696. pci_write_config_dword(pdev, 0x54, idemisc & 0x7fffffff);
  697. pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid);
  698. pci_write_config_dword(pdev, 0x54, idemisc);
  699. switch(trueid) {
  700. case 0x5518: /* SIS 962/963 */
  701. dev_info(&pdev->dev,
  702. "SiS 962/963 MuTIOL IDE UDMA133 controller\n");
  703. chipset = &sis133;
  704. if ((idemisc & 0x40000000) == 0) {
  705. pci_write_config_dword(pdev, 0x54, idemisc | 0x40000000);
  706. dev_info(&pdev->dev,
  707. "Switching to 5513 register mapping\n");
  708. }
  709. break;
  710. case 0x0180: /* SIS 965/965L */
  711. chipset = &sis133;
  712. break;
  713. case 0x1180: /* SIS 966/966L */
  714. chipset = &sis133;
  715. break;
  716. }
  717. }
  718. /* Further check */
  719. if (chipset == NULL) {
  720. struct pci_dev *lpc_bridge;
  721. u16 trueid;
  722. u8 prefctl;
  723. u8 idecfg;
  724. /* Try the second unmasking technique */
  725. pci_read_config_byte(pdev, 0x4a, &idecfg);
  726. pci_write_config_byte(pdev, 0x4a, idecfg | 0x10);
  727. pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid);
  728. pci_write_config_byte(pdev, 0x4a, idecfg);
  729. switch(trueid) {
  730. case 0x5517:
  731. lpc_bridge = pci_get_slot(pdev->bus, 0x10); /* Bus 0 Dev 2 Fn 0 */
  732. if (lpc_bridge == NULL)
  733. break;
  734. pci_read_config_byte(pdev, 0x49, &prefctl);
  735. pci_dev_put(lpc_bridge);
  736. if (lpc_bridge->revision == 0x10 && (prefctl & 0x80)) {
  737. chipset = &sis133_early;
  738. break;
  739. }
  740. chipset = &sis100;
  741. break;
  742. }
  743. }
  744. pci_dev_put(host);
  745. /* No chipset info, no support */
  746. if (chipset == NULL)
  747. return -ENODEV;
  748. ppi[0] = chipset->info;
  749. sis_fixup(pdev, chipset);
  750. return ata_pci_bmdma_init_one(pdev, ppi, &sis_sht, chipset, 0);
  751. }
  752. #ifdef CONFIG_PM_SLEEP
  753. static int sis_reinit_one(struct pci_dev *pdev)
  754. {
  755. struct ata_host *host = pci_get_drvdata(pdev);
  756. int rc;
  757. rc = ata_pci_device_do_resume(pdev);
  758. if (rc)
  759. return rc;
  760. sis_fixup(pdev, host->private_data);
  761. ata_host_resume(host);
  762. return 0;
  763. }
  764. #endif
  765. static const struct pci_device_id sis_pci_tbl[] = {
  766. { PCI_VDEVICE(SI, 0x5513), }, /* SiS 5513 */
  767. { PCI_VDEVICE(SI, 0x5518), }, /* SiS 5518 */
  768. { PCI_VDEVICE(SI, 0x1180), }, /* SiS 1180 */
  769. { }
  770. };
  771. static struct pci_driver sis_pci_driver = {
  772. .name = DRV_NAME,
  773. .id_table = sis_pci_tbl,
  774. .probe = sis_init_one,
  775. .remove = ata_pci_remove_one,
  776. #ifdef CONFIG_PM_SLEEP
  777. .suspend = ata_pci_device_suspend,
  778. .resume = sis_reinit_one,
  779. #endif
  780. };
  781. module_pci_driver(sis_pci_driver);
  782. MODULE_AUTHOR("Alan Cox");
  783. MODULE_DESCRIPTION("SCSI low-level driver for SiS ATA");
  784. MODULE_LICENSE("GPL");
  785. MODULE_DEVICE_TABLE(pci, sis_pci_tbl);
  786. MODULE_VERSION(DRV_VERSION);