pata_serverworks.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * pata_serverworks.c - Serverworks PATA for new ATA layer
  4. * (C) 2005 Red Hat Inc
  5. * (C) 2010 Bartlomiej Zolnierkiewicz
  6. *
  7. * based upon
  8. *
  9. * serverworks.c
  10. *
  11. * Copyright (C) 1998-2000 Michel Aubry
  12. * Copyright (C) 1998-2000 Andrzej Krzysztofowicz
  13. * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
  14. * Portions copyright (c) 2001 Sun Microsystems
  15. *
  16. *
  17. * RCC/ServerWorks IDE driver for Linux
  18. *
  19. * OSB4: `Open South Bridge' IDE Interface (fn 1)
  20. * supports UDMA mode 2 (33 MB/s)
  21. *
  22. * CSB5: `Champion South Bridge' IDE Interface (fn 1)
  23. * all revisions support UDMA mode 4 (66 MB/s)
  24. * revision A2.0 and up support UDMA mode 5 (100 MB/s)
  25. *
  26. * *** The CSB5 does not provide ANY register ***
  27. * *** to detect 80-conductor cable presence. ***
  28. *
  29. * CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
  30. *
  31. * Documentation:
  32. * Available under NDA only. Errata info very hard to get.
  33. */
  34. #include <linux/kernel.h>
  35. #include <linux/module.h>
  36. #include <linux/pci.h>
  37. #include <linux/blkdev.h>
  38. #include <linux/delay.h>
  39. #include <scsi/scsi_host.h>
  40. #include <linux/libata.h>
  41. #define DRV_NAME "pata_serverworks"
  42. #define DRV_VERSION "0.4.3"
  43. #define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */
  44. #define SVWKS_CSB6_REVISION 0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */
  45. /* Seagate Barracuda ATA IV Family drives in UDMA mode 5
  46. * can overrun their FIFOs when used with the CSB5 */
  47. static const char *csb_bad_ata100[] = {
  48. "ST320011A",
  49. "ST340016A",
  50. "ST360021A",
  51. "ST380021A",
  52. NULL
  53. };
  54. /**
  55. * oem_cable - Dell/Sun serverworks cable detection
  56. * @ap: ATA port to do cable detect
  57. *
  58. * Dell PowerEdge and Sun Cobalt 'Alpine' hide the 40/80 pin select
  59. * for their interfaces in the top two bits of the subsystem ID.
  60. */
  61. static int oem_cable(struct ata_port *ap)
  62. {
  63. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  64. if (pdev->subsystem_device & (1 << (ap->port_no + 14)))
  65. return ATA_CBL_PATA80;
  66. return ATA_CBL_PATA40;
  67. }
  68. struct sv_cable_table {
  69. int device;
  70. int subvendor;
  71. int (*cable_detect)(struct ata_port *ap);
  72. };
  73. static struct sv_cable_table cable_detect[] = {
  74. { PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_VENDOR_ID_DELL, oem_cable },
  75. { PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_VENDOR_ID_DELL, oem_cable },
  76. { PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_VENDOR_ID_SUN, oem_cable },
  77. { PCI_DEVICE_ID_SERVERWORKS_OSB4IDE, PCI_ANY_ID, ata_cable_40wire },
  78. { PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_ANY_ID, ata_cable_unknown },
  79. { PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_ANY_ID, ata_cable_unknown },
  80. { PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2, PCI_ANY_ID, ata_cable_unknown },
  81. { PCI_DEVICE_ID_SERVERWORKS_HT1000IDE, PCI_ANY_ID, ata_cable_unknown },
  82. { }
  83. };
  84. /**
  85. * serverworks_cable_detect - cable detection
  86. * @ap: ATA port
  87. *
  88. * Perform cable detection according to the device and subvendor
  89. * identifications
  90. */
  91. static int serverworks_cable_detect(struct ata_port *ap)
  92. {
  93. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  94. struct sv_cable_table *cb = cable_detect;
  95. while(cb->device) {
  96. if (cb->device == pdev->device &&
  97. (cb->subvendor == pdev->subsystem_vendor ||
  98. cb->subvendor == PCI_ANY_ID)) {
  99. return cb->cable_detect(ap);
  100. }
  101. cb++;
  102. }
  103. BUG();
  104. return -1; /* kill compiler warning */
  105. }
  106. /**
  107. * serverworks_is_csb - Check for CSB or OSB
  108. * @pdev: PCI device to check
  109. *
  110. * Returns true if the device being checked is known to be a CSB
  111. * series device.
  112. */
  113. static u8 serverworks_is_csb(struct pci_dev *pdev)
  114. {
  115. switch (pdev->device) {
  116. case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
  117. case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
  118. case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
  119. case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
  120. return 1;
  121. default:
  122. break;
  123. }
  124. return 0;
  125. }
  126. /**
  127. * serverworks_osb4_filter - mode selection filter
  128. * @adev: ATA device
  129. * @mask: Mask of proposed modes
  130. *
  131. * Filter the offered modes for the device to apply controller
  132. * specific rules. OSB4 requires no UDMA for disks due to a FIFO
  133. * bug we hit.
  134. */
  135. static unsigned long serverworks_osb4_filter(struct ata_device *adev, unsigned long mask)
  136. {
  137. if (adev->class == ATA_DEV_ATA)
  138. mask &= ~ATA_MASK_UDMA;
  139. return mask;
  140. }
  141. /**
  142. * serverworks_csb_filter - mode selection filter
  143. * @adev: ATA device
  144. * @mask: Mask of proposed modes
  145. *
  146. * Check the blacklist and disable UDMA5 if matched
  147. */
  148. static unsigned long serverworks_csb_filter(struct ata_device *adev, unsigned long mask)
  149. {
  150. const char *p;
  151. char model_num[ATA_ID_PROD_LEN + 1];
  152. int i;
  153. /* Disk, UDMA */
  154. if (adev->class != ATA_DEV_ATA)
  155. return mask;
  156. /* Actually do need to check */
  157. ata_id_c_string(adev->id, model_num, ATA_ID_PROD, sizeof(model_num));
  158. for (i = 0; (p = csb_bad_ata100[i]) != NULL; i++) {
  159. if (!strcmp(p, model_num))
  160. mask &= ~(0xE0 << ATA_SHIFT_UDMA);
  161. }
  162. return mask;
  163. }
  164. /**
  165. * serverworks_set_piomode - set initial PIO mode data
  166. * @ap: ATA interface
  167. * @adev: ATA device
  168. *
  169. * Program the OSB4/CSB5 timing registers for PIO. The PIO register
  170. * load is done as a simple lookup.
  171. */
  172. static void serverworks_set_piomode(struct ata_port *ap, struct ata_device *adev)
  173. {
  174. static const u8 pio_mode[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
  175. int offset = 1 + 2 * ap->port_no - adev->devno;
  176. int devbits = (2 * ap->port_no + adev->devno) * 4;
  177. u16 csb5_pio;
  178. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  179. int pio = adev->pio_mode - XFER_PIO_0;
  180. pci_write_config_byte(pdev, 0x40 + offset, pio_mode[pio]);
  181. /* The OSB4 just requires the timing but the CSB series want the
  182. mode number as well */
  183. if (serverworks_is_csb(pdev)) {
  184. pci_read_config_word(pdev, 0x4A, &csb5_pio);
  185. csb5_pio &= ~(0x0F << devbits);
  186. pci_write_config_word(pdev, 0x4A, csb5_pio | (pio << devbits));
  187. }
  188. }
  189. /**
  190. * serverworks_set_dmamode - set initial DMA mode data
  191. * @ap: ATA interface
  192. * @adev: ATA device
  193. *
  194. * Program the MWDMA/UDMA modes for the serverworks OSB4/CSB5
  195. * chipset. The MWDMA mode values are pulled from a lookup table
  196. * while the chipset uses mode number for UDMA.
  197. */
  198. static void serverworks_set_dmamode(struct ata_port *ap, struct ata_device *adev)
  199. {
  200. static const u8 dma_mode[] = { 0x77, 0x21, 0x20 };
  201. int offset = 1 + 2 * ap->port_no - adev->devno;
  202. int devbits = 2 * ap->port_no + adev->devno;
  203. u8 ultra;
  204. u8 ultra_cfg;
  205. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  206. pci_read_config_byte(pdev, 0x54, &ultra_cfg);
  207. pci_read_config_byte(pdev, 0x56 + ap->port_no, &ultra);
  208. ultra &= ~(0x0F << (adev->devno * 4));
  209. if (adev->dma_mode >= XFER_UDMA_0) {
  210. pci_write_config_byte(pdev, 0x44 + offset, 0x20);
  211. ultra |= (adev->dma_mode - XFER_UDMA_0)
  212. << (adev->devno * 4);
  213. ultra_cfg |= (1 << devbits);
  214. } else {
  215. pci_write_config_byte(pdev, 0x44 + offset,
  216. dma_mode[adev->dma_mode - XFER_MW_DMA_0]);
  217. ultra_cfg &= ~(1 << devbits);
  218. }
  219. pci_write_config_byte(pdev, 0x56 + ap->port_no, ultra);
  220. pci_write_config_byte(pdev, 0x54, ultra_cfg);
  221. }
  222. static struct scsi_host_template serverworks_osb4_sht = {
  223. ATA_BMDMA_SHT(DRV_NAME),
  224. .sg_tablesize = LIBATA_DUMB_MAX_PRD,
  225. };
  226. static struct scsi_host_template serverworks_csb_sht = {
  227. ATA_BMDMA_SHT(DRV_NAME),
  228. };
  229. static struct ata_port_operations serverworks_osb4_port_ops = {
  230. .inherits = &ata_bmdma_port_ops,
  231. .qc_prep = ata_bmdma_dumb_qc_prep,
  232. .cable_detect = serverworks_cable_detect,
  233. .mode_filter = serverworks_osb4_filter,
  234. .set_piomode = serverworks_set_piomode,
  235. .set_dmamode = serverworks_set_dmamode,
  236. };
  237. static struct ata_port_operations serverworks_csb_port_ops = {
  238. .inherits = &serverworks_osb4_port_ops,
  239. .qc_prep = ata_bmdma_qc_prep,
  240. .mode_filter = serverworks_csb_filter,
  241. };
  242. static int serverworks_fixup_osb4(struct pci_dev *pdev)
  243. {
  244. u32 reg;
  245. struct pci_dev *isa_dev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
  246. PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL);
  247. if (isa_dev) {
  248. pci_read_config_dword(isa_dev, 0x64, &reg);
  249. reg &= ~0x00002000; /* disable 600ns interrupt mask */
  250. if (!(reg & 0x00004000))
  251. printk(KERN_DEBUG DRV_NAME ": UDMA not BIOS enabled.\n");
  252. reg |= 0x00004000; /* enable UDMA/33 support */
  253. pci_write_config_dword(isa_dev, 0x64, reg);
  254. pci_dev_put(isa_dev);
  255. return 0;
  256. }
  257. printk(KERN_WARNING DRV_NAME ": Unable to find bridge.\n");
  258. return -ENODEV;
  259. }
  260. static int serverworks_fixup_csb(struct pci_dev *pdev)
  261. {
  262. u8 btr;
  263. /* Third Channel Test */
  264. if (!(PCI_FUNC(pdev->devfn) & 1)) {
  265. struct pci_dev * findev = NULL;
  266. u32 reg4c = 0;
  267. findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
  268. PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL);
  269. if (findev) {
  270. pci_read_config_dword(findev, 0x4C, &reg4c);
  271. reg4c &= ~0x000007FF;
  272. reg4c |= 0x00000040;
  273. reg4c |= 0x00000020;
  274. pci_write_config_dword(findev, 0x4C, reg4c);
  275. pci_dev_put(findev);
  276. }
  277. } else {
  278. struct pci_dev * findev = NULL;
  279. u8 reg41 = 0;
  280. findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
  281. PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL);
  282. if (findev) {
  283. pci_read_config_byte(findev, 0x41, &reg41);
  284. reg41 &= ~0x40;
  285. pci_write_config_byte(findev, 0x41, reg41);
  286. pci_dev_put(findev);
  287. }
  288. }
  289. /* setup the UDMA Control register
  290. *
  291. * 1. clear bit 6 to enable DMA
  292. * 2. enable DMA modes with bits 0-1
  293. * 00 : legacy
  294. * 01 : udma2
  295. * 10 : udma2/udma4
  296. * 11 : udma2/udma4/udma5
  297. */
  298. pci_read_config_byte(pdev, 0x5A, &btr);
  299. btr &= ~0x40;
  300. if (!(PCI_FUNC(pdev->devfn) & 1))
  301. btr |= 0x2;
  302. else
  303. btr |= (pdev->revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
  304. pci_write_config_byte(pdev, 0x5A, btr);
  305. return btr;
  306. }
  307. static void serverworks_fixup_ht1000(struct pci_dev *pdev)
  308. {
  309. u8 btr;
  310. /* Setup HT1000 SouthBridge Controller - Single Channel Only */
  311. pci_read_config_byte(pdev, 0x5A, &btr);
  312. btr &= ~0x40;
  313. btr |= 0x3;
  314. pci_write_config_byte(pdev, 0x5A, btr);
  315. }
  316. static int serverworks_fixup(struct pci_dev *pdev)
  317. {
  318. int rc = 0;
  319. /* Force master latency timer to 64 PCI clocks */
  320. pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x40);
  321. switch (pdev->device) {
  322. case PCI_DEVICE_ID_SERVERWORKS_OSB4IDE:
  323. rc = serverworks_fixup_osb4(pdev);
  324. break;
  325. case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
  326. ata_pci_bmdma_clear_simplex(pdev);
  327. fallthrough;
  328. case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
  329. case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
  330. rc = serverworks_fixup_csb(pdev);
  331. break;
  332. case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
  333. serverworks_fixup_ht1000(pdev);
  334. break;
  335. }
  336. return rc;
  337. }
  338. static int serverworks_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
  339. {
  340. static const struct ata_port_info info[4] = {
  341. { /* OSB4 */
  342. .flags = ATA_FLAG_SLAVE_POSS,
  343. .pio_mask = ATA_PIO4,
  344. .mwdma_mask = ATA_MWDMA2,
  345. .udma_mask = ATA_UDMA2,
  346. .port_ops = &serverworks_osb4_port_ops
  347. }, { /* OSB4 no UDMA */
  348. .flags = ATA_FLAG_SLAVE_POSS,
  349. .pio_mask = ATA_PIO4,
  350. .mwdma_mask = ATA_MWDMA2,
  351. /* No UDMA */
  352. .port_ops = &serverworks_osb4_port_ops
  353. }, { /* CSB5 */
  354. .flags = ATA_FLAG_SLAVE_POSS,
  355. .pio_mask = ATA_PIO4,
  356. .mwdma_mask = ATA_MWDMA2,
  357. .udma_mask = ATA_UDMA4,
  358. .port_ops = &serverworks_csb_port_ops
  359. }, { /* CSB5 - later revisions*/
  360. .flags = ATA_FLAG_SLAVE_POSS,
  361. .pio_mask = ATA_PIO4,
  362. .mwdma_mask = ATA_MWDMA2,
  363. .udma_mask = ATA_UDMA5,
  364. .port_ops = &serverworks_csb_port_ops
  365. }
  366. };
  367. const struct ata_port_info *ppi[] = { &info[id->driver_data], NULL };
  368. struct scsi_host_template *sht = &serverworks_csb_sht;
  369. int rc;
  370. rc = pcim_enable_device(pdev);
  371. if (rc)
  372. return rc;
  373. rc = serverworks_fixup(pdev);
  374. /* OSB4 : South Bridge and IDE */
  375. if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
  376. /* Select non UDMA capable OSB4 if we can't do fixups */
  377. if (rc < 0)
  378. ppi[0] = &info[1];
  379. sht = &serverworks_osb4_sht;
  380. }
  381. /* setup CSB5/CSB6 : South Bridge and IDE option RAID */
  382. else if ((pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) ||
  383. (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
  384. (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
  385. /* If the returned btr is the newer revision then
  386. select the right info block */
  387. if (rc == 3)
  388. ppi[0] = &info[3];
  389. /* Is this the 3rd channel CSB6 IDE ? */
  390. if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)
  391. ppi[1] = &ata_dummy_port_info;
  392. }
  393. return ata_pci_bmdma_init_one(pdev, ppi, sht, NULL, 0);
  394. }
  395. #ifdef CONFIG_PM_SLEEP
  396. static int serverworks_reinit_one(struct pci_dev *pdev)
  397. {
  398. struct ata_host *host = pci_get_drvdata(pdev);
  399. int rc;
  400. rc = ata_pci_device_do_resume(pdev);
  401. if (rc)
  402. return rc;
  403. (void)serverworks_fixup(pdev);
  404. ata_host_resume(host);
  405. return 0;
  406. }
  407. #endif
  408. static const struct pci_device_id serverworks[] = {
  409. { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE), 0},
  410. { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE), 2},
  411. { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE), 2},
  412. { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2), 2},
  413. { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE), 2},
  414. { },
  415. };
  416. static struct pci_driver serverworks_pci_driver = {
  417. .name = DRV_NAME,
  418. .id_table = serverworks,
  419. .probe = serverworks_init_one,
  420. .remove = ata_pci_remove_one,
  421. #ifdef CONFIG_PM_SLEEP
  422. .suspend = ata_pci_device_suspend,
  423. .resume = serverworks_reinit_one,
  424. #endif
  425. };
  426. module_pci_driver(serverworks_pci_driver);
  427. MODULE_AUTHOR("Alan Cox");
  428. MODULE_DESCRIPTION("low-level driver for Serverworks OSB4/CSB5/CSB6");
  429. MODULE_LICENSE("GPL");
  430. MODULE_DEVICE_TABLE(pci, serverworks);
  431. MODULE_VERSION(DRV_VERSION);