pata_rdc.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * pata_rdc - Driver for later RDC PATA controllers
  4. *
  5. * This is actually a driver for hardware meeting
  6. * INCITS 370-2004 (1510D): ATA Host Adapter Standards
  7. *
  8. * Based on ata_piix.
  9. */
  10. #include <linux/kernel.h>
  11. #include <linux/module.h>
  12. #include <linux/pci.h>
  13. #include <linux/blkdev.h>
  14. #include <linux/delay.h>
  15. #include <linux/device.h>
  16. #include <linux/gfp.h>
  17. #include <scsi/scsi_host.h>
  18. #include <linux/libata.h>
  19. #include <linux/dmi.h>
  20. #define DRV_NAME "pata_rdc"
  21. #define DRV_VERSION "0.01"
  22. struct rdc_host_priv {
  23. u32 saved_iocfg;
  24. };
  25. /**
  26. * rdc_pata_cable_detect - Probe host controller cable detect info
  27. * @ap: Port for which cable detect info is desired
  28. *
  29. * Read 80c cable indicator from ATA PCI device's PCI config
  30. * register. This register is normally set by firmware (BIOS).
  31. *
  32. * LOCKING:
  33. * None (inherited from caller).
  34. */
  35. static int rdc_pata_cable_detect(struct ata_port *ap)
  36. {
  37. struct rdc_host_priv *hpriv = ap->host->private_data;
  38. u8 mask;
  39. /* check BIOS cable detect results */
  40. mask = 0x30 << (2 * ap->port_no);
  41. if ((hpriv->saved_iocfg & mask) == 0)
  42. return ATA_CBL_PATA40;
  43. return ATA_CBL_PATA80;
  44. }
  45. /**
  46. * rdc_pata_prereset - prereset for PATA host controller
  47. * @link: Target link
  48. * @deadline: deadline jiffies for the operation
  49. *
  50. * LOCKING:
  51. * None (inherited from caller).
  52. */
  53. static int rdc_pata_prereset(struct ata_link *link, unsigned long deadline)
  54. {
  55. struct ata_port *ap = link->ap;
  56. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  57. static const struct pci_bits rdc_enable_bits[] = {
  58. { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
  59. { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
  60. };
  61. if (!pci_test_config_bits(pdev, &rdc_enable_bits[ap->port_no]))
  62. return -ENOENT;
  63. return ata_sff_prereset(link, deadline);
  64. }
  65. static DEFINE_SPINLOCK(rdc_lock);
  66. /**
  67. * rdc_set_piomode - Initialize host controller PATA PIO timings
  68. * @ap: Port whose timings we are configuring
  69. * @adev: um
  70. *
  71. * Set PIO mode for device, in host controller PCI config space.
  72. *
  73. * LOCKING:
  74. * None (inherited from caller).
  75. */
  76. static void rdc_set_piomode(struct ata_port *ap, struct ata_device *adev)
  77. {
  78. unsigned int pio = adev->pio_mode - XFER_PIO_0;
  79. struct pci_dev *dev = to_pci_dev(ap->host->dev);
  80. unsigned long flags;
  81. unsigned int is_slave = (adev->devno != 0);
  82. unsigned int master_port= ap->port_no ? 0x42 : 0x40;
  83. unsigned int slave_port = 0x44;
  84. u16 master_data;
  85. u8 slave_data;
  86. u8 udma_enable;
  87. int control = 0;
  88. static const /* ISP RTC */
  89. u8 timings[][2] = { { 0, 0 },
  90. { 0, 0 },
  91. { 1, 0 },
  92. { 2, 1 },
  93. { 2, 3 }, };
  94. if (pio >= 2)
  95. control |= 1; /* TIME1 enable */
  96. if (ata_pio_need_iordy(adev))
  97. control |= 2; /* IE enable */
  98. if (adev->class == ATA_DEV_ATA)
  99. control |= 4; /* PPE enable */
  100. spin_lock_irqsave(&rdc_lock, flags);
  101. /* PIO configuration clears DTE unconditionally. It will be
  102. * programmed in set_dmamode which is guaranteed to be called
  103. * after set_piomode if any DMA mode is available.
  104. */
  105. pci_read_config_word(dev, master_port, &master_data);
  106. if (is_slave) {
  107. /* clear TIME1|IE1|PPE1|DTE1 */
  108. master_data &= 0xff0f;
  109. /* Enable SITRE (separate slave timing register) */
  110. master_data |= 0x4000;
  111. /* enable PPE1, IE1 and TIME1 as needed */
  112. master_data |= (control << 4);
  113. pci_read_config_byte(dev, slave_port, &slave_data);
  114. slave_data &= (ap->port_no ? 0x0f : 0xf0);
  115. /* Load the timing nibble for this slave */
  116. slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
  117. << (ap->port_no ? 4 : 0);
  118. } else {
  119. /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
  120. master_data &= 0xccf0;
  121. /* Enable PPE, IE and TIME as appropriate */
  122. master_data |= control;
  123. /* load ISP and RCT */
  124. master_data |=
  125. (timings[pio][0] << 12) |
  126. (timings[pio][1] << 8);
  127. }
  128. pci_write_config_word(dev, master_port, master_data);
  129. if (is_slave)
  130. pci_write_config_byte(dev, slave_port, slave_data);
  131. /* Ensure the UDMA bit is off - it will be turned back on if
  132. UDMA is selected */
  133. pci_read_config_byte(dev, 0x48, &udma_enable);
  134. udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
  135. pci_write_config_byte(dev, 0x48, udma_enable);
  136. spin_unlock_irqrestore(&rdc_lock, flags);
  137. }
  138. /**
  139. * rdc_set_dmamode - Initialize host controller PATA PIO timings
  140. * @ap: Port whose timings we are configuring
  141. * @adev: Drive in question
  142. *
  143. * Set UDMA mode for device, in host controller PCI config space.
  144. *
  145. * LOCKING:
  146. * None (inherited from caller).
  147. */
  148. static void rdc_set_dmamode(struct ata_port *ap, struct ata_device *adev)
  149. {
  150. struct pci_dev *dev = to_pci_dev(ap->host->dev);
  151. unsigned long flags;
  152. u8 master_port = ap->port_no ? 0x42 : 0x40;
  153. u16 master_data;
  154. u8 speed = adev->dma_mode;
  155. int devid = adev->devno + 2 * ap->port_no;
  156. u8 udma_enable = 0;
  157. static const /* ISP RTC */
  158. u8 timings[][2] = { { 0, 0 },
  159. { 0, 0 },
  160. { 1, 0 },
  161. { 2, 1 },
  162. { 2, 3 }, };
  163. spin_lock_irqsave(&rdc_lock, flags);
  164. pci_read_config_word(dev, master_port, &master_data);
  165. pci_read_config_byte(dev, 0x48, &udma_enable);
  166. if (speed >= XFER_UDMA_0) {
  167. unsigned int udma = adev->dma_mode - XFER_UDMA_0;
  168. u16 udma_timing;
  169. u16 ideconf;
  170. int u_clock, u_speed;
  171. /*
  172. * UDMA is handled by a combination of clock switching and
  173. * selection of dividers
  174. *
  175. * Handy rule: Odd modes are UDMATIMx 01, even are 02
  176. * except UDMA0 which is 00
  177. */
  178. u_speed = min(2 - (udma & 1), udma);
  179. if (udma == 5)
  180. u_clock = 0x1000; /* 100Mhz */
  181. else if (udma > 2)
  182. u_clock = 1; /* 66Mhz */
  183. else
  184. u_clock = 0; /* 33Mhz */
  185. udma_enable |= (1 << devid);
  186. /* Load the CT/RP selection */
  187. pci_read_config_word(dev, 0x4A, &udma_timing);
  188. udma_timing &= ~(3 << (4 * devid));
  189. udma_timing |= u_speed << (4 * devid);
  190. pci_write_config_word(dev, 0x4A, udma_timing);
  191. /* Select a 33/66/100Mhz clock */
  192. pci_read_config_word(dev, 0x54, &ideconf);
  193. ideconf &= ~(0x1001 << devid);
  194. ideconf |= u_clock << devid;
  195. pci_write_config_word(dev, 0x54, ideconf);
  196. } else {
  197. /*
  198. * MWDMA is driven by the PIO timings. We must also enable
  199. * IORDY unconditionally along with TIME1. PPE has already
  200. * been set when the PIO timing was set.
  201. */
  202. unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
  203. unsigned int control;
  204. u8 slave_data;
  205. const unsigned int needed_pio[3] = {
  206. XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
  207. };
  208. int pio = needed_pio[mwdma] - XFER_PIO_0;
  209. control = 3; /* IORDY|TIME1 */
  210. /* If the drive MWDMA is faster than it can do PIO then
  211. we must force PIO into PIO0 */
  212. if (adev->pio_mode < needed_pio[mwdma])
  213. /* Enable DMA timing only */
  214. control |= 8; /* PIO cycles in PIO0 */
  215. if (adev->devno) { /* Slave */
  216. master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
  217. master_data |= control << 4;
  218. pci_read_config_byte(dev, 0x44, &slave_data);
  219. slave_data &= (ap->port_no ? 0x0f : 0xf0);
  220. /* Load the matching timing */
  221. slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
  222. pci_write_config_byte(dev, 0x44, slave_data);
  223. } else { /* Master */
  224. master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
  225. and master timing bits */
  226. master_data |= control;
  227. master_data |=
  228. (timings[pio][0] << 12) |
  229. (timings[pio][1] << 8);
  230. }
  231. udma_enable &= ~(1 << devid);
  232. pci_write_config_word(dev, master_port, master_data);
  233. }
  234. pci_write_config_byte(dev, 0x48, udma_enable);
  235. spin_unlock_irqrestore(&rdc_lock, flags);
  236. }
  237. static struct ata_port_operations rdc_pata_ops = {
  238. .inherits = &ata_bmdma32_port_ops,
  239. .cable_detect = rdc_pata_cable_detect,
  240. .set_piomode = rdc_set_piomode,
  241. .set_dmamode = rdc_set_dmamode,
  242. .prereset = rdc_pata_prereset,
  243. };
  244. static const struct ata_port_info rdc_port_info = {
  245. .flags = ATA_FLAG_SLAVE_POSS,
  246. .pio_mask = ATA_PIO4,
  247. .mwdma_mask = ATA_MWDMA12_ONLY,
  248. .udma_mask = ATA_UDMA5,
  249. .port_ops = &rdc_pata_ops,
  250. };
  251. static struct scsi_host_template rdc_sht = {
  252. ATA_BMDMA_SHT(DRV_NAME),
  253. };
  254. /**
  255. * rdc_init_one - Register PIIX ATA PCI device with kernel services
  256. * @pdev: PCI device to register
  257. * @ent: Entry in rdc_pci_tbl matching with @pdev
  258. *
  259. * Called from kernel PCI layer. We probe for combined mode (sigh),
  260. * and then hand over control to libata, for it to do the rest.
  261. *
  262. * LOCKING:
  263. * Inherited from PCI layer (may sleep).
  264. *
  265. * RETURNS:
  266. * Zero on success, or -ERRNO value.
  267. */
  268. static int rdc_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
  269. {
  270. struct device *dev = &pdev->dev;
  271. struct ata_port_info port_info[2];
  272. const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
  273. struct ata_host *host;
  274. struct rdc_host_priv *hpriv;
  275. int rc;
  276. ata_print_version_once(&pdev->dev, DRV_VERSION);
  277. port_info[0] = rdc_port_info;
  278. port_info[1] = rdc_port_info;
  279. /* enable device and prepare host */
  280. rc = pcim_enable_device(pdev);
  281. if (rc)
  282. return rc;
  283. hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
  284. if (!hpriv)
  285. return -ENOMEM;
  286. /* Save IOCFG, this will be used for cable detection, quirk
  287. * detection and restoration on detach.
  288. */
  289. pci_read_config_dword(pdev, 0x54, &hpriv->saved_iocfg);
  290. rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
  291. if (rc)
  292. return rc;
  293. host->private_data = hpriv;
  294. pci_intx(pdev, 1);
  295. host->flags |= ATA_HOST_PARALLEL_SCAN;
  296. pci_set_master(pdev);
  297. return ata_pci_sff_activate_host(host, ata_bmdma_interrupt, &rdc_sht);
  298. }
  299. static void rdc_remove_one(struct pci_dev *pdev)
  300. {
  301. struct ata_host *host = pci_get_drvdata(pdev);
  302. struct rdc_host_priv *hpriv = host->private_data;
  303. pci_write_config_dword(pdev, 0x54, hpriv->saved_iocfg);
  304. ata_pci_remove_one(pdev);
  305. }
  306. static const struct pci_device_id rdc_pci_tbl[] = {
  307. { PCI_DEVICE(0x17F3, 0x1011), },
  308. { PCI_DEVICE(0x17F3, 0x1012), },
  309. { } /* terminate list */
  310. };
  311. static struct pci_driver rdc_pci_driver = {
  312. .name = DRV_NAME,
  313. .id_table = rdc_pci_tbl,
  314. .probe = rdc_init_one,
  315. .remove = rdc_remove_one,
  316. #ifdef CONFIG_PM_SLEEP
  317. .suspend = ata_pci_device_suspend,
  318. .resume = ata_pci_device_resume,
  319. #endif
  320. };
  321. module_pci_driver(rdc_pci_driver);
  322. MODULE_AUTHOR("Alan Cox (based on ata_piix)");
  323. MODULE_DESCRIPTION("SCSI low-level driver for RDC PATA controllers");
  324. MODULE_LICENSE("GPL");
  325. MODULE_DEVICE_TABLE(pci, rdc_pci_tbl);
  326. MODULE_VERSION(DRV_VERSION);