pata_pxa.c 7.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Generic PXA PATA driver
  4. *
  5. * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
  6. */
  7. #include <linux/kernel.h>
  8. #include <linux/module.h>
  9. #include <linux/blkdev.h>
  10. #include <linux/ata.h>
  11. #include <linux/libata.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/dmaengine.h>
  14. #include <linux/slab.h>
  15. #include <linux/completion.h>
  16. #include <scsi/scsi_host.h>
  17. #include <linux/platform_data/ata-pxa.h>
  18. #define DRV_NAME "pata_pxa"
  19. #define DRV_VERSION "0.1"
  20. struct pata_pxa_data {
  21. struct dma_chan *dma_chan;
  22. dma_cookie_t dma_cookie;
  23. struct completion dma_done;
  24. };
  25. /*
  26. * DMA interrupt handler.
  27. */
  28. static void pxa_ata_dma_irq(void *d)
  29. {
  30. struct pata_pxa_data *pd = d;
  31. enum dma_status status;
  32. status = dmaengine_tx_status(pd->dma_chan, pd->dma_cookie, NULL);
  33. if (status == DMA_ERROR || status == DMA_COMPLETE)
  34. complete(&pd->dma_done);
  35. }
  36. /*
  37. * Prepare taskfile for submission.
  38. */
  39. static enum ata_completion_errors pxa_qc_prep(struct ata_queued_cmd *qc)
  40. {
  41. struct pata_pxa_data *pd = qc->ap->private_data;
  42. struct dma_async_tx_descriptor *tx;
  43. enum dma_transfer_direction dir;
  44. if (!(qc->flags & ATA_QCFLAG_DMAMAP))
  45. return AC_ERR_OK;
  46. dir = (qc->dma_dir == DMA_TO_DEVICE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM);
  47. tx = dmaengine_prep_slave_sg(pd->dma_chan, qc->sg, qc->n_elem, dir,
  48. DMA_PREP_INTERRUPT);
  49. if (!tx) {
  50. ata_dev_err(qc->dev, "prep_slave_sg() failed\n");
  51. return AC_ERR_OK;
  52. }
  53. tx->callback = pxa_ata_dma_irq;
  54. tx->callback_param = pd;
  55. pd->dma_cookie = dmaengine_submit(tx);
  56. return AC_ERR_OK;
  57. }
  58. /*
  59. * Configure the DMA controller, load the DMA descriptors, but don't start the
  60. * DMA controller yet. Only issue the ATA command.
  61. */
  62. static void pxa_bmdma_setup(struct ata_queued_cmd *qc)
  63. {
  64. qc->ap->ops->sff_exec_command(qc->ap, &qc->tf);
  65. }
  66. /*
  67. * Execute the DMA transfer.
  68. */
  69. static void pxa_bmdma_start(struct ata_queued_cmd *qc)
  70. {
  71. struct pata_pxa_data *pd = qc->ap->private_data;
  72. init_completion(&pd->dma_done);
  73. dma_async_issue_pending(pd->dma_chan);
  74. }
  75. /*
  76. * Wait until the DMA transfer completes, then stop the DMA controller.
  77. */
  78. static void pxa_bmdma_stop(struct ata_queued_cmd *qc)
  79. {
  80. struct pata_pxa_data *pd = qc->ap->private_data;
  81. enum dma_status status;
  82. status = dmaengine_tx_status(pd->dma_chan, pd->dma_cookie, NULL);
  83. if (status != DMA_ERROR && status != DMA_COMPLETE &&
  84. wait_for_completion_timeout(&pd->dma_done, HZ))
  85. ata_dev_err(qc->dev, "Timeout waiting for DMA completion!");
  86. dmaengine_terminate_all(pd->dma_chan);
  87. }
  88. /*
  89. * Read DMA status. The bmdma_stop() will take care of properly finishing the
  90. * DMA transfer so we always have DMA-complete interrupt here.
  91. */
  92. static unsigned char pxa_bmdma_status(struct ata_port *ap)
  93. {
  94. struct pata_pxa_data *pd = ap->private_data;
  95. unsigned char ret = ATA_DMA_INTR;
  96. struct dma_tx_state state;
  97. enum dma_status status;
  98. status = dmaengine_tx_status(pd->dma_chan, pd->dma_cookie, &state);
  99. if (status != DMA_COMPLETE)
  100. ret |= ATA_DMA_ERR;
  101. return ret;
  102. }
  103. /*
  104. * No IRQ register present so we do nothing.
  105. */
  106. static void pxa_irq_clear(struct ata_port *ap)
  107. {
  108. }
  109. /*
  110. * Check for ATAPI DMA. ATAPI DMA is unsupported by this driver. It's still
  111. * unclear why ATAPI has DMA issues.
  112. */
  113. static int pxa_check_atapi_dma(struct ata_queued_cmd *qc)
  114. {
  115. return -EOPNOTSUPP;
  116. }
  117. static struct scsi_host_template pxa_ata_sht = {
  118. ATA_BMDMA_SHT(DRV_NAME),
  119. };
  120. static struct ata_port_operations pxa_ata_port_ops = {
  121. .inherits = &ata_bmdma_port_ops,
  122. .cable_detect = ata_cable_40wire,
  123. .bmdma_setup = pxa_bmdma_setup,
  124. .bmdma_start = pxa_bmdma_start,
  125. .bmdma_stop = pxa_bmdma_stop,
  126. .bmdma_status = pxa_bmdma_status,
  127. .check_atapi_dma = pxa_check_atapi_dma,
  128. .sff_irq_clear = pxa_irq_clear,
  129. .qc_prep = pxa_qc_prep,
  130. };
  131. static int pxa_ata_probe(struct platform_device *pdev)
  132. {
  133. struct ata_host *host;
  134. struct ata_port *ap;
  135. struct pata_pxa_data *data;
  136. struct resource *cmd_res;
  137. struct resource *ctl_res;
  138. struct resource *dma_res;
  139. struct resource *irq_res;
  140. struct pata_pxa_pdata *pdata = dev_get_platdata(&pdev->dev);
  141. struct dma_slave_config config;
  142. int ret = 0;
  143. /*
  144. * Resource validation, three resources are needed:
  145. * - CMD port base address
  146. * - CTL port base address
  147. * - DMA port base address
  148. * - IRQ pin
  149. */
  150. if (pdev->num_resources != 4) {
  151. dev_err(&pdev->dev, "invalid number of resources\n");
  152. return -EINVAL;
  153. }
  154. /*
  155. * CMD port base address
  156. */
  157. cmd_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  158. if (unlikely(cmd_res == NULL))
  159. return -EINVAL;
  160. /*
  161. * CTL port base address
  162. */
  163. ctl_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  164. if (unlikely(ctl_res == NULL))
  165. return -EINVAL;
  166. /*
  167. * DMA port base address
  168. */
  169. dma_res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
  170. if (unlikely(dma_res == NULL))
  171. return -EINVAL;
  172. /*
  173. * IRQ pin
  174. */
  175. irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  176. if (unlikely(irq_res == NULL))
  177. return -EINVAL;
  178. /*
  179. * Allocate the host
  180. */
  181. host = ata_host_alloc(&pdev->dev, 1);
  182. if (!host)
  183. return -ENOMEM;
  184. ap = host->ports[0];
  185. ap->ops = &pxa_ata_port_ops;
  186. ap->pio_mask = ATA_PIO4;
  187. ap->mwdma_mask = ATA_MWDMA2;
  188. ap->ioaddr.cmd_addr = devm_ioremap(&pdev->dev, cmd_res->start,
  189. resource_size(cmd_res));
  190. ap->ioaddr.ctl_addr = devm_ioremap(&pdev->dev, ctl_res->start,
  191. resource_size(ctl_res));
  192. ap->ioaddr.bmdma_addr = devm_ioremap(&pdev->dev, dma_res->start,
  193. resource_size(dma_res));
  194. /*
  195. * Adjust register offsets
  196. */
  197. ap->ioaddr.altstatus_addr = ap->ioaddr.ctl_addr;
  198. ap->ioaddr.data_addr = ap->ioaddr.cmd_addr +
  199. (ATA_REG_DATA << pdata->reg_shift);
  200. ap->ioaddr.error_addr = ap->ioaddr.cmd_addr +
  201. (ATA_REG_ERR << pdata->reg_shift);
  202. ap->ioaddr.feature_addr = ap->ioaddr.cmd_addr +
  203. (ATA_REG_FEATURE << pdata->reg_shift);
  204. ap->ioaddr.nsect_addr = ap->ioaddr.cmd_addr +
  205. (ATA_REG_NSECT << pdata->reg_shift);
  206. ap->ioaddr.lbal_addr = ap->ioaddr.cmd_addr +
  207. (ATA_REG_LBAL << pdata->reg_shift);
  208. ap->ioaddr.lbam_addr = ap->ioaddr.cmd_addr +
  209. (ATA_REG_LBAM << pdata->reg_shift);
  210. ap->ioaddr.lbah_addr = ap->ioaddr.cmd_addr +
  211. (ATA_REG_LBAH << pdata->reg_shift);
  212. ap->ioaddr.device_addr = ap->ioaddr.cmd_addr +
  213. (ATA_REG_DEVICE << pdata->reg_shift);
  214. ap->ioaddr.status_addr = ap->ioaddr.cmd_addr +
  215. (ATA_REG_STATUS << pdata->reg_shift);
  216. ap->ioaddr.command_addr = ap->ioaddr.cmd_addr +
  217. (ATA_REG_CMD << pdata->reg_shift);
  218. /*
  219. * Allocate and load driver's internal data structure
  220. */
  221. data = devm_kzalloc(&pdev->dev, sizeof(struct pata_pxa_data),
  222. GFP_KERNEL);
  223. if (!data)
  224. return -ENOMEM;
  225. ap->private_data = data;
  226. memset(&config, 0, sizeof(config));
  227. config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
  228. config.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
  229. config.src_addr = dma_res->start;
  230. config.dst_addr = dma_res->start;
  231. config.src_maxburst = 32;
  232. config.dst_maxburst = 32;
  233. /*
  234. * Request the DMA channel
  235. */
  236. data->dma_chan =
  237. dma_request_slave_channel(&pdev->dev, "data");
  238. if (!data->dma_chan)
  239. return -EBUSY;
  240. ret = dmaengine_slave_config(data->dma_chan, &config);
  241. if (ret < 0) {
  242. dev_err(&pdev->dev, "dma configuration failed: %d\n", ret);
  243. return ret;
  244. }
  245. /*
  246. * Activate the ATA host
  247. */
  248. ret = ata_host_activate(host, irq_res->start, ata_sff_interrupt,
  249. pdata->irq_flags, &pxa_ata_sht);
  250. if (ret)
  251. dma_release_channel(data->dma_chan);
  252. return ret;
  253. }
  254. static int pxa_ata_remove(struct platform_device *pdev)
  255. {
  256. struct ata_host *host = platform_get_drvdata(pdev);
  257. struct pata_pxa_data *data = host->ports[0]->private_data;
  258. dma_release_channel(data->dma_chan);
  259. ata_host_detach(host);
  260. return 0;
  261. }
  262. static struct platform_driver pxa_ata_driver = {
  263. .probe = pxa_ata_probe,
  264. .remove = pxa_ata_remove,
  265. .driver = {
  266. .name = DRV_NAME,
  267. },
  268. };
  269. module_platform_driver(pxa_ata_driver);
  270. MODULE_AUTHOR("Marek Vasut <marek.vasut@gmail.com>");
  271. MODULE_DESCRIPTION("DMA-capable driver for PATA on PXA CPU");
  272. MODULE_LICENSE("GPL");
  273. MODULE_VERSION(DRV_VERSION);
  274. MODULE_ALIAS("platform:" DRV_NAME);