pata_optidma.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * pata_optidma.c - Opti DMA PATA for new ATA layer
  4. * (C) 2006 Red Hat Inc
  5. *
  6. * The Opti DMA controllers are related to the older PIO PCI controllers
  7. * and indeed the VLB ones. The main differences are that the timing
  8. * numbers are now based off PCI clocks not VLB and differ, and that
  9. * MWDMA is supported.
  10. *
  11. * This driver should support Viper-N+, FireStar, FireStar Plus.
  12. *
  13. * These devices support virtual DMA for read (aka the CS5520). Later
  14. * chips support UDMA33, but only if the rest of the board logic does,
  15. * so you have to get this right. We don't support the virtual DMA
  16. * but we do handle UDMA.
  17. *
  18. * Bits that are worth knowing
  19. * Most control registers are shadowed into I/O registers
  20. * 0x1F5 bit 0 tells you if the PCI/VLB clock is 33 or 25Mhz
  21. * Virtual DMA registers *move* between rev 0x02 and rev 0x10
  22. * UDMA requires a 66MHz FSB
  23. *
  24. */
  25. #include <linux/kernel.h>
  26. #include <linux/module.h>
  27. #include <linux/pci.h>
  28. #include <linux/blkdev.h>
  29. #include <linux/delay.h>
  30. #include <scsi/scsi_host.h>
  31. #include <linux/libata.h>
  32. #define DRV_NAME "pata_optidma"
  33. #define DRV_VERSION "0.3.2"
  34. enum {
  35. READ_REG = 0, /* index of Read cycle timing register */
  36. WRITE_REG = 1, /* index of Write cycle timing register */
  37. CNTRL_REG = 3, /* index of Control register */
  38. STRAP_REG = 5, /* index of Strap register */
  39. MISC_REG = 6 /* index of Miscellaneous register */
  40. };
  41. static int pci_clock; /* 0 = 33 1 = 25 */
  42. /**
  43. * optidma_pre_reset - probe begin
  44. * @link: ATA link
  45. * @deadline: deadline jiffies for the operation
  46. *
  47. * Set up cable type and use generic probe init
  48. */
  49. static int optidma_pre_reset(struct ata_link *link, unsigned long deadline)
  50. {
  51. struct ata_port *ap = link->ap;
  52. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  53. static const struct pci_bits optidma_enable_bits = {
  54. 0x40, 1, 0x08, 0x00
  55. };
  56. if (ap->port_no && !pci_test_config_bits(pdev, &optidma_enable_bits))
  57. return -ENOENT;
  58. return ata_sff_prereset(link, deadline);
  59. }
  60. /**
  61. * optidma_unlock - unlock control registers
  62. * @ap: ATA port
  63. *
  64. * Unlock the control register block for this adapter. Registers must not
  65. * be unlocked in a situation where libata might look at them.
  66. */
  67. static void optidma_unlock(struct ata_port *ap)
  68. {
  69. void __iomem *regio = ap->ioaddr.cmd_addr;
  70. /* These 3 unlock the control register access */
  71. ioread16(regio + 1);
  72. ioread16(regio + 1);
  73. iowrite8(3, regio + 2);
  74. }
  75. /**
  76. * optidma_lock - issue temporary relock
  77. * @ap: ATA port
  78. *
  79. * Re-lock the configuration register settings.
  80. */
  81. static void optidma_lock(struct ata_port *ap)
  82. {
  83. void __iomem *regio = ap->ioaddr.cmd_addr;
  84. /* Relock */
  85. iowrite8(0x83, regio + 2);
  86. }
  87. /**
  88. * optidma_mode_setup - set mode data
  89. * @ap: ATA interface
  90. * @adev: ATA device
  91. * @mode: Mode to set
  92. *
  93. * Called to do the DMA or PIO mode setup. Timing numbers are all
  94. * pre computed to keep the code clean. There are two tables depending
  95. * on the hardware clock speed.
  96. *
  97. * WARNING: While we do this the IDE registers vanish. If we take an
  98. * IRQ here we depend on the host set locking to avoid catastrophe.
  99. */
  100. static void optidma_mode_setup(struct ata_port *ap, struct ata_device *adev, u8 mode)
  101. {
  102. struct ata_device *pair = ata_dev_pair(adev);
  103. int pio = adev->pio_mode - XFER_PIO_0;
  104. int dma = adev->dma_mode - XFER_MW_DMA_0;
  105. void __iomem *regio = ap->ioaddr.cmd_addr;
  106. u8 addr;
  107. /* Address table precomputed with a DCLK of 2 */
  108. static const u8 addr_timing[2][5] = {
  109. { 0x30, 0x20, 0x20, 0x10, 0x10 },
  110. { 0x20, 0x20, 0x10, 0x10, 0x10 }
  111. };
  112. static const u8 data_rec_timing[2][5] = {
  113. { 0x59, 0x46, 0x30, 0x20, 0x20 },
  114. { 0x46, 0x32, 0x20, 0x20, 0x10 }
  115. };
  116. static const u8 dma_data_rec_timing[2][3] = {
  117. { 0x76, 0x20, 0x20 },
  118. { 0x54, 0x20, 0x10 }
  119. };
  120. /* Switch from IDE to control mode */
  121. optidma_unlock(ap);
  122. /*
  123. * As with many controllers the address setup time is shared
  124. * and must suit both devices if present. FIXME: Check if we
  125. * need to look at slowest of PIO/DMA mode of either device
  126. */
  127. if (mode >= XFER_MW_DMA_0)
  128. addr = 0;
  129. else
  130. addr = addr_timing[pci_clock][pio];
  131. if (pair) {
  132. u8 pair_addr;
  133. /* Hardware constraint */
  134. if (pair->dma_mode)
  135. pair_addr = 0;
  136. else
  137. pair_addr = addr_timing[pci_clock][pair->pio_mode - XFER_PIO_0];
  138. if (pair_addr > addr)
  139. addr = pair_addr;
  140. }
  141. /* Commence primary programming sequence */
  142. /* First we load the device number into the timing select */
  143. iowrite8(adev->devno, regio + MISC_REG);
  144. /* Now we load the data timings into read data/write data */
  145. if (mode < XFER_MW_DMA_0) {
  146. iowrite8(data_rec_timing[pci_clock][pio], regio + READ_REG);
  147. iowrite8(data_rec_timing[pci_clock][pio], regio + WRITE_REG);
  148. } else if (mode < XFER_UDMA_0) {
  149. iowrite8(dma_data_rec_timing[pci_clock][dma], regio + READ_REG);
  150. iowrite8(dma_data_rec_timing[pci_clock][dma], regio + WRITE_REG);
  151. }
  152. /* Finally we load the address setup into the misc register */
  153. iowrite8(addr | adev->devno, regio + MISC_REG);
  154. /* Programming sequence complete, timing 0 dev 0, timing 1 dev 1 */
  155. iowrite8(0x85, regio + CNTRL_REG);
  156. /* Switch back to IDE mode */
  157. optidma_lock(ap);
  158. /* Note: at this point our programming is incomplete. We are
  159. not supposed to program PCI 0x43 "things we hacked onto the chip"
  160. until we've done both sets of PIO/DMA timings */
  161. }
  162. /**
  163. * optiplus_mode_setup - DMA setup for Firestar Plus
  164. * @ap: ATA port
  165. * @adev: device
  166. * @mode: desired mode
  167. *
  168. * The Firestar plus has additional UDMA functionality for UDMA0-2 and
  169. * requires we do some additional work. Because the base work we must do
  170. * is mostly shared we wrap the Firestar setup functionality in this
  171. * one
  172. */
  173. static void optiplus_mode_setup(struct ata_port *ap, struct ata_device *adev, u8 mode)
  174. {
  175. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  176. u8 udcfg;
  177. u8 udslave;
  178. int dev2 = 2 * adev->devno;
  179. int unit = 2 * ap->port_no + adev->devno;
  180. int udma = mode - XFER_UDMA_0;
  181. pci_read_config_byte(pdev, 0x44, &udcfg);
  182. if (mode <= XFER_UDMA_0) {
  183. udcfg &= ~(1 << unit);
  184. optidma_mode_setup(ap, adev, adev->dma_mode);
  185. } else {
  186. udcfg |= (1 << unit);
  187. if (ap->port_no) {
  188. pci_read_config_byte(pdev, 0x45, &udslave);
  189. udslave &= ~(0x03 << dev2);
  190. udslave |= (udma << dev2);
  191. pci_write_config_byte(pdev, 0x45, udslave);
  192. } else {
  193. udcfg &= ~(0x30 << dev2);
  194. udcfg |= (udma << dev2);
  195. }
  196. }
  197. pci_write_config_byte(pdev, 0x44, udcfg);
  198. }
  199. /**
  200. * optidma_set_pio_mode - PIO setup callback
  201. * @ap: ATA port
  202. * @adev: Device
  203. *
  204. * The libata core provides separate functions for handling PIO and
  205. * DMA programming. The architecture of the Firestar makes it easier
  206. * for us to have a common function so we provide wrappers
  207. */
  208. static void optidma_set_pio_mode(struct ata_port *ap, struct ata_device *adev)
  209. {
  210. optidma_mode_setup(ap, adev, adev->pio_mode);
  211. }
  212. /**
  213. * optidma_set_dma_mode - DMA setup callback
  214. * @ap: ATA port
  215. * @adev: Device
  216. *
  217. * The libata core provides separate functions for handling PIO and
  218. * DMA programming. The architecture of the Firestar makes it easier
  219. * for us to have a common function so we provide wrappers
  220. */
  221. static void optidma_set_dma_mode(struct ata_port *ap, struct ata_device *adev)
  222. {
  223. optidma_mode_setup(ap, adev, adev->dma_mode);
  224. }
  225. /**
  226. * optiplus_set_pio_mode - PIO setup callback
  227. * @ap: ATA port
  228. * @adev: Device
  229. *
  230. * The libata core provides separate functions for handling PIO and
  231. * DMA programming. The architecture of the Firestar makes it easier
  232. * for us to have a common function so we provide wrappers
  233. */
  234. static void optiplus_set_pio_mode(struct ata_port *ap, struct ata_device *adev)
  235. {
  236. optiplus_mode_setup(ap, adev, adev->pio_mode);
  237. }
  238. /**
  239. * optiplus_set_dma_mode - DMA setup callback
  240. * @ap: ATA port
  241. * @adev: Device
  242. *
  243. * The libata core provides separate functions for handling PIO and
  244. * DMA programming. The architecture of the Firestar makes it easier
  245. * for us to have a common function so we provide wrappers
  246. */
  247. static void optiplus_set_dma_mode(struct ata_port *ap, struct ata_device *adev)
  248. {
  249. optiplus_mode_setup(ap, adev, adev->dma_mode);
  250. }
  251. /**
  252. * optidma_make_bits - PCI setup helper
  253. * @adev: ATA device
  254. *
  255. * Turn the ATA device setup into PCI configuration bits
  256. * for register 0x43 and return the two bits needed.
  257. */
  258. static u8 optidma_make_bits43(struct ata_device *adev)
  259. {
  260. static const u8 bits43[5] = {
  261. 0, 0, 0, 1, 2
  262. };
  263. if (!ata_dev_enabled(adev))
  264. return 0;
  265. if (adev->dma_mode)
  266. return adev->dma_mode - XFER_MW_DMA_0;
  267. return bits43[adev->pio_mode - XFER_PIO_0];
  268. }
  269. /**
  270. * optidma_set_mode - mode setup
  271. * @link: link to set up
  272. *
  273. * Use the standard setup to tune the chipset and then finalise the
  274. * configuration by writing the nibble of extra bits of data into
  275. * the chip.
  276. */
  277. static int optidma_set_mode(struct ata_link *link, struct ata_device **r_failed)
  278. {
  279. struct ata_port *ap = link->ap;
  280. u8 r;
  281. int nybble = 4 * ap->port_no;
  282. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  283. int rc = ata_do_set_mode(link, r_failed);
  284. if (rc == 0) {
  285. pci_read_config_byte(pdev, 0x43, &r);
  286. r &= (0x0F << nybble);
  287. r |= (optidma_make_bits43(&link->device[0]) +
  288. (optidma_make_bits43(&link->device[0]) << 2)) << nybble;
  289. pci_write_config_byte(pdev, 0x43, r);
  290. }
  291. return rc;
  292. }
  293. static struct scsi_host_template optidma_sht = {
  294. ATA_BMDMA_SHT(DRV_NAME),
  295. };
  296. static struct ata_port_operations optidma_port_ops = {
  297. .inherits = &ata_bmdma_port_ops,
  298. .cable_detect = ata_cable_40wire,
  299. .set_piomode = optidma_set_pio_mode,
  300. .set_dmamode = optidma_set_dma_mode,
  301. .set_mode = optidma_set_mode,
  302. .prereset = optidma_pre_reset,
  303. };
  304. static struct ata_port_operations optiplus_port_ops = {
  305. .inherits = &optidma_port_ops,
  306. .set_piomode = optiplus_set_pio_mode,
  307. .set_dmamode = optiplus_set_dma_mode,
  308. };
  309. /**
  310. * optiplus_with_udma - Look for UDMA capable setup
  311. * @pdev; ATA controller
  312. */
  313. static int optiplus_with_udma(struct pci_dev *pdev)
  314. {
  315. u8 r;
  316. int ret = 0;
  317. int ioport = 0x22;
  318. struct pci_dev *dev1;
  319. /* Find function 1 */
  320. dev1 = pci_get_device(0x1045, 0xC701, NULL);
  321. if (dev1 == NULL)
  322. return 0;
  323. /* Rev must be >= 0x10 */
  324. pci_read_config_byte(dev1, 0x08, &r);
  325. if (r < 0x10)
  326. goto done_nomsg;
  327. /* Read the chipset system configuration to check our mode */
  328. pci_read_config_byte(dev1, 0x5F, &r);
  329. ioport |= (r << 8);
  330. outb(0x10, ioport);
  331. /* Must be 66Mhz sync */
  332. if ((inb(ioport + 2) & 1) == 0)
  333. goto done;
  334. /* Check the ATA arbitration/timing is suitable */
  335. pci_read_config_byte(pdev, 0x42, &r);
  336. if ((r & 0x36) != 0x36)
  337. goto done;
  338. pci_read_config_byte(dev1, 0x52, &r);
  339. if (r & 0x80) /* IDEDIR disabled */
  340. ret = 1;
  341. done:
  342. printk(KERN_WARNING "UDMA not supported in this configuration.\n");
  343. done_nomsg: /* Wrong chip revision */
  344. pci_dev_put(dev1);
  345. return ret;
  346. }
  347. static int optidma_init_one(struct pci_dev *dev, const struct pci_device_id *id)
  348. {
  349. static const struct ata_port_info info_82c700 = {
  350. .flags = ATA_FLAG_SLAVE_POSS,
  351. .pio_mask = ATA_PIO4,
  352. .mwdma_mask = ATA_MWDMA2,
  353. .port_ops = &optidma_port_ops
  354. };
  355. static const struct ata_port_info info_82c700_udma = {
  356. .flags = ATA_FLAG_SLAVE_POSS,
  357. .pio_mask = ATA_PIO4,
  358. .mwdma_mask = ATA_MWDMA2,
  359. .udma_mask = ATA_UDMA2,
  360. .port_ops = &optiplus_port_ops
  361. };
  362. const struct ata_port_info *ppi[] = { &info_82c700, NULL };
  363. int rc;
  364. ata_print_version_once(&dev->dev, DRV_VERSION);
  365. rc = pcim_enable_device(dev);
  366. if (rc)
  367. return rc;
  368. /* Fixed location chipset magic */
  369. inw(0x1F1);
  370. inw(0x1F1);
  371. pci_clock = inb(0x1F5) & 1; /* 0 = 33Mhz, 1 = 25Mhz */
  372. if (optiplus_with_udma(dev))
  373. ppi[0] = &info_82c700_udma;
  374. return ata_pci_bmdma_init_one(dev, ppi, &optidma_sht, NULL, 0);
  375. }
  376. static const struct pci_device_id optidma[] = {
  377. { PCI_VDEVICE(OPTI, 0xD568), }, /* Opti 82C700 */
  378. { },
  379. };
  380. static struct pci_driver optidma_pci_driver = {
  381. .name = DRV_NAME,
  382. .id_table = optidma,
  383. .probe = optidma_init_one,
  384. .remove = ata_pci_remove_one,
  385. #ifdef CONFIG_PM_SLEEP
  386. .suspend = ata_pci_device_suspend,
  387. .resume = ata_pci_device_resume,
  388. #endif
  389. };
  390. module_pci_driver(optidma_pci_driver);
  391. MODULE_AUTHOR("Alan Cox");
  392. MODULE_DESCRIPTION("low-level driver for Opti Firestar/Firestar Plus");
  393. MODULE_LICENSE("GPL");
  394. MODULE_DEVICE_TABLE(pci, optidma);
  395. MODULE_VERSION(DRV_VERSION);