pata_mpc52xx.c 25 KB

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  1. /*
  2. * drivers/ata/pata_mpc52xx.c
  3. *
  4. * libata driver for the Freescale MPC52xx on-chip IDE interface
  5. *
  6. * Copyright (C) 2006 Sylvain Munaut <tnt@246tNt.com>
  7. * Copyright (C) 2003 Mipsys - Benjamin Herrenschmidt
  8. *
  9. * UDMA support based on patches by Freescale (Bernard Kuhn, John Rigby),
  10. * Domen Puncer and Tim Yamin.
  11. *
  12. * This file is licensed under the terms of the GNU General Public License
  13. * version 2. This program is licensed "as is" without any warranty of any
  14. * kind, whether express or implied.
  15. */
  16. #include <linux/kernel.h>
  17. #include <linux/module.h>
  18. #include <linux/gfp.h>
  19. #include <linux/delay.h>
  20. #include <linux/libata.h>
  21. #include <linux/of_platform.h>
  22. #include <linux/types.h>
  23. #include <asm/cacheflush.h>
  24. #include <asm/prom.h>
  25. #include <asm/mpc52xx.h>
  26. #include <linux/fsl/bestcomm/bestcomm.h>
  27. #include <linux/fsl/bestcomm/bestcomm_priv.h>
  28. #include <linux/fsl/bestcomm/ata.h>
  29. #define DRV_NAME "mpc52xx_ata"
  30. /* Private structures used by the driver */
  31. struct mpc52xx_ata_timings {
  32. u32 pio1;
  33. u32 pio2;
  34. u32 mdma1;
  35. u32 mdma2;
  36. u32 udma1;
  37. u32 udma2;
  38. u32 udma3;
  39. u32 udma4;
  40. u32 udma5;
  41. int using_udma;
  42. };
  43. struct mpc52xx_ata_priv {
  44. unsigned int ipb_period;
  45. struct mpc52xx_ata __iomem *ata_regs;
  46. phys_addr_t ata_regs_pa;
  47. int ata_irq;
  48. struct mpc52xx_ata_timings timings[2];
  49. int csel;
  50. /* DMA */
  51. struct bcom_task *dmatsk;
  52. const struct udmaspec *udmaspec;
  53. const struct mdmaspec *mdmaspec;
  54. int mpc52xx_ata_dma_last_write;
  55. int waiting_for_dma;
  56. };
  57. /* ATAPI-4 PIO specs (in ns) */
  58. static const u16 ataspec_t0[5] = {600, 383, 240, 180, 120};
  59. static const u16 ataspec_t1[5] = { 70, 50, 30, 30, 25};
  60. static const u16 ataspec_t2_8[5] = {290, 290, 290, 80, 70};
  61. static const u16 ataspec_t2_16[5] = {165, 125, 100, 80, 70};
  62. static const u16 ataspec_t2i[5] = { 0, 0, 0, 70, 25};
  63. static const u16 ataspec_t4[5] = { 30, 20, 15, 10, 10};
  64. static const u16 ataspec_ta[5] = { 35, 35, 35, 35, 35};
  65. #define CALC_CLKCYC(c,v) ((((v)+(c)-1)/(c)))
  66. /* ======================================================================== */
  67. /* ATAPI-4 MDMA specs (in clocks) */
  68. struct mdmaspec {
  69. u8 t0M;
  70. u8 td;
  71. u8 th;
  72. u8 tj;
  73. u8 tkw;
  74. u8 tm;
  75. u8 tn;
  76. };
  77. static const struct mdmaspec mdmaspec66[3] = {
  78. { .t0M = 32, .td = 15, .th = 2, .tj = 2, .tkw = 15, .tm = 4, .tn = 1 },
  79. { .t0M = 10, .td = 6, .th = 1, .tj = 1, .tkw = 4, .tm = 2, .tn = 1 },
  80. { .t0M = 8, .td = 5, .th = 1, .tj = 1, .tkw = 2, .tm = 2, .tn = 1 },
  81. };
  82. static const struct mdmaspec mdmaspec132[3] = {
  83. { .t0M = 64, .td = 29, .th = 3, .tj = 3, .tkw = 29, .tm = 7, .tn = 2 },
  84. { .t0M = 20, .td = 11, .th = 2, .tj = 1, .tkw = 7, .tm = 4, .tn = 1 },
  85. { .t0M = 16, .td = 10, .th = 2, .tj = 1, .tkw = 4, .tm = 4, .tn = 1 },
  86. };
  87. /* ATAPI-4 UDMA specs (in clocks) */
  88. struct udmaspec {
  89. u8 tcyc;
  90. u8 t2cyc;
  91. u8 tds;
  92. u8 tdh;
  93. u8 tdvs;
  94. u8 tdvh;
  95. u8 tfs;
  96. u8 tli;
  97. u8 tmli;
  98. u8 taz;
  99. u8 tzah;
  100. u8 tenv;
  101. u8 tsr;
  102. u8 trfs;
  103. u8 trp;
  104. u8 tack;
  105. u8 tss;
  106. };
  107. static const struct udmaspec udmaspec66[6] = {
  108. { .tcyc = 8, .t2cyc = 16, .tds = 1, .tdh = 1, .tdvs = 5, .tdvh = 1,
  109. .tfs = 16, .tli = 10, .tmli = 2, .taz = 1, .tzah = 2, .tenv = 2,
  110. .tsr = 3, .trfs = 5, .trp = 11, .tack = 2, .tss = 4,
  111. },
  112. { .tcyc = 5, .t2cyc = 11, .tds = 1, .tdh = 1, .tdvs = 4, .tdvh = 1,
  113. .tfs = 14, .tli = 10, .tmli = 2, .taz = 1, .tzah = 2, .tenv = 2,
  114. .tsr = 2, .trfs = 5, .trp = 9, .tack = 2, .tss = 4,
  115. },
  116. { .tcyc = 4, .t2cyc = 8, .tds = 1, .tdh = 1, .tdvs = 3, .tdvh = 1,
  117. .tfs = 12, .tli = 10, .tmli = 2, .taz = 1, .tzah = 2, .tenv = 2,
  118. .tsr = 2, .trfs = 4, .trp = 7, .tack = 2, .tss = 4,
  119. },
  120. { .tcyc = 3, .t2cyc = 6, .tds = 1, .tdh = 1, .tdvs = 2, .tdvh = 1,
  121. .tfs = 9, .tli = 7, .tmli = 2, .taz = 1, .tzah = 2, .tenv = 2,
  122. .tsr = 2, .trfs = 4, .trp = 7, .tack = 2, .tss = 4,
  123. },
  124. { .tcyc = 2, .t2cyc = 4, .tds = 1, .tdh = 1, .tdvs = 1, .tdvh = 1,
  125. .tfs = 8, .tli = 8, .tmli = 2, .taz = 1, .tzah = 2, .tenv = 2,
  126. .tsr = 2, .trfs = 4, .trp = 7, .tack = 2, .tss = 4,
  127. },
  128. { .tcyc = 2, .t2cyc = 2, .tds = 1, .tdh = 1, .tdvs = 1, .tdvh = 1,
  129. .tfs = 6, .tli = 5, .tmli = 2, .taz = 1, .tzah = 2, .tenv = 2,
  130. .tsr = 2, .trfs = 4, .trp = 6, .tack = 2, .tss = 4,
  131. },
  132. };
  133. static const struct udmaspec udmaspec132[6] = {
  134. { .tcyc = 15, .t2cyc = 31, .tds = 2, .tdh = 1, .tdvs = 10, .tdvh = 1,
  135. .tfs = 30, .tli = 20, .tmli = 3, .taz = 2, .tzah = 3, .tenv = 3,
  136. .tsr = 7, .trfs = 10, .trp = 22, .tack = 3, .tss = 7,
  137. },
  138. { .tcyc = 10, .t2cyc = 21, .tds = 2, .tdh = 1, .tdvs = 7, .tdvh = 1,
  139. .tfs = 27, .tli = 20, .tmli = 3, .taz = 2, .tzah = 3, .tenv = 3,
  140. .tsr = 4, .trfs = 10, .trp = 17, .tack = 3, .tss = 7,
  141. },
  142. { .tcyc = 6, .t2cyc = 12, .tds = 1, .tdh = 1, .tdvs = 5, .tdvh = 1,
  143. .tfs = 23, .tli = 20, .tmli = 3, .taz = 2, .tzah = 3, .tenv = 3,
  144. .tsr = 3, .trfs = 8, .trp = 14, .tack = 3, .tss = 7,
  145. },
  146. { .tcyc = 7, .t2cyc = 12, .tds = 1, .tdh = 1, .tdvs = 3, .tdvh = 1,
  147. .tfs = 15, .tli = 13, .tmli = 3, .taz = 2, .tzah = 3, .tenv = 3,
  148. .tsr = 3, .trfs = 8, .trp = 14, .tack = 3, .tss = 7,
  149. },
  150. { .tcyc = 2, .t2cyc = 5, .tds = 0, .tdh = 0, .tdvs = 1, .tdvh = 1,
  151. .tfs = 16, .tli = 14, .tmli = 2, .taz = 1, .tzah = 2, .tenv = 2,
  152. .tsr = 2, .trfs = 7, .trp = 13, .tack = 2, .tss = 6,
  153. },
  154. { .tcyc = 3, .t2cyc = 6, .tds = 1, .tdh = 1, .tdvs = 1, .tdvh = 1,
  155. .tfs = 12, .tli = 10, .tmli = 3, .taz = 2, .tzah = 3, .tenv = 3,
  156. .tsr = 3, .trfs = 7, .trp = 12, .tack = 3, .tss = 7,
  157. },
  158. };
  159. /* ======================================================================== */
  160. /* Bit definitions inside the registers */
  161. #define MPC52xx_ATA_HOSTCONF_SMR 0x80000000UL /* State machine reset */
  162. #define MPC52xx_ATA_HOSTCONF_FR 0x40000000UL /* FIFO Reset */
  163. #define MPC52xx_ATA_HOSTCONF_IE 0x02000000UL /* Enable interrupt in PIO */
  164. #define MPC52xx_ATA_HOSTCONF_IORDY 0x01000000UL /* Drive supports IORDY protocol */
  165. #define MPC52xx_ATA_HOSTSTAT_TIP 0x80000000UL /* Transaction in progress */
  166. #define MPC52xx_ATA_HOSTSTAT_UREP 0x40000000UL /* UDMA Read Extended Pause */
  167. #define MPC52xx_ATA_HOSTSTAT_RERR 0x02000000UL /* Read Error */
  168. #define MPC52xx_ATA_HOSTSTAT_WERR 0x01000000UL /* Write Error */
  169. #define MPC52xx_ATA_FIFOSTAT_EMPTY 0x01 /* FIFO Empty */
  170. #define MPC52xx_ATA_FIFOSTAT_ERROR 0x40 /* FIFO Error */
  171. #define MPC52xx_ATA_DMAMODE_WRITE 0x01 /* Write DMA */
  172. #define MPC52xx_ATA_DMAMODE_READ 0x02 /* Read DMA */
  173. #define MPC52xx_ATA_DMAMODE_UDMA 0x04 /* UDMA enabled */
  174. #define MPC52xx_ATA_DMAMODE_IE 0x08 /* Enable drive interrupt to CPU in DMA mode */
  175. #define MPC52xx_ATA_DMAMODE_FE 0x10 /* FIFO Flush enable in Rx mode */
  176. #define MPC52xx_ATA_DMAMODE_FR 0x20 /* FIFO Reset */
  177. #define MPC52xx_ATA_DMAMODE_HUT 0x40 /* Host UDMA burst terminate */
  178. #define MAX_DMA_BUFFERS 128
  179. #define MAX_DMA_BUFFER_SIZE 0x20000u
  180. /* Structure of the hardware registers */
  181. struct mpc52xx_ata {
  182. /* Host interface registers */
  183. u32 config; /* ATA + 0x00 Host configuration */
  184. u32 host_status; /* ATA + 0x04 Host controller status */
  185. u32 pio1; /* ATA + 0x08 PIO Timing 1 */
  186. u32 pio2; /* ATA + 0x0c PIO Timing 2 */
  187. u32 mdma1; /* ATA + 0x10 MDMA Timing 1 */
  188. u32 mdma2; /* ATA + 0x14 MDMA Timing 2 */
  189. u32 udma1; /* ATA + 0x18 UDMA Timing 1 */
  190. u32 udma2; /* ATA + 0x1c UDMA Timing 2 */
  191. u32 udma3; /* ATA + 0x20 UDMA Timing 3 */
  192. u32 udma4; /* ATA + 0x24 UDMA Timing 4 */
  193. u32 udma5; /* ATA + 0x28 UDMA Timing 5 */
  194. u32 share_cnt; /* ATA + 0x2c ATA share counter */
  195. u32 reserved0[3];
  196. /* FIFO registers */
  197. u32 fifo_data; /* ATA + 0x3c */
  198. u8 fifo_status_frame; /* ATA + 0x40 */
  199. u8 fifo_status; /* ATA + 0x41 */
  200. u16 reserved7[1];
  201. u8 fifo_control; /* ATA + 0x44 */
  202. u8 reserved8[5];
  203. u16 fifo_alarm; /* ATA + 0x4a */
  204. u16 reserved9;
  205. u16 fifo_rdp; /* ATA + 0x4e */
  206. u16 reserved10;
  207. u16 fifo_wrp; /* ATA + 0x52 */
  208. u16 reserved11;
  209. u16 fifo_lfrdp; /* ATA + 0x56 */
  210. u16 reserved12;
  211. u16 fifo_lfwrp; /* ATA + 0x5a */
  212. /* Drive TaskFile registers */
  213. u8 tf_control; /* ATA + 0x5c TASKFILE Control/Alt Status */
  214. u8 reserved13[3];
  215. u16 tf_data; /* ATA + 0x60 TASKFILE Data */
  216. u16 reserved14;
  217. u8 tf_features; /* ATA + 0x64 TASKFILE Features/Error */
  218. u8 reserved15[3];
  219. u8 tf_sec_count; /* ATA + 0x68 TASKFILE Sector Count */
  220. u8 reserved16[3];
  221. u8 tf_sec_num; /* ATA + 0x6c TASKFILE Sector Number */
  222. u8 reserved17[3];
  223. u8 tf_cyl_low; /* ATA + 0x70 TASKFILE Cylinder Low */
  224. u8 reserved18[3];
  225. u8 tf_cyl_high; /* ATA + 0x74 TASKFILE Cylinder High */
  226. u8 reserved19[3];
  227. u8 tf_dev_head; /* ATA + 0x78 TASKFILE Device/Head */
  228. u8 reserved20[3];
  229. u8 tf_command; /* ATA + 0x7c TASKFILE Command/Status */
  230. u8 dma_mode; /* ATA + 0x7d ATA Host DMA Mode configuration */
  231. u8 reserved21[2];
  232. };
  233. /* ======================================================================== */
  234. /* Aux fns */
  235. /* ======================================================================== */
  236. /* MPC52xx low level hw control */
  237. static int
  238. mpc52xx_ata_compute_pio_timings(struct mpc52xx_ata_priv *priv, int dev, int pio)
  239. {
  240. struct mpc52xx_ata_timings *timing = &priv->timings[dev];
  241. unsigned int ipb_period = priv->ipb_period;
  242. u32 t0, t1, t2_8, t2_16, t2i, t4, ta;
  243. if ((pio < 0) || (pio > 4))
  244. return -EINVAL;
  245. t0 = CALC_CLKCYC(ipb_period, 1000 * ataspec_t0[pio]);
  246. t1 = CALC_CLKCYC(ipb_period, 1000 * ataspec_t1[pio]);
  247. t2_8 = CALC_CLKCYC(ipb_period, 1000 * ataspec_t2_8[pio]);
  248. t2_16 = CALC_CLKCYC(ipb_period, 1000 * ataspec_t2_16[pio]);
  249. t2i = CALC_CLKCYC(ipb_period, 1000 * ataspec_t2i[pio]);
  250. t4 = CALC_CLKCYC(ipb_period, 1000 * ataspec_t4[pio]);
  251. ta = CALC_CLKCYC(ipb_period, 1000 * ataspec_ta[pio]);
  252. timing->pio1 = (t0 << 24) | (t2_8 << 16) | (t2_16 << 8) | (t2i);
  253. timing->pio2 = (t4 << 24) | (t1 << 16) | (ta << 8);
  254. return 0;
  255. }
  256. static int
  257. mpc52xx_ata_compute_mdma_timings(struct mpc52xx_ata_priv *priv, int dev,
  258. int speed)
  259. {
  260. struct mpc52xx_ata_timings *t = &priv->timings[dev];
  261. const struct mdmaspec *s = &priv->mdmaspec[speed];
  262. if (speed < 0 || speed > 2)
  263. return -EINVAL;
  264. t->mdma1 = ((u32)s->t0M << 24) | ((u32)s->td << 16) | ((u32)s->tkw << 8) | s->tm;
  265. t->mdma2 = ((u32)s->th << 24) | ((u32)s->tj << 16) | ((u32)s->tn << 8);
  266. t->using_udma = 0;
  267. return 0;
  268. }
  269. static int
  270. mpc52xx_ata_compute_udma_timings(struct mpc52xx_ata_priv *priv, int dev,
  271. int speed)
  272. {
  273. struct mpc52xx_ata_timings *t = &priv->timings[dev];
  274. const struct udmaspec *s = &priv->udmaspec[speed];
  275. if (speed < 0 || speed > 2)
  276. return -EINVAL;
  277. t->udma1 = ((u32)s->t2cyc << 24) | ((u32)s->tcyc << 16) | ((u32)s->tds << 8) | s->tdh;
  278. t->udma2 = ((u32)s->tdvs << 24) | ((u32)s->tdvh << 16) | ((u32)s->tfs << 8) | s->tli;
  279. t->udma3 = ((u32)s->tmli << 24) | ((u32)s->taz << 16) | ((u32)s->tenv << 8) | s->tsr;
  280. t->udma4 = ((u32)s->tss << 24) | ((u32)s->trfs << 16) | ((u32)s->trp << 8) | s->tack;
  281. t->udma5 = (u32)s->tzah << 24;
  282. t->using_udma = 1;
  283. return 0;
  284. }
  285. static void
  286. mpc52xx_ata_apply_timings(struct mpc52xx_ata_priv *priv, int device)
  287. {
  288. struct mpc52xx_ata __iomem *regs = priv->ata_regs;
  289. struct mpc52xx_ata_timings *timing = &priv->timings[device];
  290. out_be32(&regs->pio1, timing->pio1);
  291. out_be32(&regs->pio2, timing->pio2);
  292. out_be32(&regs->mdma1, timing->mdma1);
  293. out_be32(&regs->mdma2, timing->mdma2);
  294. out_be32(&regs->udma1, timing->udma1);
  295. out_be32(&regs->udma2, timing->udma2);
  296. out_be32(&regs->udma3, timing->udma3);
  297. out_be32(&regs->udma4, timing->udma4);
  298. out_be32(&regs->udma5, timing->udma5);
  299. priv->csel = device;
  300. }
  301. static int
  302. mpc52xx_ata_hw_init(struct mpc52xx_ata_priv *priv)
  303. {
  304. struct mpc52xx_ata __iomem *regs = priv->ata_regs;
  305. int tslot;
  306. /* Clear share_cnt (all sample code do this ...) */
  307. out_be32(&regs->share_cnt, 0);
  308. /* Configure and reset host */
  309. out_be32(&regs->config,
  310. MPC52xx_ATA_HOSTCONF_IE |
  311. MPC52xx_ATA_HOSTCONF_IORDY |
  312. MPC52xx_ATA_HOSTCONF_SMR |
  313. MPC52xx_ATA_HOSTCONF_FR);
  314. udelay(10);
  315. out_be32(&regs->config,
  316. MPC52xx_ATA_HOSTCONF_IE |
  317. MPC52xx_ATA_HOSTCONF_IORDY);
  318. /* Set the time slot to 1us */
  319. tslot = CALC_CLKCYC(priv->ipb_period, 1000000);
  320. out_be32(&regs->share_cnt, tslot << 16);
  321. /* Init timings to PIO0 */
  322. memset(priv->timings, 0x00, 2*sizeof(struct mpc52xx_ata_timings));
  323. mpc52xx_ata_compute_pio_timings(priv, 0, 0);
  324. mpc52xx_ata_compute_pio_timings(priv, 1, 0);
  325. mpc52xx_ata_apply_timings(priv, 0);
  326. return 0;
  327. }
  328. /* ======================================================================== */
  329. /* libata driver */
  330. /* ======================================================================== */
  331. static void
  332. mpc52xx_ata_set_piomode(struct ata_port *ap, struct ata_device *adev)
  333. {
  334. struct mpc52xx_ata_priv *priv = ap->host->private_data;
  335. int pio, rv;
  336. pio = adev->pio_mode - XFER_PIO_0;
  337. rv = mpc52xx_ata_compute_pio_timings(priv, adev->devno, pio);
  338. if (rv) {
  339. dev_err(ap->dev, "error: invalid PIO mode: %d\n", pio);
  340. return;
  341. }
  342. mpc52xx_ata_apply_timings(priv, adev->devno);
  343. }
  344. static void
  345. mpc52xx_ata_set_dmamode(struct ata_port *ap, struct ata_device *adev)
  346. {
  347. struct mpc52xx_ata_priv *priv = ap->host->private_data;
  348. int rv;
  349. if (adev->dma_mode >= XFER_UDMA_0) {
  350. int dma = adev->dma_mode - XFER_UDMA_0;
  351. rv = mpc52xx_ata_compute_udma_timings(priv, adev->devno, dma);
  352. } else {
  353. int dma = adev->dma_mode - XFER_MW_DMA_0;
  354. rv = mpc52xx_ata_compute_mdma_timings(priv, adev->devno, dma);
  355. }
  356. if (rv) {
  357. dev_alert(ap->dev,
  358. "Trying to select invalid DMA mode %d\n",
  359. adev->dma_mode);
  360. return;
  361. }
  362. mpc52xx_ata_apply_timings(priv, adev->devno);
  363. }
  364. static void
  365. mpc52xx_ata_dev_select(struct ata_port *ap, unsigned int device)
  366. {
  367. struct mpc52xx_ata_priv *priv = ap->host->private_data;
  368. if (device != priv->csel)
  369. mpc52xx_ata_apply_timings(priv, device);
  370. ata_sff_dev_select(ap, device);
  371. }
  372. static int
  373. mpc52xx_ata_build_dmatable(struct ata_queued_cmd *qc)
  374. {
  375. struct ata_port *ap = qc->ap;
  376. struct mpc52xx_ata_priv *priv = ap->host->private_data;
  377. struct bcom_ata_bd *bd;
  378. unsigned int read = !(qc->tf.flags & ATA_TFLAG_WRITE), si;
  379. struct scatterlist *sg;
  380. int count = 0;
  381. if (read)
  382. bcom_ata_rx_prepare(priv->dmatsk);
  383. else
  384. bcom_ata_tx_prepare(priv->dmatsk);
  385. for_each_sg(qc->sg, sg, qc->n_elem, si) {
  386. dma_addr_t cur_addr = sg_dma_address(sg);
  387. u32 cur_len = sg_dma_len(sg);
  388. while (cur_len) {
  389. unsigned int tc = min(cur_len, MAX_DMA_BUFFER_SIZE);
  390. bd = (struct bcom_ata_bd *)
  391. bcom_prepare_next_buffer(priv->dmatsk);
  392. if (read) {
  393. bd->status = tc;
  394. bd->src_pa = (__force u32) priv->ata_regs_pa +
  395. offsetof(struct mpc52xx_ata, fifo_data);
  396. bd->dst_pa = (__force u32) cur_addr;
  397. } else {
  398. bd->status = tc;
  399. bd->src_pa = (__force u32) cur_addr;
  400. bd->dst_pa = (__force u32) priv->ata_regs_pa +
  401. offsetof(struct mpc52xx_ata, fifo_data);
  402. }
  403. bcom_submit_next_buffer(priv->dmatsk, NULL);
  404. cur_addr += tc;
  405. cur_len -= tc;
  406. count++;
  407. if (count > MAX_DMA_BUFFERS) {
  408. dev_alert(ap->dev, "dma table"
  409. "too small\n");
  410. goto use_pio_instead;
  411. }
  412. }
  413. }
  414. return 1;
  415. use_pio_instead:
  416. bcom_ata_reset_bd(priv->dmatsk);
  417. return 0;
  418. }
  419. static void
  420. mpc52xx_bmdma_setup(struct ata_queued_cmd *qc)
  421. {
  422. struct ata_port *ap = qc->ap;
  423. struct mpc52xx_ata_priv *priv = ap->host->private_data;
  424. struct mpc52xx_ata __iomem *regs = priv->ata_regs;
  425. unsigned int read = !(qc->tf.flags & ATA_TFLAG_WRITE);
  426. u8 dma_mode;
  427. if (!mpc52xx_ata_build_dmatable(qc))
  428. dev_alert(ap->dev, "%s: %i, return 1?\n",
  429. __func__, __LINE__);
  430. /* Check FIFO is OK... */
  431. if (in_8(&priv->ata_regs->fifo_status) & MPC52xx_ATA_FIFOSTAT_ERROR)
  432. dev_alert(ap->dev, "%s: FIFO error detected: 0x%02x!\n",
  433. __func__, in_8(&priv->ata_regs->fifo_status));
  434. if (read) {
  435. dma_mode = MPC52xx_ATA_DMAMODE_IE | MPC52xx_ATA_DMAMODE_READ |
  436. MPC52xx_ATA_DMAMODE_FE;
  437. /* Setup FIFO if direction changed */
  438. if (priv->mpc52xx_ata_dma_last_write != 0) {
  439. priv->mpc52xx_ata_dma_last_write = 0;
  440. /* Configure FIFO with granularity to 7 */
  441. out_8(&regs->fifo_control, 7);
  442. out_be16(&regs->fifo_alarm, 128);
  443. /* Set FIFO Reset bit (FR) */
  444. out_8(&regs->dma_mode, MPC52xx_ATA_DMAMODE_FR);
  445. }
  446. } else {
  447. dma_mode = MPC52xx_ATA_DMAMODE_IE | MPC52xx_ATA_DMAMODE_WRITE;
  448. /* Setup FIFO if direction changed */
  449. if (priv->mpc52xx_ata_dma_last_write != 1) {
  450. priv->mpc52xx_ata_dma_last_write = 1;
  451. /* Configure FIFO with granularity to 4 */
  452. out_8(&regs->fifo_control, 4);
  453. out_be16(&regs->fifo_alarm, 128);
  454. }
  455. }
  456. if (priv->timings[qc->dev->devno].using_udma)
  457. dma_mode |= MPC52xx_ATA_DMAMODE_UDMA;
  458. out_8(&regs->dma_mode, dma_mode);
  459. priv->waiting_for_dma = ATA_DMA_ACTIVE;
  460. ata_wait_idle(ap);
  461. ap->ops->sff_exec_command(ap, &qc->tf);
  462. }
  463. static void
  464. mpc52xx_bmdma_start(struct ata_queued_cmd *qc)
  465. {
  466. struct ata_port *ap = qc->ap;
  467. struct mpc52xx_ata_priv *priv = ap->host->private_data;
  468. bcom_set_task_auto_start(priv->dmatsk->tasknum, priv->dmatsk->tasknum);
  469. bcom_enable(priv->dmatsk);
  470. }
  471. static void
  472. mpc52xx_bmdma_stop(struct ata_queued_cmd *qc)
  473. {
  474. struct ata_port *ap = qc->ap;
  475. struct mpc52xx_ata_priv *priv = ap->host->private_data;
  476. bcom_disable(priv->dmatsk);
  477. bcom_ata_reset_bd(priv->dmatsk);
  478. priv->waiting_for_dma = 0;
  479. /* Check FIFO is OK... */
  480. if (in_8(&priv->ata_regs->fifo_status) & MPC52xx_ATA_FIFOSTAT_ERROR)
  481. dev_alert(ap->dev, "%s: FIFO error detected: 0x%02x!\n",
  482. __func__, in_8(&priv->ata_regs->fifo_status));
  483. }
  484. static u8
  485. mpc52xx_bmdma_status(struct ata_port *ap)
  486. {
  487. struct mpc52xx_ata_priv *priv = ap->host->private_data;
  488. /* Check FIFO is OK... */
  489. if (in_8(&priv->ata_regs->fifo_status) & MPC52xx_ATA_FIFOSTAT_ERROR) {
  490. dev_alert(ap->dev, "%s: FIFO error detected: 0x%02x!\n",
  491. __func__, in_8(&priv->ata_regs->fifo_status));
  492. return priv->waiting_for_dma | ATA_DMA_ERR;
  493. }
  494. return priv->waiting_for_dma;
  495. }
  496. static irqreturn_t
  497. mpc52xx_ata_task_irq(int irq, void *vpriv)
  498. {
  499. struct mpc52xx_ata_priv *priv = vpriv;
  500. while (bcom_buffer_done(priv->dmatsk))
  501. bcom_retrieve_buffer(priv->dmatsk, NULL, NULL);
  502. priv->waiting_for_dma |= ATA_DMA_INTR;
  503. return IRQ_HANDLED;
  504. }
  505. static struct scsi_host_template mpc52xx_ata_sht = {
  506. ATA_PIO_SHT(DRV_NAME),
  507. };
  508. static struct ata_port_operations mpc52xx_ata_port_ops = {
  509. .inherits = &ata_bmdma_port_ops,
  510. .sff_dev_select = mpc52xx_ata_dev_select,
  511. .set_piomode = mpc52xx_ata_set_piomode,
  512. .set_dmamode = mpc52xx_ata_set_dmamode,
  513. .bmdma_setup = mpc52xx_bmdma_setup,
  514. .bmdma_start = mpc52xx_bmdma_start,
  515. .bmdma_stop = mpc52xx_bmdma_stop,
  516. .bmdma_status = mpc52xx_bmdma_status,
  517. .qc_prep = ata_noop_qc_prep,
  518. };
  519. static int mpc52xx_ata_init_one(struct device *dev,
  520. struct mpc52xx_ata_priv *priv,
  521. unsigned long raw_ata_regs,
  522. int mwdma_mask, int udma_mask)
  523. {
  524. struct ata_host *host;
  525. struct ata_port *ap;
  526. struct ata_ioports *aio;
  527. host = ata_host_alloc(dev, 1);
  528. if (!host)
  529. return -ENOMEM;
  530. ap = host->ports[0];
  531. ap->flags |= ATA_FLAG_SLAVE_POSS;
  532. ap->pio_mask = ATA_PIO4;
  533. ap->mwdma_mask = mwdma_mask;
  534. ap->udma_mask = udma_mask;
  535. ap->ops = &mpc52xx_ata_port_ops;
  536. host->private_data = priv;
  537. aio = &ap->ioaddr;
  538. aio->cmd_addr = NULL; /* Don't have a classic reg block */
  539. aio->altstatus_addr = &priv->ata_regs->tf_control;
  540. aio->ctl_addr = &priv->ata_regs->tf_control;
  541. aio->data_addr = &priv->ata_regs->tf_data;
  542. aio->error_addr = &priv->ata_regs->tf_features;
  543. aio->feature_addr = &priv->ata_regs->tf_features;
  544. aio->nsect_addr = &priv->ata_regs->tf_sec_count;
  545. aio->lbal_addr = &priv->ata_regs->tf_sec_num;
  546. aio->lbam_addr = &priv->ata_regs->tf_cyl_low;
  547. aio->lbah_addr = &priv->ata_regs->tf_cyl_high;
  548. aio->device_addr = &priv->ata_regs->tf_dev_head;
  549. aio->status_addr = &priv->ata_regs->tf_command;
  550. aio->command_addr = &priv->ata_regs->tf_command;
  551. ata_port_desc(ap, "ata_regs 0x%lx", raw_ata_regs);
  552. /* activate host */
  553. return ata_host_activate(host, priv->ata_irq, ata_bmdma_interrupt, 0,
  554. &mpc52xx_ata_sht);
  555. }
  556. /* ======================================================================== */
  557. /* OF Platform driver */
  558. /* ======================================================================== */
  559. static int mpc52xx_ata_probe(struct platform_device *op)
  560. {
  561. unsigned int ipb_freq;
  562. struct resource res_mem;
  563. int ata_irq = 0;
  564. struct mpc52xx_ata __iomem *ata_regs;
  565. struct mpc52xx_ata_priv *priv = NULL;
  566. int rv, task_irq;
  567. int mwdma_mask = 0, udma_mask = 0;
  568. const __be32 *prop;
  569. int proplen;
  570. struct bcom_task *dmatsk;
  571. /* Get ipb frequency */
  572. ipb_freq = mpc5xxx_get_bus_frequency(op->dev.of_node);
  573. if (!ipb_freq) {
  574. dev_err(&op->dev, "could not determine IPB bus frequency\n");
  575. return -ENODEV;
  576. }
  577. /* Get device base address from device tree, request the region
  578. * and ioremap it. */
  579. rv = of_address_to_resource(op->dev.of_node, 0, &res_mem);
  580. if (rv) {
  581. dev_err(&op->dev, "could not determine device base address\n");
  582. return rv;
  583. }
  584. if (!devm_request_mem_region(&op->dev, res_mem.start,
  585. sizeof(*ata_regs), DRV_NAME)) {
  586. dev_err(&op->dev, "error requesting register region\n");
  587. return -EBUSY;
  588. }
  589. ata_regs = devm_ioremap(&op->dev, res_mem.start, sizeof(*ata_regs));
  590. if (!ata_regs) {
  591. dev_err(&op->dev, "error mapping device registers\n");
  592. return -ENOMEM;
  593. }
  594. /*
  595. * By default, all DMA modes are disabled for the MPC5200. Some
  596. * boards don't have the required signals routed to make DMA work.
  597. * Also, the MPC5200B has a silicon bug that causes data corruption
  598. * with UDMA if it is used at the same time as the LocalPlus bus.
  599. *
  600. * Instead of trying to guess what modes are usable, check the
  601. * ATA device tree node to find out what DMA modes work on the board.
  602. * UDMA/MWDMA modes can also be forced by adding "libata.force=<mode>"
  603. * to the kernel boot parameters.
  604. *
  605. * The MPC5200 ATA controller supports MWDMA modes 0, 1 and 2 and
  606. * UDMA modes 0, 1 and 2.
  607. */
  608. prop = of_get_property(op->dev.of_node, "mwdma-mode", &proplen);
  609. if ((prop) && (proplen >= 4))
  610. mwdma_mask = ATA_MWDMA2 & ((1 << (*prop + 1)) - 1);
  611. prop = of_get_property(op->dev.of_node, "udma-mode", &proplen);
  612. if ((prop) && (proplen >= 4))
  613. udma_mask = ATA_UDMA2 & ((1 << (*prop + 1)) - 1);
  614. ata_irq = irq_of_parse_and_map(op->dev.of_node, 0);
  615. if (ata_irq == NO_IRQ) {
  616. dev_err(&op->dev, "error mapping irq\n");
  617. return -EINVAL;
  618. }
  619. /* Prepare our private structure */
  620. priv = devm_kzalloc(&op->dev, sizeof(*priv), GFP_ATOMIC);
  621. if (!priv) {
  622. rv = -ENOMEM;
  623. goto err1;
  624. }
  625. priv->ipb_period = 1000000000 / (ipb_freq / 1000);
  626. priv->ata_regs = ata_regs;
  627. priv->ata_regs_pa = res_mem.start;
  628. priv->ata_irq = ata_irq;
  629. priv->csel = -1;
  630. priv->mpc52xx_ata_dma_last_write = -1;
  631. if (ipb_freq/1000000 == 66) {
  632. priv->mdmaspec = mdmaspec66;
  633. priv->udmaspec = udmaspec66;
  634. } else {
  635. priv->mdmaspec = mdmaspec132;
  636. priv->udmaspec = udmaspec132;
  637. }
  638. /* Allocate a BestComm task for DMA */
  639. dmatsk = bcom_ata_init(MAX_DMA_BUFFERS, MAX_DMA_BUFFER_SIZE);
  640. if (!dmatsk) {
  641. dev_err(&op->dev, "bestcomm initialization failed\n");
  642. rv = -ENOMEM;
  643. goto err1;
  644. }
  645. task_irq = bcom_get_task_irq(dmatsk);
  646. rv = devm_request_irq(&op->dev, task_irq, &mpc52xx_ata_task_irq, 0,
  647. "ATA task", priv);
  648. if (rv) {
  649. dev_err(&op->dev, "error requesting DMA IRQ\n");
  650. goto err2;
  651. }
  652. priv->dmatsk = dmatsk;
  653. /* Init the hw */
  654. rv = mpc52xx_ata_hw_init(priv);
  655. if (rv) {
  656. dev_err(&op->dev, "error initializing hardware\n");
  657. goto err2;
  658. }
  659. /* Register ourselves to libata */
  660. rv = mpc52xx_ata_init_one(&op->dev, priv, res_mem.start,
  661. mwdma_mask, udma_mask);
  662. if (rv) {
  663. dev_err(&op->dev, "error registering with ATA layer\n");
  664. goto err2;
  665. }
  666. return 0;
  667. err2:
  668. irq_dispose_mapping(task_irq);
  669. bcom_ata_release(dmatsk);
  670. err1:
  671. irq_dispose_mapping(ata_irq);
  672. return rv;
  673. }
  674. static int
  675. mpc52xx_ata_remove(struct platform_device *op)
  676. {
  677. struct ata_host *host = platform_get_drvdata(op);
  678. struct mpc52xx_ata_priv *priv = host->private_data;
  679. int task_irq;
  680. /* Deregister the ATA interface */
  681. ata_platform_remove_one(op);
  682. /* Clean up DMA */
  683. task_irq = bcom_get_task_irq(priv->dmatsk);
  684. irq_dispose_mapping(task_irq);
  685. bcom_ata_release(priv->dmatsk);
  686. irq_dispose_mapping(priv->ata_irq);
  687. return 0;
  688. }
  689. #ifdef CONFIG_PM_SLEEP
  690. static int
  691. mpc52xx_ata_suspend(struct platform_device *op, pm_message_t state)
  692. {
  693. struct ata_host *host = platform_get_drvdata(op);
  694. return ata_host_suspend(host, state);
  695. }
  696. static int
  697. mpc52xx_ata_resume(struct platform_device *op)
  698. {
  699. struct ata_host *host = platform_get_drvdata(op);
  700. struct mpc52xx_ata_priv *priv = host->private_data;
  701. int rv;
  702. rv = mpc52xx_ata_hw_init(priv);
  703. if (rv) {
  704. dev_err(host->dev, "error initializing hardware\n");
  705. return rv;
  706. }
  707. ata_host_resume(host);
  708. return 0;
  709. }
  710. #endif
  711. static const struct of_device_id mpc52xx_ata_of_match[] = {
  712. { .compatible = "fsl,mpc5200-ata", },
  713. { .compatible = "mpc5200-ata", },
  714. {},
  715. };
  716. static struct platform_driver mpc52xx_ata_of_platform_driver = {
  717. .probe = mpc52xx_ata_probe,
  718. .remove = mpc52xx_ata_remove,
  719. #ifdef CONFIG_PM_SLEEP
  720. .suspend = mpc52xx_ata_suspend,
  721. .resume = mpc52xx_ata_resume,
  722. #endif
  723. .driver = {
  724. .name = DRV_NAME,
  725. .of_match_table = mpc52xx_ata_of_match,
  726. },
  727. };
  728. module_platform_driver(mpc52xx_ata_of_platform_driver);
  729. MODULE_AUTHOR("Sylvain Munaut <tnt@246tNt.com>");
  730. MODULE_DESCRIPTION("Freescale MPC52xx IDE/ATA libata driver");
  731. MODULE_LICENSE("GPL");
  732. MODULE_DEVICE_TABLE(of, mpc52xx_ata_of_match);