pata_icside.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. #include <linux/kernel.h>
  3. #include <linux/module.h>
  4. #include <linux/init.h>
  5. #include <linux/blkdev.h>
  6. #include <linux/gfp.h>
  7. #include <scsi/scsi_host.h>
  8. #include <linux/ata.h>
  9. #include <linux/libata.h>
  10. #include <asm/dma.h>
  11. #include <asm/ecard.h>
  12. #define DRV_NAME "pata_icside"
  13. #define ICS_IDENT_OFFSET 0x2280
  14. #define ICS_ARCIN_V5_INTRSTAT 0x0000
  15. #define ICS_ARCIN_V5_INTROFFSET 0x0004
  16. #define ICS_ARCIN_V6_INTROFFSET_1 0x2200
  17. #define ICS_ARCIN_V6_INTRSTAT_1 0x2290
  18. #define ICS_ARCIN_V6_INTROFFSET_2 0x3200
  19. #define ICS_ARCIN_V6_INTRSTAT_2 0x3290
  20. struct portinfo {
  21. unsigned int dataoffset;
  22. unsigned int ctrloffset;
  23. unsigned int stepping;
  24. };
  25. static const struct portinfo pata_icside_portinfo_v5 = {
  26. .dataoffset = 0x2800,
  27. .ctrloffset = 0x2b80,
  28. .stepping = 6,
  29. };
  30. static const struct portinfo pata_icside_portinfo_v6_1 = {
  31. .dataoffset = 0x2000,
  32. .ctrloffset = 0x2380,
  33. .stepping = 6,
  34. };
  35. static const struct portinfo pata_icside_portinfo_v6_2 = {
  36. .dataoffset = 0x3000,
  37. .ctrloffset = 0x3380,
  38. .stepping = 6,
  39. };
  40. struct pata_icside_state {
  41. void __iomem *irq_port;
  42. void __iomem *ioc_base;
  43. unsigned int type;
  44. unsigned int dma;
  45. struct {
  46. u8 port_sel;
  47. u8 disabled;
  48. unsigned int speed[ATA_MAX_DEVICES];
  49. } port[2];
  50. };
  51. struct pata_icside_info {
  52. struct pata_icside_state *state;
  53. struct expansion_card *ec;
  54. void __iomem *base;
  55. void __iomem *irqaddr;
  56. unsigned int irqmask;
  57. const expansioncard_ops_t *irqops;
  58. unsigned int mwdma_mask;
  59. unsigned int nr_ports;
  60. const struct portinfo *port[2];
  61. unsigned long raw_base;
  62. unsigned long raw_ioc_base;
  63. };
  64. #define ICS_TYPE_A3IN 0
  65. #define ICS_TYPE_A3USER 1
  66. #define ICS_TYPE_V6 3
  67. #define ICS_TYPE_V5 15
  68. #define ICS_TYPE_NOTYPE ((unsigned int)-1)
  69. /* ---------------- Version 5 PCB Support Functions --------------------- */
  70. /* Prototype: pata_icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
  71. * Purpose : enable interrupts from card
  72. */
  73. static void pata_icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
  74. {
  75. struct pata_icside_state *state = ec->irq_data;
  76. writeb(0, state->irq_port + ICS_ARCIN_V5_INTROFFSET);
  77. }
  78. /* Prototype: pata_icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
  79. * Purpose : disable interrupts from card
  80. */
  81. static void pata_icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
  82. {
  83. struct pata_icside_state *state = ec->irq_data;
  84. readb(state->irq_port + ICS_ARCIN_V5_INTROFFSET);
  85. }
  86. static const expansioncard_ops_t pata_icside_ops_arcin_v5 = {
  87. .irqenable = pata_icside_irqenable_arcin_v5,
  88. .irqdisable = pata_icside_irqdisable_arcin_v5,
  89. };
  90. /* ---------------- Version 6 PCB Support Functions --------------------- */
  91. /* Prototype: pata_icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
  92. * Purpose : enable interrupts from card
  93. */
  94. static void pata_icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
  95. {
  96. struct pata_icside_state *state = ec->irq_data;
  97. void __iomem *base = state->irq_port;
  98. if (!state->port[0].disabled)
  99. writeb(0, base + ICS_ARCIN_V6_INTROFFSET_1);
  100. if (!state->port[1].disabled)
  101. writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2);
  102. }
  103. /* Prototype: pata_icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
  104. * Purpose : disable interrupts from card
  105. */
  106. static void pata_icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
  107. {
  108. struct pata_icside_state *state = ec->irq_data;
  109. readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
  110. readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
  111. }
  112. /* Prototype: pata_icside_irqprobe(struct expansion_card *ec)
  113. * Purpose : detect an active interrupt from card
  114. */
  115. static int pata_icside_irqpending_arcin_v6(struct expansion_card *ec)
  116. {
  117. struct pata_icside_state *state = ec->irq_data;
  118. return readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_1) & 1 ||
  119. readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_2) & 1;
  120. }
  121. static const expansioncard_ops_t pata_icside_ops_arcin_v6 = {
  122. .irqenable = pata_icside_irqenable_arcin_v6,
  123. .irqdisable = pata_icside_irqdisable_arcin_v6,
  124. .irqpending = pata_icside_irqpending_arcin_v6,
  125. };
  126. /*
  127. * SG-DMA support.
  128. *
  129. * Similar to the BM-DMA, but we use the RiscPCs IOMD DMA controllers.
  130. * There is only one DMA controller per card, which means that only
  131. * one drive can be accessed at one time. NOTE! We do not enforce that
  132. * here, but we rely on the main IDE driver spotting that both
  133. * interfaces use the same IRQ, which should guarantee this.
  134. */
  135. /*
  136. * Configure the IOMD to give the appropriate timings for the transfer
  137. * mode being requested. We take the advice of the ATA standards, and
  138. * calculate the cycle time based on the transfer mode, and the EIDE
  139. * MW DMA specs that the drive provides in the IDENTIFY command.
  140. *
  141. * We have the following IOMD DMA modes to choose from:
  142. *
  143. * Type Active Recovery Cycle
  144. * A 250 (250) 312 (550) 562 (800)
  145. * B 187 (200) 250 (550) 437 (750)
  146. * C 125 (125) 125 (375) 250 (500)
  147. * D 62 (50) 125 (375) 187 (425)
  148. *
  149. * (figures in brackets are actual measured timings on DIOR/DIOW)
  150. *
  151. * However, we also need to take care of the read/write active and
  152. * recovery timings:
  153. *
  154. * Read Write
  155. * Mode Active -- Recovery -- Cycle IOMD type
  156. * MW0 215 50 215 480 A
  157. * MW1 80 50 50 150 C
  158. * MW2 70 25 25 120 C
  159. */
  160. static void pata_icside_set_dmamode(struct ata_port *ap, struct ata_device *adev)
  161. {
  162. struct pata_icside_state *state = ap->host->private_data;
  163. struct ata_timing t;
  164. unsigned int cycle;
  165. char iomd_type;
  166. /*
  167. * DMA is based on a 16MHz clock
  168. */
  169. if (ata_timing_compute(adev, adev->dma_mode, &t, 1000, 1))
  170. return;
  171. /*
  172. * Choose the IOMD cycle timing which ensure that the interface
  173. * satisfies the measured active, recovery and cycle times.
  174. */
  175. if (t.active <= 50 && t.recover <= 375 && t.cycle <= 425)
  176. iomd_type = 'D', cycle = 187;
  177. else if (t.active <= 125 && t.recover <= 375 && t.cycle <= 500)
  178. iomd_type = 'C', cycle = 250;
  179. else if (t.active <= 200 && t.recover <= 550 && t.cycle <= 750)
  180. iomd_type = 'B', cycle = 437;
  181. else
  182. iomd_type = 'A', cycle = 562;
  183. ata_dev_info(adev, "timings: act %dns rec %dns cyc %dns (%c)\n",
  184. t.active, t.recover, t.cycle, iomd_type);
  185. state->port[ap->port_no].speed[adev->devno] = cycle;
  186. }
  187. static void pata_icside_bmdma_setup(struct ata_queued_cmd *qc)
  188. {
  189. struct ata_port *ap = qc->ap;
  190. struct pata_icside_state *state = ap->host->private_data;
  191. unsigned int write = qc->tf.flags & ATA_TFLAG_WRITE;
  192. /*
  193. * We are simplex; BUG if we try to fiddle with DMA
  194. * while it's active.
  195. */
  196. BUG_ON(dma_channel_active(state->dma));
  197. /*
  198. * Route the DMA signals to the correct interface
  199. */
  200. writeb(state->port[ap->port_no].port_sel, state->ioc_base);
  201. set_dma_speed(state->dma, state->port[ap->port_no].speed[qc->dev->devno]);
  202. set_dma_sg(state->dma, qc->sg, qc->n_elem);
  203. set_dma_mode(state->dma, write ? DMA_MODE_WRITE : DMA_MODE_READ);
  204. /* issue r/w command */
  205. ap->ops->sff_exec_command(ap, &qc->tf);
  206. }
  207. static void pata_icside_bmdma_start(struct ata_queued_cmd *qc)
  208. {
  209. struct ata_port *ap = qc->ap;
  210. struct pata_icside_state *state = ap->host->private_data;
  211. BUG_ON(dma_channel_active(state->dma));
  212. enable_dma(state->dma);
  213. }
  214. static void pata_icside_bmdma_stop(struct ata_queued_cmd *qc)
  215. {
  216. struct ata_port *ap = qc->ap;
  217. struct pata_icside_state *state = ap->host->private_data;
  218. disable_dma(state->dma);
  219. /* see ata_bmdma_stop */
  220. ata_sff_dma_pause(ap);
  221. }
  222. static u8 pata_icside_bmdma_status(struct ata_port *ap)
  223. {
  224. struct pata_icside_state *state = ap->host->private_data;
  225. void __iomem *irq_port;
  226. irq_port = state->irq_port + (ap->port_no ? ICS_ARCIN_V6_INTRSTAT_2 :
  227. ICS_ARCIN_V6_INTRSTAT_1);
  228. return readb(irq_port) & 1 ? ATA_DMA_INTR : 0;
  229. }
  230. static int icside_dma_init(struct pata_icside_info *info)
  231. {
  232. struct pata_icside_state *state = info->state;
  233. struct expansion_card *ec = info->ec;
  234. int i;
  235. for (i = 0; i < ATA_MAX_DEVICES; i++) {
  236. state->port[0].speed[i] = 480;
  237. state->port[1].speed[i] = 480;
  238. }
  239. if (ec->dma != NO_DMA && !request_dma(ec->dma, DRV_NAME)) {
  240. state->dma = ec->dma;
  241. info->mwdma_mask = ATA_MWDMA2;
  242. }
  243. return 0;
  244. }
  245. static struct scsi_host_template pata_icside_sht = {
  246. ATA_BASE_SHT(DRV_NAME),
  247. .sg_tablesize = SG_MAX_SEGMENTS,
  248. .dma_boundary = IOMD_DMA_BOUNDARY,
  249. };
  250. static void pata_icside_postreset(struct ata_link *link, unsigned int *classes)
  251. {
  252. struct ata_port *ap = link->ap;
  253. struct pata_icside_state *state = ap->host->private_data;
  254. if (classes[0] != ATA_DEV_NONE || classes[1] != ATA_DEV_NONE)
  255. return ata_sff_postreset(link, classes);
  256. state->port[ap->port_no].disabled = 1;
  257. if (state->type == ICS_TYPE_V6) {
  258. /*
  259. * Disable interrupts from this port, otherwise we
  260. * receive spurious interrupts from the floating
  261. * interrupt line.
  262. */
  263. void __iomem *irq_port = state->irq_port +
  264. (ap->port_no ? ICS_ARCIN_V6_INTROFFSET_2 : ICS_ARCIN_V6_INTROFFSET_1);
  265. readb(irq_port);
  266. }
  267. }
  268. static struct ata_port_operations pata_icside_port_ops = {
  269. .inherits = &ata_bmdma_port_ops,
  270. /* no need to build any PRD tables for DMA */
  271. .qc_prep = ata_noop_qc_prep,
  272. .sff_data_xfer = ata_sff_data_xfer32,
  273. .bmdma_setup = pata_icside_bmdma_setup,
  274. .bmdma_start = pata_icside_bmdma_start,
  275. .bmdma_stop = pata_icside_bmdma_stop,
  276. .bmdma_status = pata_icside_bmdma_status,
  277. .cable_detect = ata_cable_40wire,
  278. .set_dmamode = pata_icside_set_dmamode,
  279. .postreset = pata_icside_postreset,
  280. .port_start = ATA_OP_NULL, /* don't need PRD table */
  281. };
  282. static void pata_icside_setup_ioaddr(struct ata_port *ap, void __iomem *base,
  283. struct pata_icside_info *info,
  284. const struct portinfo *port)
  285. {
  286. struct ata_ioports *ioaddr = &ap->ioaddr;
  287. void __iomem *cmd = base + port->dataoffset;
  288. ioaddr->cmd_addr = cmd;
  289. ioaddr->data_addr = cmd + (ATA_REG_DATA << port->stepping);
  290. ioaddr->error_addr = cmd + (ATA_REG_ERR << port->stepping);
  291. ioaddr->feature_addr = cmd + (ATA_REG_FEATURE << port->stepping);
  292. ioaddr->nsect_addr = cmd + (ATA_REG_NSECT << port->stepping);
  293. ioaddr->lbal_addr = cmd + (ATA_REG_LBAL << port->stepping);
  294. ioaddr->lbam_addr = cmd + (ATA_REG_LBAM << port->stepping);
  295. ioaddr->lbah_addr = cmd + (ATA_REG_LBAH << port->stepping);
  296. ioaddr->device_addr = cmd + (ATA_REG_DEVICE << port->stepping);
  297. ioaddr->status_addr = cmd + (ATA_REG_STATUS << port->stepping);
  298. ioaddr->command_addr = cmd + (ATA_REG_CMD << port->stepping);
  299. ioaddr->ctl_addr = base + port->ctrloffset;
  300. ioaddr->altstatus_addr = ioaddr->ctl_addr;
  301. ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx",
  302. info->raw_base + port->dataoffset,
  303. info->raw_base + port->ctrloffset);
  304. if (info->raw_ioc_base)
  305. ata_port_desc(ap, "iocbase 0x%lx", info->raw_ioc_base);
  306. }
  307. static int pata_icside_register_v5(struct pata_icside_info *info)
  308. {
  309. struct pata_icside_state *state = info->state;
  310. void __iomem *base;
  311. base = ecardm_iomap(info->ec, ECARD_RES_MEMC, 0, 0);
  312. if (!base)
  313. return -ENOMEM;
  314. state->irq_port = base;
  315. info->base = base;
  316. info->irqaddr = base + ICS_ARCIN_V5_INTRSTAT;
  317. info->irqmask = 1;
  318. info->irqops = &pata_icside_ops_arcin_v5;
  319. info->nr_ports = 1;
  320. info->port[0] = &pata_icside_portinfo_v5;
  321. info->raw_base = ecard_resource_start(info->ec, ECARD_RES_MEMC);
  322. return 0;
  323. }
  324. static int pata_icside_register_v6(struct pata_icside_info *info)
  325. {
  326. struct pata_icside_state *state = info->state;
  327. struct expansion_card *ec = info->ec;
  328. void __iomem *ioc_base, *easi_base;
  329. unsigned int sel = 0;
  330. ioc_base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
  331. if (!ioc_base)
  332. return -ENOMEM;
  333. easi_base = ioc_base;
  334. if (ecard_resource_flags(ec, ECARD_RES_EASI)) {
  335. easi_base = ecardm_iomap(ec, ECARD_RES_EASI, 0, 0);
  336. if (!easi_base)
  337. return -ENOMEM;
  338. /*
  339. * Enable access to the EASI region.
  340. */
  341. sel = 1 << 5;
  342. }
  343. writeb(sel, ioc_base);
  344. state->irq_port = easi_base;
  345. state->ioc_base = ioc_base;
  346. state->port[0].port_sel = sel;
  347. state->port[1].port_sel = sel | 1;
  348. info->base = easi_base;
  349. info->irqops = &pata_icside_ops_arcin_v6;
  350. info->nr_ports = 2;
  351. info->port[0] = &pata_icside_portinfo_v6_1;
  352. info->port[1] = &pata_icside_portinfo_v6_2;
  353. info->raw_base = ecard_resource_start(ec, ECARD_RES_EASI);
  354. info->raw_ioc_base = ecard_resource_start(ec, ECARD_RES_IOCFAST);
  355. return icside_dma_init(info);
  356. }
  357. static int pata_icside_add_ports(struct pata_icside_info *info)
  358. {
  359. struct expansion_card *ec = info->ec;
  360. struct ata_host *host;
  361. int i;
  362. if (info->irqaddr) {
  363. ec->irqaddr = info->irqaddr;
  364. ec->irqmask = info->irqmask;
  365. }
  366. if (info->irqops)
  367. ecard_setirq(ec, info->irqops, info->state);
  368. /*
  369. * Be on the safe side - disable interrupts
  370. */
  371. ec->ops->irqdisable(ec, ec->irq);
  372. host = ata_host_alloc(&ec->dev, info->nr_ports);
  373. if (!host)
  374. return -ENOMEM;
  375. host->private_data = info->state;
  376. host->flags = ATA_HOST_SIMPLEX;
  377. for (i = 0; i < info->nr_ports; i++) {
  378. struct ata_port *ap = host->ports[i];
  379. ap->pio_mask = ATA_PIO4;
  380. ap->mwdma_mask = info->mwdma_mask;
  381. ap->flags |= ATA_FLAG_SLAVE_POSS;
  382. ap->ops = &pata_icside_port_ops;
  383. pata_icside_setup_ioaddr(ap, info->base, info, info->port[i]);
  384. }
  385. return ata_host_activate(host, ec->irq, ata_bmdma_interrupt, 0,
  386. &pata_icside_sht);
  387. }
  388. static int pata_icside_probe(struct expansion_card *ec,
  389. const struct ecard_id *id)
  390. {
  391. struct pata_icside_state *state;
  392. struct pata_icside_info info;
  393. void __iomem *idmem;
  394. int ret;
  395. ret = ecard_request_resources(ec);
  396. if (ret)
  397. goto out;
  398. state = devm_kzalloc(&ec->dev, sizeof(*state), GFP_KERNEL);
  399. if (!state) {
  400. ret = -ENOMEM;
  401. goto release;
  402. }
  403. state->type = ICS_TYPE_NOTYPE;
  404. state->dma = NO_DMA;
  405. idmem = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
  406. if (idmem) {
  407. unsigned int type;
  408. type = readb(idmem + ICS_IDENT_OFFSET) & 1;
  409. type |= (readb(idmem + ICS_IDENT_OFFSET + 4) & 1) << 1;
  410. type |= (readb(idmem + ICS_IDENT_OFFSET + 8) & 1) << 2;
  411. type |= (readb(idmem + ICS_IDENT_OFFSET + 12) & 1) << 3;
  412. ecardm_iounmap(ec, idmem);
  413. state->type = type;
  414. }
  415. memset(&info, 0, sizeof(info));
  416. info.state = state;
  417. info.ec = ec;
  418. switch (state->type) {
  419. case ICS_TYPE_A3IN:
  420. dev_warn(&ec->dev, "A3IN unsupported\n");
  421. ret = -ENODEV;
  422. break;
  423. case ICS_TYPE_A3USER:
  424. dev_warn(&ec->dev, "A3USER unsupported\n");
  425. ret = -ENODEV;
  426. break;
  427. case ICS_TYPE_V5:
  428. ret = pata_icside_register_v5(&info);
  429. break;
  430. case ICS_TYPE_V6:
  431. ret = pata_icside_register_v6(&info);
  432. break;
  433. default:
  434. dev_warn(&ec->dev, "unknown interface type\n");
  435. ret = -ENODEV;
  436. break;
  437. }
  438. if (ret == 0)
  439. ret = pata_icside_add_ports(&info);
  440. if (ret == 0)
  441. goto out;
  442. release:
  443. ecard_release_resources(ec);
  444. out:
  445. return ret;
  446. }
  447. static void pata_icside_shutdown(struct expansion_card *ec)
  448. {
  449. struct ata_host *host = ecard_get_drvdata(ec);
  450. unsigned long flags;
  451. /*
  452. * Disable interrupts from this card. We need to do
  453. * this before disabling EASI since we may be accessing
  454. * this register via that region.
  455. */
  456. local_irq_save(flags);
  457. ec->ops->irqdisable(ec, ec->irq);
  458. local_irq_restore(flags);
  459. /*
  460. * Reset the ROM pointer so that we can read the ROM
  461. * after a soft reboot. This also disables access to
  462. * the IDE taskfile via the EASI region.
  463. */
  464. if (host) {
  465. struct pata_icside_state *state = host->private_data;
  466. if (state->ioc_base)
  467. writeb(0, state->ioc_base);
  468. }
  469. }
  470. static void pata_icside_remove(struct expansion_card *ec)
  471. {
  472. struct ata_host *host = ecard_get_drvdata(ec);
  473. struct pata_icside_state *state = host->private_data;
  474. ata_host_detach(host);
  475. pata_icside_shutdown(ec);
  476. /*
  477. * don't NULL out the drvdata - devres/libata wants it
  478. * to free the ata_host structure.
  479. */
  480. if (state->dma != NO_DMA)
  481. free_dma(state->dma);
  482. ecard_release_resources(ec);
  483. }
  484. static const struct ecard_id pata_icside_ids[] = {
  485. { MANU_ICS, PROD_ICS_IDE },
  486. { MANU_ICS2, PROD_ICS2_IDE },
  487. { 0xffff, 0xffff }
  488. };
  489. static struct ecard_driver pata_icside_driver = {
  490. .probe = pata_icside_probe,
  491. .remove = pata_icside_remove,
  492. .shutdown = pata_icside_shutdown,
  493. .id_table = pata_icside_ids,
  494. .drv = {
  495. .name = DRV_NAME,
  496. },
  497. };
  498. static int __init pata_icside_init(void)
  499. {
  500. return ecard_register_driver(&pata_icside_driver);
  501. }
  502. static void __exit pata_icside_exit(void)
  503. {
  504. ecard_remove_driver(&pata_icside_driver);
  505. }
  506. MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
  507. MODULE_LICENSE("GPL");
  508. MODULE_DESCRIPTION("ICS PATA driver");
  509. module_init(pata_icside_init);
  510. module_exit(pata_icside_exit);