pata_hpt3x2n.c 16 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Libata driver for the HighPoint 371N, 372N, and 302N UDMA66 ATA controllers.
  4. *
  5. * This driver is heavily based upon:
  6. *
  7. * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
  8. *
  9. * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
  10. * Portions Copyright (C) 2001 Sun Microsystems, Inc.
  11. * Portions Copyright (C) 2003 Red Hat Inc
  12. * Portions Copyright (C) 2005-2010 MontaVista Software, Inc.
  13. *
  14. *
  15. * TODO
  16. * Work out best PLL policy
  17. */
  18. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  19. #include <linux/kernel.h>
  20. #include <linux/module.h>
  21. #include <linux/pci.h>
  22. #include <linux/blkdev.h>
  23. #include <linux/delay.h>
  24. #include <scsi/scsi_host.h>
  25. #include <linux/libata.h>
  26. #define DRV_NAME "pata_hpt3x2n"
  27. #define DRV_VERSION "0.3.15"
  28. enum {
  29. HPT_PCI_FAST = (1 << 31),
  30. PCI66 = (1 << 1),
  31. USE_DPLL = (1 << 0)
  32. };
  33. struct hpt_clock {
  34. u8 xfer_speed;
  35. u32 timing;
  36. };
  37. struct hpt_chip {
  38. const char *name;
  39. struct hpt_clock *clocks[3];
  40. };
  41. /* key for bus clock timings
  42. * bit
  43. * 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
  44. * cycles = value + 1
  45. * 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
  46. * cycles = value + 1
  47. * 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
  48. * register access.
  49. * 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file
  50. * register access.
  51. * 18:20 udma_cycle_time. Clock cycles for UDMA xfer.
  52. * 21 CLK frequency for UDMA: 0=ATA clock, 1=dual ATA clock.
  53. * 22:24 pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer.
  54. * 25:27 cmd_pre_high_time. Time to initialize 1st PIO cycle for task file
  55. * register access.
  56. * 28 UDMA enable.
  57. * 29 DMA enable.
  58. * 30 PIO_MST enable. If set, the chip is in bus master mode during
  59. * PIO xfer.
  60. * 31 FIFO enable. Only for PIO.
  61. */
  62. /* 66MHz DPLL clocks */
  63. static struct hpt_clock hpt3x2n_clocks[] = {
  64. { XFER_UDMA_7, 0x1c869c62 },
  65. { XFER_UDMA_6, 0x1c869c62 },
  66. { XFER_UDMA_5, 0x1c8a9c62 },
  67. { XFER_UDMA_4, 0x1c8a9c62 },
  68. { XFER_UDMA_3, 0x1c8e9c62 },
  69. { XFER_UDMA_2, 0x1c929c62 },
  70. { XFER_UDMA_1, 0x1c9a9c62 },
  71. { XFER_UDMA_0, 0x1c829c62 },
  72. { XFER_MW_DMA_2, 0x2c829c62 },
  73. { XFER_MW_DMA_1, 0x2c829c66 },
  74. { XFER_MW_DMA_0, 0x2c829d2e },
  75. { XFER_PIO_4, 0x0c829c62 },
  76. { XFER_PIO_3, 0x0c829c84 },
  77. { XFER_PIO_2, 0x0c829ca6 },
  78. { XFER_PIO_1, 0x0d029d26 },
  79. { XFER_PIO_0, 0x0d029d5e },
  80. };
  81. /**
  82. * hpt3x2n_find_mode - reset the hpt3x2n bus
  83. * @ap: ATA port
  84. * @speed: transfer mode
  85. *
  86. * Return the 32bit register programming information for this channel
  87. * that matches the speed provided. For the moment the clocks table
  88. * is hard coded but easy to change. This will be needed if we use
  89. * different DPLLs
  90. */
  91. static u32 hpt3x2n_find_mode(struct ata_port *ap, int speed)
  92. {
  93. struct hpt_clock *clocks = hpt3x2n_clocks;
  94. while (clocks->xfer_speed) {
  95. if (clocks->xfer_speed == speed)
  96. return clocks->timing;
  97. clocks++;
  98. }
  99. BUG();
  100. return 0xffffffffU; /* silence compiler warning */
  101. }
  102. /**
  103. * hpt372n_filter - mode selection filter
  104. * @adev: ATA device
  105. * @mask: mode mask
  106. *
  107. * The Marvell bridge chips used on the HighPoint SATA cards do not seem
  108. * to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes...
  109. */
  110. static unsigned long hpt372n_filter(struct ata_device *adev, unsigned long mask)
  111. {
  112. if (ata_id_is_sata(adev->id))
  113. mask &= ~((0xE << ATA_SHIFT_UDMA) | ATA_MASK_MWDMA);
  114. return mask;
  115. }
  116. /**
  117. * hpt3x2n_cable_detect - Detect the cable type
  118. * @ap: ATA port to detect on
  119. *
  120. * Return the cable type attached to this port
  121. */
  122. static int hpt3x2n_cable_detect(struct ata_port *ap)
  123. {
  124. u8 scr2, ata66;
  125. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  126. pci_read_config_byte(pdev, 0x5B, &scr2);
  127. pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01);
  128. udelay(10); /* debounce */
  129. /* Cable register now active */
  130. pci_read_config_byte(pdev, 0x5A, &ata66);
  131. /* Restore state */
  132. pci_write_config_byte(pdev, 0x5B, scr2);
  133. if (ata66 & (2 >> ap->port_no))
  134. return ATA_CBL_PATA40;
  135. else
  136. return ATA_CBL_PATA80;
  137. }
  138. /**
  139. * hpt3x2n_pre_reset - reset the hpt3x2n bus
  140. * @link: ATA link to reset
  141. * @deadline: deadline jiffies for the operation
  142. *
  143. * Perform the initial reset handling for the 3x2n series controllers.
  144. * Reset the hardware and state machine,
  145. */
  146. static int hpt3x2n_pre_reset(struct ata_link *link, unsigned long deadline)
  147. {
  148. struct ata_port *ap = link->ap;
  149. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  150. /* Reset the state machine */
  151. pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
  152. udelay(100);
  153. return ata_sff_prereset(link, deadline);
  154. }
  155. static void hpt3x2n_set_mode(struct ata_port *ap, struct ata_device *adev,
  156. u8 mode)
  157. {
  158. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  159. u32 addr1, addr2;
  160. u32 reg, timing, mask;
  161. u8 fast;
  162. addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
  163. addr2 = 0x51 + 4 * ap->port_no;
  164. /* Fast interrupt prediction disable, hold off interrupt disable */
  165. pci_read_config_byte(pdev, addr2, &fast);
  166. fast &= ~0x07;
  167. pci_write_config_byte(pdev, addr2, fast);
  168. /* Determine timing mask and find matching mode entry */
  169. if (mode < XFER_MW_DMA_0)
  170. mask = 0xcfc3ffff;
  171. else if (mode < XFER_UDMA_0)
  172. mask = 0x31c001ff;
  173. else
  174. mask = 0x303c0000;
  175. timing = hpt3x2n_find_mode(ap, mode);
  176. pci_read_config_dword(pdev, addr1, &reg);
  177. reg = (reg & ~mask) | (timing & mask);
  178. pci_write_config_dword(pdev, addr1, reg);
  179. }
  180. /**
  181. * hpt3x2n_set_piomode - PIO setup
  182. * @ap: ATA interface
  183. * @adev: device on the interface
  184. *
  185. * Perform PIO mode setup.
  186. */
  187. static void hpt3x2n_set_piomode(struct ata_port *ap, struct ata_device *adev)
  188. {
  189. hpt3x2n_set_mode(ap, adev, adev->pio_mode);
  190. }
  191. /**
  192. * hpt3x2n_set_dmamode - DMA timing setup
  193. * @ap: ATA interface
  194. * @adev: Device being configured
  195. *
  196. * Set up the channel for MWDMA or UDMA modes.
  197. */
  198. static void hpt3x2n_set_dmamode(struct ata_port *ap, struct ata_device *adev)
  199. {
  200. hpt3x2n_set_mode(ap, adev, adev->dma_mode);
  201. }
  202. /**
  203. * hpt3x2n_bmdma_end - DMA engine stop
  204. * @qc: ATA command
  205. *
  206. * Clean up after the HPT3x2n and later DMA engine
  207. */
  208. static void hpt3x2n_bmdma_stop(struct ata_queued_cmd *qc)
  209. {
  210. struct ata_port *ap = qc->ap;
  211. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  212. int mscreg = 0x50 + 2 * ap->port_no;
  213. u8 bwsr_stat, msc_stat;
  214. pci_read_config_byte(pdev, 0x6A, &bwsr_stat);
  215. pci_read_config_byte(pdev, mscreg, &msc_stat);
  216. if (bwsr_stat & (1 << ap->port_no))
  217. pci_write_config_byte(pdev, mscreg, msc_stat | 0x30);
  218. ata_bmdma_stop(qc);
  219. }
  220. /**
  221. * hpt3x2n_set_clock - clock control
  222. * @ap: ATA port
  223. * @source: 0x21 or 0x23 for PLL or PCI sourced clock
  224. *
  225. * Switch the ATA bus clock between the PLL and PCI clock sources
  226. * while correctly isolating the bus and resetting internal logic
  227. *
  228. * We must use the DPLL for
  229. * - writing
  230. * - second channel UDMA7 (SATA ports) or higher
  231. * - 66MHz PCI
  232. *
  233. * or we will underclock the device and get reduced performance.
  234. */
  235. static void hpt3x2n_set_clock(struct ata_port *ap, int source)
  236. {
  237. void __iomem *bmdma = ap->ioaddr.bmdma_addr - ap->port_no * 8;
  238. /* Tristate the bus */
  239. iowrite8(0x80, bmdma+0x73);
  240. iowrite8(0x80, bmdma+0x77);
  241. /* Switch clock and reset channels */
  242. iowrite8(source, bmdma+0x7B);
  243. iowrite8(0xC0, bmdma+0x79);
  244. /* Reset state machines, avoid enabling the disabled channels */
  245. iowrite8(ioread8(bmdma+0x70) | 0x32, bmdma+0x70);
  246. iowrite8(ioread8(bmdma+0x74) | 0x32, bmdma+0x74);
  247. /* Complete reset */
  248. iowrite8(0x00, bmdma+0x79);
  249. /* Reconnect channels to bus */
  250. iowrite8(0x00, bmdma+0x73);
  251. iowrite8(0x00, bmdma+0x77);
  252. }
  253. static int hpt3x2n_use_dpll(struct ata_port *ap, int writing)
  254. {
  255. long flags = (long)ap->host->private_data;
  256. /* See if we should use the DPLL */
  257. if (writing)
  258. return USE_DPLL; /* Needed for write */
  259. if (flags & PCI66)
  260. return USE_DPLL; /* Needed at 66Mhz */
  261. return 0;
  262. }
  263. static int hpt3x2n_qc_defer(struct ata_queued_cmd *qc)
  264. {
  265. struct ata_port *ap = qc->ap;
  266. struct ata_port *alt = ap->host->ports[ap->port_no ^ 1];
  267. int rc, flags = (long)ap->host->private_data;
  268. int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE);
  269. /* First apply the usual rules */
  270. rc = ata_std_qc_defer(qc);
  271. if (rc != 0)
  272. return rc;
  273. if ((flags & USE_DPLL) != dpll && alt->qc_active)
  274. return ATA_DEFER_PORT;
  275. return 0;
  276. }
  277. static unsigned int hpt3x2n_qc_issue(struct ata_queued_cmd *qc)
  278. {
  279. struct ata_port *ap = qc->ap;
  280. int flags = (long)ap->host->private_data;
  281. int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE);
  282. if ((flags & USE_DPLL) != dpll) {
  283. flags &= ~USE_DPLL;
  284. flags |= dpll;
  285. ap->host->private_data = (void *)(long)flags;
  286. hpt3x2n_set_clock(ap, dpll ? 0x21 : 0x23);
  287. }
  288. return ata_bmdma_qc_issue(qc);
  289. }
  290. static struct scsi_host_template hpt3x2n_sht = {
  291. ATA_BMDMA_SHT(DRV_NAME),
  292. };
  293. /*
  294. * Configuration for HPT302N/371N.
  295. */
  296. static struct ata_port_operations hpt3xxn_port_ops = {
  297. .inherits = &ata_bmdma_port_ops,
  298. .bmdma_stop = hpt3x2n_bmdma_stop,
  299. .qc_defer = hpt3x2n_qc_defer,
  300. .qc_issue = hpt3x2n_qc_issue,
  301. .cable_detect = hpt3x2n_cable_detect,
  302. .set_piomode = hpt3x2n_set_piomode,
  303. .set_dmamode = hpt3x2n_set_dmamode,
  304. .prereset = hpt3x2n_pre_reset,
  305. };
  306. /*
  307. * Configuration for HPT372N. Same as 302N/371N but we have a mode filter.
  308. */
  309. static struct ata_port_operations hpt372n_port_ops = {
  310. .inherits = &hpt3xxn_port_ops,
  311. .mode_filter = &hpt372n_filter,
  312. };
  313. /**
  314. * hpt3xn_calibrate_dpll - Calibrate the DPLL loop
  315. * @dev: PCI device
  316. *
  317. * Perform a calibration cycle on the HPT3xN DPLL. Returns 1 if this
  318. * succeeds
  319. */
  320. static int hpt3xn_calibrate_dpll(struct pci_dev *dev)
  321. {
  322. u8 reg5b;
  323. u32 reg5c;
  324. int tries;
  325. for (tries = 0; tries < 0x5000; tries++) {
  326. udelay(50);
  327. pci_read_config_byte(dev, 0x5b, &reg5b);
  328. if (reg5b & 0x80) {
  329. /* See if it stays set */
  330. for (tries = 0; tries < 0x1000; tries++) {
  331. pci_read_config_byte(dev, 0x5b, &reg5b);
  332. /* Failed ? */
  333. if ((reg5b & 0x80) == 0)
  334. return 0;
  335. }
  336. /* Turn off tuning, we have the DPLL set */
  337. pci_read_config_dword(dev, 0x5c, &reg5c);
  338. pci_write_config_dword(dev, 0x5c, reg5c & ~0x100);
  339. return 1;
  340. }
  341. }
  342. /* Never went stable */
  343. return 0;
  344. }
  345. static int hpt3x2n_pci_clock(struct pci_dev *pdev)
  346. {
  347. unsigned long freq;
  348. u32 fcnt;
  349. unsigned long iobase = pci_resource_start(pdev, 4);
  350. fcnt = inl(iobase + 0x90); /* Not PCI readable for some chips */
  351. if ((fcnt >> 12) != 0xABCDE) {
  352. int i;
  353. u16 sr;
  354. u32 total = 0;
  355. pr_warn("BIOS clock data not set\n");
  356. /* This is the process the HPT371 BIOS is reported to use */
  357. for (i = 0; i < 128; i++) {
  358. pci_read_config_word(pdev, 0x78, &sr);
  359. total += sr & 0x1FF;
  360. udelay(15);
  361. }
  362. fcnt = total / 128;
  363. }
  364. fcnt &= 0x1FF;
  365. freq = (fcnt * 77) / 192;
  366. /* Clamp to bands */
  367. if (freq < 40)
  368. return 33;
  369. if (freq < 45)
  370. return 40;
  371. if (freq < 55)
  372. return 50;
  373. return 66;
  374. }
  375. /**
  376. * hpt3x2n_init_one - Initialise an HPT37X/302
  377. * @dev: PCI device
  378. * @id: Entry in match table
  379. *
  380. * Initialise an HPT3x2n device. There are some interesting complications
  381. * here. Firstly the chip may report 366 and be one of several variants.
  382. * Secondly all the timings depend on the clock for the chip which we must
  383. * detect and look up
  384. *
  385. * This is the known chip mappings. It may be missing a couple of later
  386. * releases.
  387. *
  388. * Chip version PCI Rev Notes
  389. * HPT372 4 (HPT366) 5 Other driver
  390. * HPT372N 4 (HPT366) 6 UDMA133
  391. * HPT372 5 (HPT372) 1 Other driver
  392. * HPT372N 5 (HPT372) 2 UDMA133
  393. * HPT302 6 (HPT302) * Other driver
  394. * HPT302N 6 (HPT302) > 1 UDMA133
  395. * HPT371 7 (HPT371) * Other driver
  396. * HPT371N 7 (HPT371) > 1 UDMA133
  397. * HPT374 8 (HPT374) * Other driver
  398. * HPT372N 9 (HPT372N) * UDMA133
  399. *
  400. * (1) UDMA133 support depends on the bus clock
  401. */
  402. static int hpt3x2n_init_one(struct pci_dev *dev, const struct pci_device_id *id)
  403. {
  404. /* HPT372N - UDMA133 */
  405. static const struct ata_port_info info_hpt372n = {
  406. .flags = ATA_FLAG_SLAVE_POSS,
  407. .pio_mask = ATA_PIO4,
  408. .mwdma_mask = ATA_MWDMA2,
  409. .udma_mask = ATA_UDMA6,
  410. .port_ops = &hpt372n_port_ops
  411. };
  412. /* HPT302N and HPT371N - UDMA133 */
  413. static const struct ata_port_info info_hpt3xxn = {
  414. .flags = ATA_FLAG_SLAVE_POSS,
  415. .pio_mask = ATA_PIO4,
  416. .mwdma_mask = ATA_MWDMA2,
  417. .udma_mask = ATA_UDMA6,
  418. .port_ops = &hpt3xxn_port_ops
  419. };
  420. const struct ata_port_info *ppi[] = { &info_hpt3xxn, NULL };
  421. u8 rev = dev->revision;
  422. u8 irqmask;
  423. unsigned int pci_mhz;
  424. unsigned int f_low, f_high;
  425. int adjust;
  426. unsigned long iobase = pci_resource_start(dev, 4);
  427. void *hpriv = (void *)USE_DPLL;
  428. int rc;
  429. rc = pcim_enable_device(dev);
  430. if (rc)
  431. return rc;
  432. switch (dev->device) {
  433. case PCI_DEVICE_ID_TTI_HPT366:
  434. /* 372N if rev >= 6 */
  435. if (rev < 6)
  436. return -ENODEV;
  437. goto hpt372n;
  438. case PCI_DEVICE_ID_TTI_HPT371:
  439. /* 371N if rev >= 2 */
  440. if (rev < 2)
  441. return -ENODEV;
  442. break;
  443. case PCI_DEVICE_ID_TTI_HPT372:
  444. /* 372N if rev >= 2 */
  445. if (rev < 2)
  446. return -ENODEV;
  447. goto hpt372n;
  448. case PCI_DEVICE_ID_TTI_HPT302:
  449. /* 302N if rev >= 2 */
  450. if (rev < 2)
  451. return -ENODEV;
  452. break;
  453. case PCI_DEVICE_ID_TTI_HPT372N:
  454. hpt372n:
  455. ppi[0] = &info_hpt372n;
  456. break;
  457. default:
  458. pr_err("PCI table is bogus, please report (%d)\n", dev->device);
  459. return -ENODEV;
  460. }
  461. /* Ok so this is a chip we support */
  462. pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
  463. pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
  464. pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
  465. pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
  466. pci_read_config_byte(dev, 0x5A, &irqmask);
  467. irqmask &= ~0x10;
  468. pci_write_config_byte(dev, 0x5a, irqmask);
  469. /*
  470. * HPT371 chips physically have only one channel, the secondary one,
  471. * but the primary channel registers do exist! Go figure...
  472. * So, we manually disable the non-existing channel here
  473. * (if the BIOS hasn't done this already).
  474. */
  475. if (dev->device == PCI_DEVICE_ID_TTI_HPT371) {
  476. u8 mcr1;
  477. pci_read_config_byte(dev, 0x50, &mcr1);
  478. mcr1 &= ~0x04;
  479. pci_write_config_byte(dev, 0x50, mcr1);
  480. }
  481. /*
  482. * Tune the PLL. HPT recommend using 75 for SATA, 66 for UDMA133 or
  483. * 50 for UDMA100. Right now we always use 66
  484. */
  485. pci_mhz = hpt3x2n_pci_clock(dev);
  486. f_low = (pci_mhz * 48) / 66; /* PCI Mhz for 66Mhz DPLL */
  487. f_high = f_low + 2; /* Tolerance */
  488. pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100);
  489. /* PLL clock */
  490. pci_write_config_byte(dev, 0x5B, 0x21);
  491. /* Unlike the 37x we don't try jiggling the frequency */
  492. for (adjust = 0; adjust < 8; adjust++) {
  493. if (hpt3xn_calibrate_dpll(dev))
  494. break;
  495. pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low);
  496. }
  497. if (adjust == 8) {
  498. pr_err("DPLL did not stabilize!\n");
  499. return -ENODEV;
  500. }
  501. pr_info("bus clock %dMHz, using 66MHz DPLL\n", pci_mhz);
  502. /*
  503. * Set our private data up. We only need a few flags
  504. * so we use it directly.
  505. */
  506. if (pci_mhz > 60)
  507. hpriv = (void *)(PCI66 | USE_DPLL);
  508. /*
  509. * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in
  510. * the MISC. register to stretch the UltraDMA Tss timing.
  511. * NOTE: This register is only writeable via I/O space.
  512. */
  513. if (dev->device == PCI_DEVICE_ID_TTI_HPT371)
  514. outb(inb(iobase + 0x9c) | 0x04, iobase + 0x9c);
  515. /* Now kick off ATA set up */
  516. return ata_pci_bmdma_init_one(dev, ppi, &hpt3x2n_sht, hpriv, 0);
  517. }
  518. static const struct pci_device_id hpt3x2n[] = {
  519. { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
  520. { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), },
  521. { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), },
  522. { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), },
  523. { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372N), },
  524. { },
  525. };
  526. static struct pci_driver hpt3x2n_pci_driver = {
  527. .name = DRV_NAME,
  528. .id_table = hpt3x2n,
  529. .probe = hpt3x2n_init_one,
  530. .remove = ata_pci_remove_one
  531. };
  532. module_pci_driver(hpt3x2n_pci_driver);
  533. MODULE_AUTHOR("Alan Cox");
  534. MODULE_DESCRIPTION("low-level driver for the Highpoint HPT3xxN");
  535. MODULE_LICENSE("GPL");
  536. MODULE_DEVICE_TABLE(pci, hpt3x2n);
  537. MODULE_VERSION(DRV_VERSION);