pata_ftide010.c 16 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Faraday Technology FTIDE010 driver
  4. * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
  5. *
  6. * Includes portions of the SL2312/SL3516/Gemini PATA driver
  7. * Copyright (C) 2003 StorLine, Inc <jason@storlink.com.tw>
  8. * Copyright (C) 2009 Janos Laube <janos.dev@gmail.com>
  9. * Copyright (C) 2010 Frederic Pecourt <opengemini@free.fr>
  10. * Copyright (C) 2011 Tobias Waldvogel <tobias.waldvogel@gmail.com>
  11. */
  12. #include <linux/platform_device.h>
  13. #include <linux/module.h>
  14. #include <linux/libata.h>
  15. #include <linux/bitops.h>
  16. #include <linux/of_address.h>
  17. #include <linux/of_device.h>
  18. #include <linux/clk.h>
  19. #include "sata_gemini.h"
  20. #define DRV_NAME "pata_ftide010"
  21. /**
  22. * struct ftide010 - state container for the Faraday FTIDE010
  23. * @dev: pointer back to the device representing this controller
  24. * @base: remapped I/O space address
  25. * @pclk: peripheral clock for the IDE block
  26. * @host: pointer to the ATA host for this device
  27. * @master_cbl: master cable type
  28. * @slave_cbl: slave cable type
  29. * @sg: Gemini SATA bridge pointer, if running on the Gemini
  30. * @master_to_sata0: Gemini SATA bridge: the ATA master is connected
  31. * to the SATA0 bridge
  32. * @slave_to_sata0: Gemini SATA bridge: the ATA slave is connected
  33. * to the SATA0 bridge
  34. * @master_to_sata1: Gemini SATA bridge: the ATA master is connected
  35. * to the SATA1 bridge
  36. * @slave_to_sata1: Gemini SATA bridge: the ATA slave is connected
  37. * to the SATA1 bridge
  38. */
  39. struct ftide010 {
  40. struct device *dev;
  41. void __iomem *base;
  42. struct clk *pclk;
  43. struct ata_host *host;
  44. unsigned int master_cbl;
  45. unsigned int slave_cbl;
  46. /* Gemini-specific properties */
  47. struct sata_gemini *sg;
  48. bool master_to_sata0;
  49. bool slave_to_sata0;
  50. bool master_to_sata1;
  51. bool slave_to_sata1;
  52. };
  53. #define FTIDE010_DMA_REG 0x00
  54. #define FTIDE010_DMA_STATUS 0x02
  55. #define FTIDE010_IDE_BMDTPR 0x04
  56. #define FTIDE010_IDE_DEVICE_ID 0x08
  57. #define FTIDE010_PIO_TIMING 0x10
  58. #define FTIDE010_MWDMA_TIMING 0x11
  59. #define FTIDE010_UDMA_TIMING0 0x12 /* Master */
  60. #define FTIDE010_UDMA_TIMING1 0x13 /* Slave */
  61. #define FTIDE010_CLK_MOD 0x14
  62. /* These registers are mapped directly to the IDE registers */
  63. #define FTIDE010_CMD_DATA 0x20
  64. #define FTIDE010_ERROR_FEATURES 0x21
  65. #define FTIDE010_NSECT 0x22
  66. #define FTIDE010_LBAL 0x23
  67. #define FTIDE010_LBAM 0x24
  68. #define FTIDE010_LBAH 0x25
  69. #define FTIDE010_DEVICE 0x26
  70. #define FTIDE010_STATUS_COMMAND 0x27
  71. #define FTIDE010_ALTSTAT_CTRL 0x36
  72. /* Set this bit for UDMA mode 5 and 6 */
  73. #define FTIDE010_UDMA_TIMING_MODE_56 BIT(7)
  74. /* 0 = 50 MHz, 1 = 66 MHz */
  75. #define FTIDE010_CLK_MOD_DEV0_CLK_SEL BIT(0)
  76. #define FTIDE010_CLK_MOD_DEV1_CLK_SEL BIT(1)
  77. /* Enable UDMA on a device */
  78. #define FTIDE010_CLK_MOD_DEV0_UDMA_EN BIT(4)
  79. #define FTIDE010_CLK_MOD_DEV1_UDMA_EN BIT(5)
  80. static struct scsi_host_template pata_ftide010_sht = {
  81. ATA_BMDMA_SHT(DRV_NAME),
  82. };
  83. /*
  84. * Bus timings
  85. *
  86. * The unit of the below required timings is two clock periods of the ATA
  87. * reference clock which is 30 nanoseconds per unit at 66MHz and 20
  88. * nanoseconds per unit at 50 MHz. The PIO timings assume 33MHz speed for
  89. * PIO.
  90. *
  91. * pio_active_time: array of 5 elements for T2 timing for Mode 0,
  92. * 1, 2, 3 and 4. Range 0..15.
  93. * pio_recovery_time: array of 5 elements for T2l timing for Mode 0,
  94. * 1, 2, 3 and 4. Range 0..15.
  95. * mdma_50_active_time: array of 4 elements for Td timing for multi
  96. * word DMA, Mode 0, 1, and 2 at 50 MHz. Range 0..15.
  97. * mdma_50_recovery_time: array of 4 elements for Tk timing for
  98. * multi word DMA, Mode 0, 1 and 2 at 50 MHz. Range 0..15.
  99. * mdma_66_active_time: array of 4 elements for Td timing for multi
  100. * word DMA, Mode 0, 1 and 2 at 66 MHz. Range 0..15.
  101. * mdma_66_recovery_time: array of 4 elements for Tk timing for
  102. * multi word DMA, Mode 0, 1 and 2 at 66 MHz. Range 0..15.
  103. * udma_50_setup_time: array of 4 elements for Tvds timing for ultra
  104. * DMA, Mode 0, 1, 2, 3, 4 and 5 at 50 MHz. Range 0..7.
  105. * udma_50_hold_time: array of 4 elements for Tdvh timing for
  106. * multi word DMA, Mode 0, 1, 2, 3, 4 and 5 at 50 MHz, Range 0..7.
  107. * udma_66_setup_time: array of 4 elements for Tvds timing for multi
  108. * word DMA, Mode 0, 1, 2, 3, 4, 5 and 6 at 66 MHz. Range 0..7.
  109. * udma_66_hold_time: array of 4 elements for Tdvh timing for
  110. * multi word DMA, Mode 0, 1, 2, 3, 4, 5 and 6 at 66 MHz. Range 0..7.
  111. */
  112. static const u8 pio_active_time[5] = {10, 10, 10, 3, 3};
  113. static const u8 pio_recovery_time[5] = {10, 3, 1, 3, 1};
  114. static const u8 mwdma_50_active_time[3] = {6, 2, 2};
  115. static const u8 mwdma_50_recovery_time[3] = {6, 2, 1};
  116. static const u8 mwdma_66_active_time[3] = {8, 3, 3};
  117. static const u8 mwdma_66_recovery_time[3] = {8, 2, 1};
  118. static const u8 udma_50_setup_time[6] = {3, 3, 2, 2, 1, 1};
  119. static const u8 udma_50_hold_time[6] = {3, 1, 1, 1, 1, 1};
  120. static const u8 udma_66_setup_time[7] = {4, 4, 3, 2, };
  121. static const u8 udma_66_hold_time[7] = {};
  122. /*
  123. * We set 66 MHz for all MWDMA modes
  124. */
  125. static const bool set_mdma_66_mhz[] = { true, true, true, true };
  126. /*
  127. * We set 66 MHz for UDMA modes 3, 4 and 6 and no others
  128. */
  129. static const bool set_udma_66_mhz[] = { false, false, false, true, true, false, true };
  130. static void ftide010_set_dmamode(struct ata_port *ap, struct ata_device *adev)
  131. {
  132. struct ftide010 *ftide = ap->host->private_data;
  133. u8 speed = adev->dma_mode;
  134. u8 devno = adev->devno & 1;
  135. u8 udma_en_mask;
  136. u8 f66m_en_mask;
  137. u8 clkreg;
  138. u8 timreg;
  139. u8 i;
  140. /* Target device 0 (master) or 1 (slave) */
  141. if (!devno) {
  142. udma_en_mask = FTIDE010_CLK_MOD_DEV0_UDMA_EN;
  143. f66m_en_mask = FTIDE010_CLK_MOD_DEV0_CLK_SEL;
  144. } else {
  145. udma_en_mask = FTIDE010_CLK_MOD_DEV1_UDMA_EN;
  146. f66m_en_mask = FTIDE010_CLK_MOD_DEV1_CLK_SEL;
  147. }
  148. clkreg = readb(ftide->base + FTIDE010_CLK_MOD);
  149. clkreg &= ~udma_en_mask;
  150. clkreg &= ~f66m_en_mask;
  151. if (speed & XFER_UDMA_0) {
  152. i = speed & ~XFER_UDMA_0;
  153. dev_dbg(ftide->dev, "set UDMA mode %02x, index %d\n",
  154. speed, i);
  155. clkreg |= udma_en_mask;
  156. if (set_udma_66_mhz[i]) {
  157. clkreg |= f66m_en_mask;
  158. timreg = udma_66_setup_time[i] << 4 |
  159. udma_66_hold_time[i];
  160. } else {
  161. timreg = udma_50_setup_time[i] << 4 |
  162. udma_50_hold_time[i];
  163. }
  164. /* A special bit needs to be set for modes 5 and 6 */
  165. if (i >= 5)
  166. timreg |= FTIDE010_UDMA_TIMING_MODE_56;
  167. dev_dbg(ftide->dev, "UDMA write clkreg = %02x, timreg = %02x\n",
  168. clkreg, timreg);
  169. writeb(clkreg, ftide->base + FTIDE010_CLK_MOD);
  170. writeb(timreg, ftide->base + FTIDE010_UDMA_TIMING0 + devno);
  171. } else {
  172. i = speed & ~XFER_MW_DMA_0;
  173. dev_dbg(ftide->dev, "set MWDMA mode %02x, index %d\n",
  174. speed, i);
  175. if (set_mdma_66_mhz[i]) {
  176. clkreg |= f66m_en_mask;
  177. timreg = mwdma_66_active_time[i] << 4 |
  178. mwdma_66_recovery_time[i];
  179. } else {
  180. timreg = mwdma_50_active_time[i] << 4 |
  181. mwdma_50_recovery_time[i];
  182. }
  183. dev_dbg(ftide->dev,
  184. "MWDMA write clkreg = %02x, timreg = %02x\n",
  185. clkreg, timreg);
  186. /* This will affect all devices */
  187. writeb(clkreg, ftide->base + FTIDE010_CLK_MOD);
  188. writeb(timreg, ftide->base + FTIDE010_MWDMA_TIMING);
  189. }
  190. /*
  191. * Store the current device (master or slave) in ap->private_data
  192. * so that .qc_issue() can detect if this changes and reprogram
  193. * the DMA settings.
  194. */
  195. ap->private_data = adev;
  196. return;
  197. }
  198. static void ftide010_set_piomode(struct ata_port *ap, struct ata_device *adev)
  199. {
  200. struct ftide010 *ftide = ap->host->private_data;
  201. u8 pio = adev->pio_mode - XFER_PIO_0;
  202. dev_dbg(ftide->dev, "set PIO mode %02x, index %d\n",
  203. adev->pio_mode, pio);
  204. writeb(pio_active_time[pio] << 4 | pio_recovery_time[pio],
  205. ftide->base + FTIDE010_PIO_TIMING);
  206. }
  207. /*
  208. * We implement our own qc_issue() callback since we may need to set up
  209. * the timings differently for master and slave transfers: the CLK_MOD_REG
  210. * and MWDMA_TIMING_REG is shared between master and slave, so reprogramming
  211. * this may be necessary.
  212. */
  213. static unsigned int ftide010_qc_issue(struct ata_queued_cmd *qc)
  214. {
  215. struct ata_port *ap = qc->ap;
  216. struct ata_device *adev = qc->dev;
  217. /*
  218. * If the device changed, i.e. slave->master, master->slave,
  219. * then set up the DMA mode again so we are sure the timings
  220. * are correct.
  221. */
  222. if (adev != ap->private_data && ata_dma_enabled(adev))
  223. ftide010_set_dmamode(ap, adev);
  224. return ata_bmdma_qc_issue(qc);
  225. }
  226. static struct ata_port_operations pata_ftide010_port_ops = {
  227. .inherits = &ata_bmdma_port_ops,
  228. .set_dmamode = ftide010_set_dmamode,
  229. .set_piomode = ftide010_set_piomode,
  230. .qc_issue = ftide010_qc_issue,
  231. };
  232. static struct ata_port_info ftide010_port_info = {
  233. .flags = ATA_FLAG_SLAVE_POSS,
  234. .mwdma_mask = ATA_MWDMA2,
  235. .udma_mask = ATA_UDMA6,
  236. .pio_mask = ATA_PIO4,
  237. .port_ops = &pata_ftide010_port_ops,
  238. };
  239. #if IS_ENABLED(CONFIG_SATA_GEMINI)
  240. static int pata_ftide010_gemini_port_start(struct ata_port *ap)
  241. {
  242. struct ftide010 *ftide = ap->host->private_data;
  243. struct device *dev = ftide->dev;
  244. struct sata_gemini *sg = ftide->sg;
  245. int bridges = 0;
  246. int ret;
  247. ret = ata_bmdma_port_start(ap);
  248. if (ret)
  249. return ret;
  250. if (ftide->master_to_sata0) {
  251. dev_info(dev, "SATA0 (master) start\n");
  252. ret = gemini_sata_start_bridge(sg, 0);
  253. if (!ret)
  254. bridges++;
  255. }
  256. if (ftide->master_to_sata1) {
  257. dev_info(dev, "SATA1 (master) start\n");
  258. ret = gemini_sata_start_bridge(sg, 1);
  259. if (!ret)
  260. bridges++;
  261. }
  262. /* Avoid double-starting */
  263. if (ftide->slave_to_sata0 && !ftide->master_to_sata0) {
  264. dev_info(dev, "SATA0 (slave) start\n");
  265. ret = gemini_sata_start_bridge(sg, 0);
  266. if (!ret)
  267. bridges++;
  268. }
  269. /* Avoid double-starting */
  270. if (ftide->slave_to_sata1 && !ftide->master_to_sata1) {
  271. dev_info(dev, "SATA1 (slave) start\n");
  272. ret = gemini_sata_start_bridge(sg, 1);
  273. if (!ret)
  274. bridges++;
  275. }
  276. dev_info(dev, "brought %d bridges online\n", bridges);
  277. return (bridges > 0) ? 0 : -EINVAL; // -ENODEV;
  278. }
  279. static void pata_ftide010_gemini_port_stop(struct ata_port *ap)
  280. {
  281. struct ftide010 *ftide = ap->host->private_data;
  282. struct device *dev = ftide->dev;
  283. struct sata_gemini *sg = ftide->sg;
  284. if (ftide->master_to_sata0) {
  285. dev_info(dev, "SATA0 (master) stop\n");
  286. gemini_sata_stop_bridge(sg, 0);
  287. }
  288. if (ftide->master_to_sata1) {
  289. dev_info(dev, "SATA1 (master) stop\n");
  290. gemini_sata_stop_bridge(sg, 1);
  291. }
  292. /* Avoid double-stopping */
  293. if (ftide->slave_to_sata0 && !ftide->master_to_sata0) {
  294. dev_info(dev, "SATA0 (slave) stop\n");
  295. gemini_sata_stop_bridge(sg, 0);
  296. }
  297. /* Avoid double-stopping */
  298. if (ftide->slave_to_sata1 && !ftide->master_to_sata1) {
  299. dev_info(dev, "SATA1 (slave) stop\n");
  300. gemini_sata_stop_bridge(sg, 1);
  301. }
  302. }
  303. static int pata_ftide010_gemini_cable_detect(struct ata_port *ap)
  304. {
  305. struct ftide010 *ftide = ap->host->private_data;
  306. /*
  307. * Return the master cable, I have no clue how to return a different
  308. * cable for the slave than for the master.
  309. */
  310. return ftide->master_cbl;
  311. }
  312. static int pata_ftide010_gemini_init(struct ftide010 *ftide,
  313. struct ata_port_info *pi,
  314. bool is_ata1)
  315. {
  316. struct device *dev = ftide->dev;
  317. struct sata_gemini *sg;
  318. enum gemini_muxmode muxmode;
  319. /* Look up SATA bridge */
  320. sg = gemini_sata_bridge_get();
  321. if (IS_ERR(sg))
  322. return PTR_ERR(sg);
  323. ftide->sg = sg;
  324. muxmode = gemini_sata_get_muxmode(sg);
  325. /* Special ops */
  326. pata_ftide010_port_ops.port_start =
  327. pata_ftide010_gemini_port_start;
  328. pata_ftide010_port_ops.port_stop =
  329. pata_ftide010_gemini_port_stop;
  330. pata_ftide010_port_ops.cable_detect =
  331. pata_ftide010_gemini_cable_detect;
  332. /* Flag port as SATA-capable */
  333. if (gemini_sata_bridge_enabled(sg, is_ata1))
  334. pi->flags |= ATA_FLAG_SATA;
  335. /* This device has broken DMA, only PIO works */
  336. if (of_machine_is_compatible("itian,sq201")) {
  337. pi->mwdma_mask = 0;
  338. pi->udma_mask = 0;
  339. }
  340. /*
  341. * We assume that a simple 40-wire cable is used in the PATA mode.
  342. * if you're adding a system using the PATA interface, make sure
  343. * the right cable is set up here, it might be necessary to use
  344. * special hardware detection or encode the cable type in the device
  345. * tree with special properties.
  346. */
  347. if (!is_ata1) {
  348. switch (muxmode) {
  349. case GEMINI_MUXMODE_0:
  350. ftide->master_cbl = ATA_CBL_SATA;
  351. ftide->slave_cbl = ATA_CBL_PATA40;
  352. ftide->master_to_sata0 = true;
  353. break;
  354. case GEMINI_MUXMODE_1:
  355. ftide->master_cbl = ATA_CBL_SATA;
  356. ftide->slave_cbl = ATA_CBL_NONE;
  357. ftide->master_to_sata0 = true;
  358. break;
  359. case GEMINI_MUXMODE_2:
  360. ftide->master_cbl = ATA_CBL_PATA40;
  361. ftide->slave_cbl = ATA_CBL_PATA40;
  362. break;
  363. case GEMINI_MUXMODE_3:
  364. ftide->master_cbl = ATA_CBL_SATA;
  365. ftide->slave_cbl = ATA_CBL_SATA;
  366. ftide->master_to_sata0 = true;
  367. ftide->slave_to_sata1 = true;
  368. break;
  369. }
  370. } else {
  371. switch (muxmode) {
  372. case GEMINI_MUXMODE_0:
  373. ftide->master_cbl = ATA_CBL_SATA;
  374. ftide->slave_cbl = ATA_CBL_NONE;
  375. ftide->master_to_sata1 = true;
  376. break;
  377. case GEMINI_MUXMODE_1:
  378. ftide->master_cbl = ATA_CBL_SATA;
  379. ftide->slave_cbl = ATA_CBL_PATA40;
  380. ftide->master_to_sata1 = true;
  381. break;
  382. case GEMINI_MUXMODE_2:
  383. ftide->master_cbl = ATA_CBL_SATA;
  384. ftide->slave_cbl = ATA_CBL_SATA;
  385. ftide->slave_to_sata0 = true;
  386. ftide->master_to_sata1 = true;
  387. break;
  388. case GEMINI_MUXMODE_3:
  389. ftide->master_cbl = ATA_CBL_PATA40;
  390. ftide->slave_cbl = ATA_CBL_PATA40;
  391. break;
  392. }
  393. }
  394. dev_info(dev, "set up Gemini PATA%d\n", is_ata1);
  395. return 0;
  396. }
  397. #else
  398. static int pata_ftide010_gemini_init(struct ftide010 *ftide,
  399. struct ata_port_info *pi,
  400. bool is_ata1)
  401. {
  402. return -ENOTSUPP;
  403. }
  404. #endif
  405. static int pata_ftide010_probe(struct platform_device *pdev)
  406. {
  407. struct device *dev = &pdev->dev;
  408. struct device_node *np = dev->of_node;
  409. struct ata_port_info pi = ftide010_port_info;
  410. const struct ata_port_info *ppi[] = { &pi, NULL };
  411. struct ftide010 *ftide;
  412. struct resource *res;
  413. int irq;
  414. int ret;
  415. int i;
  416. ftide = devm_kzalloc(dev, sizeof(*ftide), GFP_KERNEL);
  417. if (!ftide)
  418. return -ENOMEM;
  419. ftide->dev = dev;
  420. irq = platform_get_irq(pdev, 0);
  421. if (irq < 0)
  422. return irq;
  423. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  424. if (!res)
  425. return -ENODEV;
  426. ftide->base = devm_ioremap_resource(dev, res);
  427. if (IS_ERR(ftide->base))
  428. return PTR_ERR(ftide->base);
  429. ftide->pclk = devm_clk_get(dev, "PCLK");
  430. if (!IS_ERR(ftide->pclk)) {
  431. ret = clk_prepare_enable(ftide->pclk);
  432. if (ret) {
  433. dev_err(dev, "failed to enable PCLK\n");
  434. return ret;
  435. }
  436. }
  437. /* Some special Cortina Gemini init, if needed */
  438. if (of_device_is_compatible(np, "cortina,gemini-pata")) {
  439. /*
  440. * We need to know which instance is probing (the
  441. * Gemini has two instances of FTIDE010) and we do
  442. * this simply by looking at the physical base
  443. * address, which is 0x63400000 for ATA1, else we
  444. * are ATA0. This will also set up the cable types.
  445. */
  446. ret = pata_ftide010_gemini_init(ftide,
  447. &pi,
  448. (res->start == 0x63400000));
  449. if (ret)
  450. goto err_dis_clk;
  451. } else {
  452. /* Else assume we are connected using PATA40 */
  453. ftide->master_cbl = ATA_CBL_PATA40;
  454. ftide->slave_cbl = ATA_CBL_PATA40;
  455. }
  456. ftide->host = ata_host_alloc_pinfo(dev, ppi, 1);
  457. if (!ftide->host) {
  458. ret = -ENOMEM;
  459. goto err_dis_clk;
  460. }
  461. ftide->host->private_data = ftide;
  462. for (i = 0; i < ftide->host->n_ports; i++) {
  463. struct ata_port *ap = ftide->host->ports[i];
  464. struct ata_ioports *ioaddr = &ap->ioaddr;
  465. ioaddr->bmdma_addr = ftide->base + FTIDE010_DMA_REG;
  466. ioaddr->cmd_addr = ftide->base + FTIDE010_CMD_DATA;
  467. ioaddr->ctl_addr = ftide->base + FTIDE010_ALTSTAT_CTRL;
  468. ioaddr->altstatus_addr = ftide->base + FTIDE010_ALTSTAT_CTRL;
  469. ata_sff_std_ports(ioaddr);
  470. }
  471. dev_info(dev, "device ID %08x, irq %d, reg %pR\n",
  472. readl(ftide->base + FTIDE010_IDE_DEVICE_ID), irq, res);
  473. ret = ata_host_activate(ftide->host, irq, ata_bmdma_interrupt,
  474. 0, &pata_ftide010_sht);
  475. if (ret)
  476. goto err_dis_clk;
  477. return 0;
  478. err_dis_clk:
  479. if (!IS_ERR(ftide->pclk))
  480. clk_disable_unprepare(ftide->pclk);
  481. return ret;
  482. }
  483. static int pata_ftide010_remove(struct platform_device *pdev)
  484. {
  485. struct ata_host *host = platform_get_drvdata(pdev);
  486. struct ftide010 *ftide = host->private_data;
  487. ata_host_detach(ftide->host);
  488. if (!IS_ERR(ftide->pclk))
  489. clk_disable_unprepare(ftide->pclk);
  490. return 0;
  491. }
  492. static const struct of_device_id pata_ftide010_of_match[] = {
  493. {
  494. .compatible = "faraday,ftide010",
  495. },
  496. {},
  497. };
  498. static struct platform_driver pata_ftide010_driver = {
  499. .driver = {
  500. .name = DRV_NAME,
  501. .of_match_table = of_match_ptr(pata_ftide010_of_match),
  502. },
  503. .probe = pata_ftide010_probe,
  504. .remove = pata_ftide010_remove,
  505. };
  506. module_platform_driver(pata_ftide010_driver);
  507. MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
  508. MODULE_LICENSE("GPL");
  509. MODULE_ALIAS("platform:" DRV_NAME);