pata_bk3710.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Palmchip BK3710 PATA controller driver
  4. *
  5. * Copyright (c) 2017 Samsung Electronics Co., Ltd.
  6. * http://www.samsung.com
  7. *
  8. * Based on palm_bk3710.c:
  9. *
  10. * Copyright (C) 2006 Texas Instruments.
  11. * Copyright (C) 2007 MontaVista Software, Inc., <source@mvista.com>
  12. */
  13. #include <linux/ata.h>
  14. #include <linux/clk.h>
  15. #include <linux/delay.h>
  16. #include <linux/init.h>
  17. #include <linux/ioport.h>
  18. #include <linux/kernel.h>
  19. #include <linux/libata.h>
  20. #include <linux/module.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/types.h>
  23. #define DRV_NAME "pata_bk3710"
  24. #define BK3710_TF_OFFSET 0x1F0
  25. #define BK3710_CTL_OFFSET 0x3F6
  26. #define BK3710_BMISP 0x02
  27. #define BK3710_IDETIMP 0x40
  28. #define BK3710_UDMACTL 0x48
  29. #define BK3710_MISCCTL 0x50
  30. #define BK3710_REGSTB 0x54
  31. #define BK3710_REGRCVR 0x58
  32. #define BK3710_DATSTB 0x5C
  33. #define BK3710_DATRCVR 0x60
  34. #define BK3710_DMASTB 0x64
  35. #define BK3710_DMARCVR 0x68
  36. #define BK3710_UDMASTB 0x6C
  37. #define BK3710_UDMATRP 0x70
  38. #define BK3710_UDMAENV 0x74
  39. #define BK3710_IORDYTMP 0x78
  40. static struct scsi_host_template pata_bk3710_sht = {
  41. ATA_BMDMA_SHT(DRV_NAME),
  42. };
  43. static unsigned int ideclk_period; /* in nanoseconds */
  44. struct pata_bk3710_udmatiming {
  45. unsigned int rptime; /* tRP -- Ready to pause time (nsec) */
  46. unsigned int cycletime; /* tCYCTYP2/2 -- avg Cycle Time (nsec) */
  47. /* tENV is always a minimum of 20 nsec */
  48. };
  49. static const struct pata_bk3710_udmatiming pata_bk3710_udmatimings[6] = {
  50. { 160, 240 / 2 }, /* UDMA Mode 0 */
  51. { 125, 160 / 2 }, /* UDMA Mode 1 */
  52. { 100, 120 / 2 }, /* UDMA Mode 2 */
  53. { 100, 90 / 2 }, /* UDMA Mode 3 */
  54. { 100, 60 / 2 }, /* UDMA Mode 4 */
  55. { 85, 40 / 2 }, /* UDMA Mode 5 */
  56. };
  57. static void pata_bk3710_setudmamode(void __iomem *base, unsigned int dev,
  58. unsigned int mode)
  59. {
  60. u32 val32;
  61. u16 val16;
  62. u8 tenv, trp, t0;
  63. /* DMA Data Setup */
  64. t0 = DIV_ROUND_UP(pata_bk3710_udmatimings[mode].cycletime,
  65. ideclk_period) - 1;
  66. tenv = DIV_ROUND_UP(20, ideclk_period) - 1;
  67. trp = DIV_ROUND_UP(pata_bk3710_udmatimings[mode].rptime,
  68. ideclk_period) - 1;
  69. /* udmastb Ultra DMA Access Strobe Width */
  70. val32 = ioread32(base + BK3710_UDMASTB) & (0xFF << (dev ? 0 : 8));
  71. val32 |= t0 << (dev ? 8 : 0);
  72. iowrite32(val32, base + BK3710_UDMASTB);
  73. /* udmatrp Ultra DMA Ready to Pause Time */
  74. val32 = ioread32(base + BK3710_UDMATRP) & (0xFF << (dev ? 0 : 8));
  75. val32 |= trp << (dev ? 8 : 0);
  76. iowrite32(val32, base + BK3710_UDMATRP);
  77. /* udmaenv Ultra DMA envelop Time */
  78. val32 = ioread32(base + BK3710_UDMAENV) & (0xFF << (dev ? 0 : 8));
  79. val32 |= tenv << (dev ? 8 : 0);
  80. iowrite32(val32, base + BK3710_UDMAENV);
  81. /* Enable UDMA for Device */
  82. val16 = ioread16(base + BK3710_UDMACTL) | (1 << dev);
  83. iowrite16(val16, base + BK3710_UDMACTL);
  84. }
  85. static void pata_bk3710_setmwdmamode(void __iomem *base, unsigned int dev,
  86. unsigned short min_cycle,
  87. unsigned int mode)
  88. {
  89. const struct ata_timing *t;
  90. int cycletime;
  91. u32 val32;
  92. u16 val16;
  93. u8 td, tkw, t0;
  94. t = ata_timing_find_mode(mode);
  95. cycletime = max_t(int, t->cycle, min_cycle);
  96. /* DMA Data Setup */
  97. t0 = DIV_ROUND_UP(cycletime, ideclk_period);
  98. td = DIV_ROUND_UP(t->active, ideclk_period);
  99. tkw = t0 - td - 1;
  100. td--;
  101. val32 = ioread32(base + BK3710_DMASTB) & (0xFF << (dev ? 0 : 8));
  102. val32 |= td << (dev ? 8 : 0);
  103. iowrite32(val32, base + BK3710_DMASTB);
  104. val32 = ioread32(base + BK3710_DMARCVR) & (0xFF << (dev ? 0 : 8));
  105. val32 |= tkw << (dev ? 8 : 0);
  106. iowrite32(val32, base + BK3710_DMARCVR);
  107. /* Disable UDMA for Device */
  108. val16 = ioread16(base + BK3710_UDMACTL) & ~(1 << dev);
  109. iowrite16(val16, base + BK3710_UDMACTL);
  110. }
  111. static void pata_bk3710_set_dmamode(struct ata_port *ap,
  112. struct ata_device *adev)
  113. {
  114. void __iomem *base = (void __iomem *)ap->ioaddr.bmdma_addr;
  115. int is_slave = adev->devno;
  116. const u8 xferspeed = adev->dma_mode;
  117. if (xferspeed >= XFER_UDMA_0)
  118. pata_bk3710_setudmamode(base, is_slave,
  119. xferspeed - XFER_UDMA_0);
  120. else
  121. pata_bk3710_setmwdmamode(base, is_slave,
  122. adev->id[ATA_ID_EIDE_DMA_MIN],
  123. xferspeed);
  124. }
  125. static void pata_bk3710_setpiomode(void __iomem *base, struct ata_device *pair,
  126. unsigned int dev, unsigned int cycletime,
  127. unsigned int mode)
  128. {
  129. const struct ata_timing *t;
  130. u32 val32;
  131. u8 t2, t2i, t0;
  132. t = ata_timing_find_mode(XFER_PIO_0 + mode);
  133. /* PIO Data Setup */
  134. t0 = DIV_ROUND_UP(cycletime, ideclk_period);
  135. t2 = DIV_ROUND_UP(t->active, ideclk_period);
  136. t2i = t0 - t2 - 1;
  137. t2--;
  138. val32 = ioread32(base + BK3710_DATSTB) & (0xFF << (dev ? 0 : 8));
  139. val32 |= t2 << (dev ? 8 : 0);
  140. iowrite32(val32, base + BK3710_DATSTB);
  141. val32 = ioread32(base + BK3710_DATRCVR) & (0xFF << (dev ? 0 : 8));
  142. val32 |= t2i << (dev ? 8 : 0);
  143. iowrite32(val32, base + BK3710_DATRCVR);
  144. /* FIXME: this is broken also in the old driver */
  145. if (pair) {
  146. u8 mode2 = pair->pio_mode - XFER_PIO_0;
  147. if (mode2 < mode)
  148. mode = mode2;
  149. }
  150. /* TASKFILE Setup */
  151. t0 = DIV_ROUND_UP(t->cyc8b, ideclk_period);
  152. t2 = DIV_ROUND_UP(t->act8b, ideclk_period);
  153. t2i = t0 - t2 - 1;
  154. t2--;
  155. val32 = ioread32(base + BK3710_REGSTB) & (0xFF << (dev ? 0 : 8));
  156. val32 |= t2 << (dev ? 8 : 0);
  157. iowrite32(val32, base + BK3710_REGSTB);
  158. val32 = ioread32(base + BK3710_REGRCVR) & (0xFF << (dev ? 0 : 8));
  159. val32 |= t2i << (dev ? 8 : 0);
  160. iowrite32(val32, base + BK3710_REGRCVR);
  161. }
  162. static void pata_bk3710_set_piomode(struct ata_port *ap,
  163. struct ata_device *adev)
  164. {
  165. void __iomem *base = (void __iomem *)ap->ioaddr.bmdma_addr;
  166. struct ata_device *pair = ata_dev_pair(adev);
  167. const struct ata_timing *t = ata_timing_find_mode(adev->pio_mode);
  168. const u16 *id = adev->id;
  169. unsigned int cycle_time = 0;
  170. int is_slave = adev->devno;
  171. const u8 pio = adev->pio_mode - XFER_PIO_0;
  172. if (id[ATA_ID_FIELD_VALID] & 2) {
  173. if (ata_id_has_iordy(id))
  174. cycle_time = id[ATA_ID_EIDE_PIO_IORDY];
  175. else
  176. cycle_time = id[ATA_ID_EIDE_PIO];
  177. /* conservative "downgrade" for all pre-ATA2 drives */
  178. if (pio < 3 && cycle_time < t->cycle)
  179. cycle_time = 0; /* use standard timing */
  180. }
  181. if (!cycle_time)
  182. cycle_time = t->cycle;
  183. pata_bk3710_setpiomode(base, pair, is_slave, cycle_time, pio);
  184. }
  185. static void pata_bk3710_chipinit(void __iomem *base)
  186. {
  187. /*
  188. * REVISIT: the ATA reset signal needs to be managed through a
  189. * GPIO, which means it should come from platform_data. Until
  190. * we get and use such information, we have to trust that things
  191. * have been reset before we get here.
  192. */
  193. /*
  194. * Program the IDETIMP Register Value based on the following assumptions
  195. *
  196. * (ATA_IDETIMP_IDEEN , ENABLE ) |
  197. * (ATA_IDETIMP_PREPOST1 , DISABLE) |
  198. * (ATA_IDETIMP_PREPOST0 , DISABLE) |
  199. *
  200. * DM6446 silicon rev 2.1 and earlier have no observed net benefit
  201. * from enabling prefetch/postwrite.
  202. */
  203. iowrite16(BIT(15), base + BK3710_IDETIMP);
  204. /*
  205. * UDMACTL Ultra-ATA DMA Control
  206. * (ATA_UDMACTL_UDMAP1 , 0 ) |
  207. * (ATA_UDMACTL_UDMAP0 , 0 )
  208. *
  209. */
  210. iowrite16(0, base + BK3710_UDMACTL);
  211. /*
  212. * MISCCTL Miscellaneous Conrol Register
  213. * (ATA_MISCCTL_HWNHLD1P , 1 cycle)
  214. * (ATA_MISCCTL_HWNHLD0P , 1 cycle)
  215. * (ATA_MISCCTL_TIMORIDE , 1)
  216. */
  217. iowrite32(0x001, base + BK3710_MISCCTL);
  218. /*
  219. * IORDYTMP IORDY Timer for Primary Register
  220. * (ATA_IORDYTMP_IORDYTMP , DISABLE)
  221. */
  222. iowrite32(0, base + BK3710_IORDYTMP);
  223. /*
  224. * Configure BMISP Register
  225. * (ATA_BMISP_DMAEN1 , DISABLE ) |
  226. * (ATA_BMISP_DMAEN0 , DISABLE ) |
  227. * (ATA_BMISP_IORDYINT , CLEAR) |
  228. * (ATA_BMISP_INTRSTAT , CLEAR) |
  229. * (ATA_BMISP_DMAERROR , CLEAR)
  230. */
  231. iowrite16(0xE, base + BK3710_BMISP);
  232. pata_bk3710_setpiomode(base, NULL, 0, 600, 0);
  233. pata_bk3710_setpiomode(base, NULL, 1, 600, 0);
  234. }
  235. static struct ata_port_operations pata_bk3710_ports_ops = {
  236. .inherits = &ata_bmdma_port_ops,
  237. .cable_detect = ata_cable_80wire,
  238. .set_piomode = pata_bk3710_set_piomode,
  239. .set_dmamode = pata_bk3710_set_dmamode,
  240. };
  241. static int __init pata_bk3710_probe(struct platform_device *pdev)
  242. {
  243. struct clk *clk;
  244. struct resource *mem;
  245. struct ata_host *host;
  246. struct ata_port *ap;
  247. void __iomem *base;
  248. unsigned long rate;
  249. int irq;
  250. clk = devm_clk_get(&pdev->dev, NULL);
  251. if (IS_ERR(clk))
  252. return -ENODEV;
  253. clk_enable(clk);
  254. rate = clk_get_rate(clk);
  255. if (!rate)
  256. return -EINVAL;
  257. /* NOTE: round *down* to meet minimum timings; we count in clocks */
  258. ideclk_period = 1000000000UL / rate;
  259. mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  260. irq = platform_get_irq(pdev, 0);
  261. if (irq < 0) {
  262. pr_err(DRV_NAME ": failed to get IRQ resource\n");
  263. return irq;
  264. }
  265. base = devm_ioremap_resource(&pdev->dev, mem);
  266. if (IS_ERR(base))
  267. return PTR_ERR(base);
  268. /* configure the Palmchip controller */
  269. pata_bk3710_chipinit(base);
  270. /* allocate host */
  271. host = ata_host_alloc(&pdev->dev, 1);
  272. if (!host)
  273. return -ENOMEM;
  274. ap = host->ports[0];
  275. ap->ops = &pata_bk3710_ports_ops;
  276. ap->pio_mask = ATA_PIO4;
  277. ap->mwdma_mask = ATA_MWDMA2;
  278. ap->udma_mask = rate < 100000000 ? ATA_UDMA4 : ATA_UDMA5;
  279. ap->flags |= ATA_FLAG_SLAVE_POSS;
  280. ap->ioaddr.data_addr = base + BK3710_TF_OFFSET;
  281. ap->ioaddr.error_addr = base + BK3710_TF_OFFSET + 1;
  282. ap->ioaddr.feature_addr = base + BK3710_TF_OFFSET + 1;
  283. ap->ioaddr.nsect_addr = base + BK3710_TF_OFFSET + 2;
  284. ap->ioaddr.lbal_addr = base + BK3710_TF_OFFSET + 3;
  285. ap->ioaddr.lbam_addr = base + BK3710_TF_OFFSET + 4;
  286. ap->ioaddr.lbah_addr = base + BK3710_TF_OFFSET + 5;
  287. ap->ioaddr.device_addr = base + BK3710_TF_OFFSET + 6;
  288. ap->ioaddr.status_addr = base + BK3710_TF_OFFSET + 7;
  289. ap->ioaddr.command_addr = base + BK3710_TF_OFFSET + 7;
  290. ap->ioaddr.altstatus_addr = base + BK3710_CTL_OFFSET;
  291. ap->ioaddr.ctl_addr = base + BK3710_CTL_OFFSET;
  292. ap->ioaddr.bmdma_addr = base;
  293. ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx",
  294. (unsigned long)base + BK3710_TF_OFFSET,
  295. (unsigned long)base + BK3710_CTL_OFFSET);
  296. /* activate */
  297. return ata_host_activate(host, irq, ata_sff_interrupt, 0,
  298. &pata_bk3710_sht);
  299. }
  300. /* work with hotplug and coldplug */
  301. MODULE_ALIAS("platform:palm_bk3710");
  302. static struct platform_driver pata_bk3710_driver = {
  303. .driver = {
  304. .name = "palm_bk3710",
  305. },
  306. };
  307. static int __init pata_bk3710_init(void)
  308. {
  309. return platform_driver_probe(&pata_bk3710_driver, pata_bk3710_probe);
  310. }
  311. module_init(pata_bk3710_init);
  312. MODULE_LICENSE("GPL v2");