pata_atiixp.c 8.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * pata_atiixp.c - ATI PATA for new ATA layer
  4. * (C) 2005 Red Hat Inc
  5. * (C) 2009-2010 Bartlomiej Zolnierkiewicz
  6. *
  7. * Based on
  8. *
  9. * linux/drivers/ide/pci/atiixp.c Version 0.01-bart2 Feb. 26, 2004
  10. *
  11. * Copyright (C) 2003 ATI Inc. <hyu@ati.com>
  12. * Copyright (C) 2004 Bartlomiej Zolnierkiewicz
  13. *
  14. */
  15. #include <linux/kernel.h>
  16. #include <linux/module.h>
  17. #include <linux/pci.h>
  18. #include <linux/blkdev.h>
  19. #include <linux/delay.h>
  20. #include <scsi/scsi_host.h>
  21. #include <linux/libata.h>
  22. #include <linux/dmi.h>
  23. #define DRV_NAME "pata_atiixp"
  24. #define DRV_VERSION "0.4.6"
  25. enum {
  26. ATIIXP_IDE_PIO_TIMING = 0x40,
  27. ATIIXP_IDE_MWDMA_TIMING = 0x44,
  28. ATIIXP_IDE_PIO_CONTROL = 0x48,
  29. ATIIXP_IDE_PIO_MODE = 0x4a,
  30. ATIIXP_IDE_UDMA_CONTROL = 0x54,
  31. ATIIXP_IDE_UDMA_MODE = 0x56
  32. };
  33. static const struct dmi_system_id attixp_cable_override_dmi_table[] = {
  34. {
  35. /* Board has onboard PATA<->SATA converters */
  36. .ident = "MSI E350DM-E33",
  37. .matches = {
  38. DMI_MATCH(DMI_BOARD_VENDOR, "MSI"),
  39. DMI_MATCH(DMI_BOARD_NAME, "E350DM-E33(MS-7720)"),
  40. },
  41. },
  42. { }
  43. };
  44. static int atiixp_cable_detect(struct ata_port *ap)
  45. {
  46. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  47. u8 udma;
  48. if (dmi_check_system(attixp_cable_override_dmi_table))
  49. return ATA_CBL_PATA40_SHORT;
  50. /* Hack from drivers/ide/pci. Really we want to know how to do the
  51. raw detection not play follow the bios mode guess */
  52. pci_read_config_byte(pdev, ATIIXP_IDE_UDMA_MODE + ap->port_no, &udma);
  53. if ((udma & 0x07) >= 0x04 || (udma & 0x70) >= 0x40)
  54. return ATA_CBL_PATA80;
  55. return ATA_CBL_PATA40;
  56. }
  57. static DEFINE_SPINLOCK(atiixp_lock);
  58. /**
  59. * atiixp_prereset - perform reset handling
  60. * @link: ATA link
  61. * @deadline: deadline jiffies for the operation
  62. *
  63. * Reset sequence checking enable bits to see which ports are
  64. * active.
  65. */
  66. static int atiixp_prereset(struct ata_link *link, unsigned long deadline)
  67. {
  68. static const struct pci_bits atiixp_enable_bits[] = {
  69. { 0x48, 1, 0x01, 0x00 },
  70. { 0x48, 1, 0x08, 0x00 }
  71. };
  72. struct ata_port *ap = link->ap;
  73. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  74. if (!pci_test_config_bits(pdev, &atiixp_enable_bits[ap->port_no]))
  75. return -ENOENT;
  76. return ata_sff_prereset(link, deadline);
  77. }
  78. /**
  79. * atiixp_set_pio_timing - set initial PIO mode data
  80. * @ap: ATA interface
  81. * @adev: ATA device
  82. *
  83. * Called by both the pio and dma setup functions to set the controller
  84. * timings for PIO transfers. We must load both the mode number and
  85. * timing values into the controller.
  86. */
  87. static void atiixp_set_pio_timing(struct ata_port *ap, struct ata_device *adev, int pio)
  88. {
  89. static u8 pio_timings[5] = { 0x5D, 0x47, 0x34, 0x22, 0x20 };
  90. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  91. int dn = 2 * ap->port_no + adev->devno;
  92. int timing_shift = (16 * ap->port_no) + 8 * (adev->devno ^ 1);
  93. u32 pio_timing_data;
  94. u16 pio_mode_data;
  95. pci_read_config_word(pdev, ATIIXP_IDE_PIO_MODE, &pio_mode_data);
  96. pio_mode_data &= ~(0x7 << (4 * dn));
  97. pio_mode_data |= pio << (4 * dn);
  98. pci_write_config_word(pdev, ATIIXP_IDE_PIO_MODE, pio_mode_data);
  99. pci_read_config_dword(pdev, ATIIXP_IDE_PIO_TIMING, &pio_timing_data);
  100. pio_timing_data &= ~(0xFF << timing_shift);
  101. pio_timing_data |= (pio_timings[pio] << timing_shift);
  102. pci_write_config_dword(pdev, ATIIXP_IDE_PIO_TIMING, pio_timing_data);
  103. }
  104. /**
  105. * atiixp_set_piomode - set initial PIO mode data
  106. * @ap: ATA interface
  107. * @adev: ATA device
  108. *
  109. * Called to do the PIO mode setup. We use a shared helper for this
  110. * as the DMA setup must also adjust the PIO timing information.
  111. */
  112. static void atiixp_set_piomode(struct ata_port *ap, struct ata_device *adev)
  113. {
  114. unsigned long flags;
  115. spin_lock_irqsave(&atiixp_lock, flags);
  116. atiixp_set_pio_timing(ap, adev, adev->pio_mode - XFER_PIO_0);
  117. spin_unlock_irqrestore(&atiixp_lock, flags);
  118. }
  119. /**
  120. * atiixp_set_dmamode - set initial DMA mode data
  121. * @ap: ATA interface
  122. * @adev: ATA device
  123. *
  124. * Called to do the DMA mode setup. We use timing tables for most
  125. * modes but must tune an appropriate PIO mode to match.
  126. */
  127. static void atiixp_set_dmamode(struct ata_port *ap, struct ata_device *adev)
  128. {
  129. static u8 mwdma_timings[5] = { 0x77, 0x21, 0x20 };
  130. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  131. int dma = adev->dma_mode;
  132. int dn = 2 * ap->port_no + adev->devno;
  133. int wanted_pio;
  134. unsigned long flags;
  135. spin_lock_irqsave(&atiixp_lock, flags);
  136. if (adev->dma_mode >= XFER_UDMA_0) {
  137. u16 udma_mode_data;
  138. dma -= XFER_UDMA_0;
  139. pci_read_config_word(pdev, ATIIXP_IDE_UDMA_MODE, &udma_mode_data);
  140. udma_mode_data &= ~(0x7 << (4 * dn));
  141. udma_mode_data |= dma << (4 * dn);
  142. pci_write_config_word(pdev, ATIIXP_IDE_UDMA_MODE, udma_mode_data);
  143. } else {
  144. int timing_shift = (16 * ap->port_no) + 8 * (adev->devno ^ 1);
  145. u32 mwdma_timing_data;
  146. dma -= XFER_MW_DMA_0;
  147. pci_read_config_dword(pdev, ATIIXP_IDE_MWDMA_TIMING,
  148. &mwdma_timing_data);
  149. mwdma_timing_data &= ~(0xFF << timing_shift);
  150. mwdma_timing_data |= (mwdma_timings[dma] << timing_shift);
  151. pci_write_config_dword(pdev, ATIIXP_IDE_MWDMA_TIMING,
  152. mwdma_timing_data);
  153. }
  154. /*
  155. * We must now look at the PIO mode situation. We may need to
  156. * adjust the PIO mode to keep the timings acceptable
  157. */
  158. if (adev->dma_mode >= XFER_MW_DMA_2)
  159. wanted_pio = 4;
  160. else if (adev->dma_mode == XFER_MW_DMA_1)
  161. wanted_pio = 3;
  162. else if (adev->dma_mode == XFER_MW_DMA_0)
  163. wanted_pio = 0;
  164. else BUG();
  165. if (adev->pio_mode != wanted_pio)
  166. atiixp_set_pio_timing(ap, adev, wanted_pio);
  167. spin_unlock_irqrestore(&atiixp_lock, flags);
  168. }
  169. /**
  170. * atiixp_bmdma_start - DMA start callback
  171. * @qc: Command in progress
  172. *
  173. * When DMA begins we need to ensure that the UDMA control
  174. * register for the channel is correctly set.
  175. *
  176. * Note: The host lock held by the libata layer protects
  177. * us from two channels both trying to set DMA bits at once
  178. */
  179. static void atiixp_bmdma_start(struct ata_queued_cmd *qc)
  180. {
  181. struct ata_port *ap = qc->ap;
  182. struct ata_device *adev = qc->dev;
  183. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  184. int dn = (2 * ap->port_no) + adev->devno;
  185. u16 tmp16;
  186. pci_read_config_word(pdev, ATIIXP_IDE_UDMA_CONTROL, &tmp16);
  187. if (ata_using_udma(adev))
  188. tmp16 |= (1 << dn);
  189. else
  190. tmp16 &= ~(1 << dn);
  191. pci_write_config_word(pdev, ATIIXP_IDE_UDMA_CONTROL, tmp16);
  192. ata_bmdma_start(qc);
  193. }
  194. /**
  195. * atiixp_dma_stop - DMA stop callback
  196. * @qc: Command in progress
  197. *
  198. * DMA has completed. Clear the UDMA flag as the next operations will
  199. * be PIO ones not UDMA data transfer.
  200. *
  201. * Note: The host lock held by the libata layer protects
  202. * us from two channels both trying to set DMA bits at once
  203. */
  204. static void atiixp_bmdma_stop(struct ata_queued_cmd *qc)
  205. {
  206. struct ata_port *ap = qc->ap;
  207. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  208. int dn = (2 * ap->port_no) + qc->dev->devno;
  209. u16 tmp16;
  210. pci_read_config_word(pdev, ATIIXP_IDE_UDMA_CONTROL, &tmp16);
  211. tmp16 &= ~(1 << dn);
  212. pci_write_config_word(pdev, ATIIXP_IDE_UDMA_CONTROL, tmp16);
  213. ata_bmdma_stop(qc);
  214. }
  215. static struct scsi_host_template atiixp_sht = {
  216. ATA_BMDMA_SHT(DRV_NAME),
  217. .sg_tablesize = LIBATA_DUMB_MAX_PRD,
  218. };
  219. static struct ata_port_operations atiixp_port_ops = {
  220. .inherits = &ata_bmdma_port_ops,
  221. .qc_prep = ata_bmdma_dumb_qc_prep,
  222. .bmdma_start = atiixp_bmdma_start,
  223. .bmdma_stop = atiixp_bmdma_stop,
  224. .prereset = atiixp_prereset,
  225. .cable_detect = atiixp_cable_detect,
  226. .set_piomode = atiixp_set_piomode,
  227. .set_dmamode = atiixp_set_dmamode,
  228. };
  229. static int atiixp_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
  230. {
  231. static const struct ata_port_info info = {
  232. .flags = ATA_FLAG_SLAVE_POSS,
  233. .pio_mask = ATA_PIO4,
  234. .mwdma_mask = ATA_MWDMA12_ONLY,
  235. .udma_mask = ATA_UDMA5,
  236. .port_ops = &atiixp_port_ops
  237. };
  238. const struct ata_port_info *ppi[] = { &info, &info };
  239. /* SB600 doesn't have secondary port wired */
  240. if (pdev->device == PCI_DEVICE_ID_ATI_IXP600_IDE)
  241. ppi[1] = &ata_dummy_port_info;
  242. return ata_pci_bmdma_init_one(pdev, ppi, &atiixp_sht, NULL,
  243. ATA_HOST_PARALLEL_SCAN);
  244. }
  245. static const struct pci_device_id atiixp[] = {
  246. { PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP200_IDE), },
  247. { PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP300_IDE), },
  248. { PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP400_IDE), },
  249. { PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP600_IDE), },
  250. { PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP700_IDE), },
  251. { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_HUDSON2_IDE), },
  252. { },
  253. };
  254. static struct pci_driver atiixp_pci_driver = {
  255. .name = DRV_NAME,
  256. .id_table = atiixp,
  257. .probe = atiixp_init_one,
  258. .remove = ata_pci_remove_one,
  259. #ifdef CONFIG_PM_SLEEP
  260. .resume = ata_pci_device_resume,
  261. .suspend = ata_pci_device_suspend,
  262. #endif
  263. };
  264. module_pci_driver(atiixp_pci_driver);
  265. MODULE_AUTHOR("Alan Cox");
  266. MODULE_DESCRIPTION("low-level driver for ATI IXP200/300/400");
  267. MODULE_LICENSE("GPL");
  268. MODULE_DEVICE_TABLE(pci, atiixp);
  269. MODULE_VERSION(DRV_VERSION);