pata_arasan_cf.c 26 KB

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  1. /*
  2. * drivers/ata/pata_arasan_cf.c
  3. *
  4. * Arasan Compact Flash host controller source file
  5. *
  6. * Copyright (C) 2011 ST Microelectronics
  7. * Viresh Kumar <vireshk@kernel.org>
  8. *
  9. * This file is licensed under the terms of the GNU General Public
  10. * License version 2. This program is licensed "as is" without any
  11. * warranty of any kind, whether express or implied.
  12. */
  13. /*
  14. * The Arasan CompactFlash Device Controller IP core has three basic modes of
  15. * operation: PC card ATA using I/O mode, PC card ATA using memory mode, PC card
  16. * ATA using true IDE modes. This driver supports only True IDE mode currently.
  17. *
  18. * Arasan CF Controller shares global irq register with Arasan XD Controller.
  19. *
  20. * Tested on arch/arm/mach-spear13xx
  21. */
  22. #include <linux/ata.h>
  23. #include <linux/clk.h>
  24. #include <linux/completion.h>
  25. #include <linux/delay.h>
  26. #include <linux/dmaengine.h>
  27. #include <linux/io.h>
  28. #include <linux/irq.h>
  29. #include <linux/kernel.h>
  30. #include <linux/libata.h>
  31. #include <linux/module.h>
  32. #include <linux/of.h>
  33. #include <linux/pata_arasan_cf_data.h>
  34. #include <linux/platform_device.h>
  35. #include <linux/pm.h>
  36. #include <linux/slab.h>
  37. #include <linux/spinlock.h>
  38. #include <linux/types.h>
  39. #include <linux/workqueue.h>
  40. #define DRIVER_NAME "arasan_cf"
  41. #define TIMEOUT msecs_to_jiffies(3000)
  42. /* Registers */
  43. /* CompactFlash Interface Status */
  44. #define CFI_STS 0x000
  45. #define STS_CHG (1)
  46. #define BIN_AUDIO_OUT (1 << 1)
  47. #define CARD_DETECT1 (1 << 2)
  48. #define CARD_DETECT2 (1 << 3)
  49. #define INP_ACK (1 << 4)
  50. #define CARD_READY (1 << 5)
  51. #define IO_READY (1 << 6)
  52. #define B16_IO_PORT_SEL (1 << 7)
  53. /* IRQ */
  54. #define IRQ_STS 0x004
  55. /* Interrupt Enable */
  56. #define IRQ_EN 0x008
  57. #define CARD_DETECT_IRQ (1)
  58. #define STATUS_CHNG_IRQ (1 << 1)
  59. #define MEM_MODE_IRQ (1 << 2)
  60. #define IO_MODE_IRQ (1 << 3)
  61. #define TRUE_IDE_MODE_IRQ (1 << 8)
  62. #define PIO_XFER_ERR_IRQ (1 << 9)
  63. #define BUF_AVAIL_IRQ (1 << 10)
  64. #define XFER_DONE_IRQ (1 << 11)
  65. #define IGNORED_IRQS (STATUS_CHNG_IRQ | MEM_MODE_IRQ | IO_MODE_IRQ |\
  66. TRUE_IDE_MODE_IRQ)
  67. #define TRUE_IDE_IRQS (CARD_DETECT_IRQ | PIO_XFER_ERR_IRQ |\
  68. BUF_AVAIL_IRQ | XFER_DONE_IRQ)
  69. /* Operation Mode */
  70. #define OP_MODE 0x00C
  71. #define CARD_MODE_MASK (0x3)
  72. #define MEM_MODE (0x0)
  73. #define IO_MODE (0x1)
  74. #define TRUE_IDE_MODE (0x2)
  75. #define CARD_TYPE_MASK (1 << 2)
  76. #define CF_CARD (0)
  77. #define CF_PLUS_CARD (1 << 2)
  78. #define CARD_RESET (1 << 3)
  79. #define CFHOST_ENB (1 << 4)
  80. #define OUTPUTS_TRISTATE (1 << 5)
  81. #define ULTRA_DMA_ENB (1 << 8)
  82. #define MULTI_WORD_DMA_ENB (1 << 9)
  83. #define DRQ_BLOCK_SIZE_MASK (0x3 << 11)
  84. #define DRQ_BLOCK_SIZE_512 (0)
  85. #define DRQ_BLOCK_SIZE_1024 (1 << 11)
  86. #define DRQ_BLOCK_SIZE_2048 (2 << 11)
  87. #define DRQ_BLOCK_SIZE_4096 (3 << 11)
  88. /* CF Interface Clock Configuration */
  89. #define CLK_CFG 0x010
  90. #define CF_IF_CLK_MASK (0XF)
  91. /* CF Timing Mode Configuration */
  92. #define TM_CFG 0x014
  93. #define MEM_MODE_TIMING_MASK (0x3)
  94. #define MEM_MODE_TIMING_250NS (0x0)
  95. #define MEM_MODE_TIMING_120NS (0x1)
  96. #define MEM_MODE_TIMING_100NS (0x2)
  97. #define MEM_MODE_TIMING_80NS (0x3)
  98. #define IO_MODE_TIMING_MASK (0x3 << 2)
  99. #define IO_MODE_TIMING_250NS (0x0 << 2)
  100. #define IO_MODE_TIMING_120NS (0x1 << 2)
  101. #define IO_MODE_TIMING_100NS (0x2 << 2)
  102. #define IO_MODE_TIMING_80NS (0x3 << 2)
  103. #define TRUEIDE_PIO_TIMING_MASK (0x7 << 4)
  104. #define TRUEIDE_PIO_TIMING_SHIFT 4
  105. #define TRUEIDE_MWORD_DMA_TIMING_MASK (0x7 << 7)
  106. #define TRUEIDE_MWORD_DMA_TIMING_SHIFT 7
  107. #define ULTRA_DMA_TIMING_MASK (0x7 << 10)
  108. #define ULTRA_DMA_TIMING_SHIFT 10
  109. /* CF Transfer Address */
  110. #define XFER_ADDR 0x014
  111. #define XFER_ADDR_MASK (0x7FF)
  112. #define MAX_XFER_COUNT 0x20000u
  113. /* Transfer Control */
  114. #define XFER_CTR 0x01C
  115. #define XFER_COUNT_MASK (0x3FFFF)
  116. #define ADDR_INC_DISABLE (1 << 24)
  117. #define XFER_WIDTH_MASK (1 << 25)
  118. #define XFER_WIDTH_8B (0)
  119. #define XFER_WIDTH_16B (1 << 25)
  120. #define MEM_TYPE_MASK (1 << 26)
  121. #define MEM_TYPE_COMMON (0)
  122. #define MEM_TYPE_ATTRIBUTE (1 << 26)
  123. #define MEM_IO_XFER_MASK (1 << 27)
  124. #define MEM_XFER (0)
  125. #define IO_XFER (1 << 27)
  126. #define DMA_XFER_MODE (1 << 28)
  127. #define AHB_BUS_NORMAL_PIO_OPRTN (~(1 << 29))
  128. #define XFER_DIR_MASK (1 << 30)
  129. #define XFER_READ (0)
  130. #define XFER_WRITE (1 << 30)
  131. #define XFER_START (1 << 31)
  132. /* Write Data Port */
  133. #define WRITE_PORT 0x024
  134. /* Read Data Port */
  135. #define READ_PORT 0x028
  136. /* ATA Data Port */
  137. #define ATA_DATA_PORT 0x030
  138. #define ATA_DATA_PORT_MASK (0xFFFF)
  139. /* ATA Error/Features */
  140. #define ATA_ERR_FTR 0x034
  141. /* ATA Sector Count */
  142. #define ATA_SC 0x038
  143. /* ATA Sector Number */
  144. #define ATA_SN 0x03C
  145. /* ATA Cylinder Low */
  146. #define ATA_CL 0x040
  147. /* ATA Cylinder High */
  148. #define ATA_CH 0x044
  149. /* ATA Select Card/Head */
  150. #define ATA_SH 0x048
  151. /* ATA Status-Command */
  152. #define ATA_STS_CMD 0x04C
  153. /* ATA Alternate Status/Device Control */
  154. #define ATA_ASTS_DCTR 0x050
  155. /* Extended Write Data Port 0x200-0x3FC */
  156. #define EXT_WRITE_PORT 0x200
  157. /* Extended Read Data Port 0x400-0x5FC */
  158. #define EXT_READ_PORT 0x400
  159. #define FIFO_SIZE 0x200u
  160. /* Global Interrupt Status */
  161. #define GIRQ_STS 0x800
  162. /* Global Interrupt Status enable */
  163. #define GIRQ_STS_EN 0x804
  164. /* Global Interrupt Signal enable */
  165. #define GIRQ_SGN_EN 0x808
  166. #define GIRQ_CF (1)
  167. #define GIRQ_XD (1 << 1)
  168. /* Compact Flash Controller Dev Structure */
  169. struct arasan_cf_dev {
  170. /* pointer to ata_host structure */
  171. struct ata_host *host;
  172. /* clk structure */
  173. struct clk *clk;
  174. /* physical base address of controller */
  175. dma_addr_t pbase;
  176. /* virtual base address of controller */
  177. void __iomem *vbase;
  178. /* irq number*/
  179. int irq;
  180. /* status to be updated to framework regarding DMA transfer */
  181. u8 dma_status;
  182. /* Card is present or Not */
  183. u8 card_present;
  184. /* dma specific */
  185. /* Completion for transfer complete interrupt from controller */
  186. struct completion cf_completion;
  187. /* Completion for DMA transfer complete. */
  188. struct completion dma_completion;
  189. /* Dma channel allocated */
  190. struct dma_chan *dma_chan;
  191. /* Mask for DMA transfers */
  192. dma_cap_mask_t mask;
  193. /* DMA transfer work */
  194. struct work_struct work;
  195. /* DMA delayed finish work */
  196. struct delayed_work dwork;
  197. /* qc to be transferred using DMA */
  198. struct ata_queued_cmd *qc;
  199. };
  200. static struct scsi_host_template arasan_cf_sht = {
  201. ATA_BASE_SHT(DRIVER_NAME),
  202. .dma_boundary = 0xFFFFFFFFUL,
  203. };
  204. static void cf_dumpregs(struct arasan_cf_dev *acdev)
  205. {
  206. struct device *dev = acdev->host->dev;
  207. dev_dbg(dev, ": =========== REGISTER DUMP ===========");
  208. dev_dbg(dev, ": CFI_STS: %x", readl(acdev->vbase + CFI_STS));
  209. dev_dbg(dev, ": IRQ_STS: %x", readl(acdev->vbase + IRQ_STS));
  210. dev_dbg(dev, ": IRQ_EN: %x", readl(acdev->vbase + IRQ_EN));
  211. dev_dbg(dev, ": OP_MODE: %x", readl(acdev->vbase + OP_MODE));
  212. dev_dbg(dev, ": CLK_CFG: %x", readl(acdev->vbase + CLK_CFG));
  213. dev_dbg(dev, ": TM_CFG: %x", readl(acdev->vbase + TM_CFG));
  214. dev_dbg(dev, ": XFER_CTR: %x", readl(acdev->vbase + XFER_CTR));
  215. dev_dbg(dev, ": GIRQ_STS: %x", readl(acdev->vbase + GIRQ_STS));
  216. dev_dbg(dev, ": GIRQ_STS_EN: %x", readl(acdev->vbase + GIRQ_STS_EN));
  217. dev_dbg(dev, ": GIRQ_SGN_EN: %x", readl(acdev->vbase + GIRQ_SGN_EN));
  218. dev_dbg(dev, ": =====================================");
  219. }
  220. /* Enable/Disable global interrupts shared between CF and XD ctrlr. */
  221. static void cf_ginterrupt_enable(struct arasan_cf_dev *acdev, bool enable)
  222. {
  223. /* enable should be 0 or 1 */
  224. writel(enable, acdev->vbase + GIRQ_STS_EN);
  225. writel(enable, acdev->vbase + GIRQ_SGN_EN);
  226. }
  227. /* Enable/Disable CF interrupts */
  228. static inline void
  229. cf_interrupt_enable(struct arasan_cf_dev *acdev, u32 mask, bool enable)
  230. {
  231. u32 val = readl(acdev->vbase + IRQ_EN);
  232. /* clear & enable/disable irqs */
  233. if (enable) {
  234. writel(mask, acdev->vbase + IRQ_STS);
  235. writel(val | mask, acdev->vbase + IRQ_EN);
  236. } else
  237. writel(val & ~mask, acdev->vbase + IRQ_EN);
  238. }
  239. static inline void cf_card_reset(struct arasan_cf_dev *acdev)
  240. {
  241. u32 val = readl(acdev->vbase + OP_MODE);
  242. writel(val | CARD_RESET, acdev->vbase + OP_MODE);
  243. udelay(200);
  244. writel(val & ~CARD_RESET, acdev->vbase + OP_MODE);
  245. }
  246. static inline void cf_ctrl_reset(struct arasan_cf_dev *acdev)
  247. {
  248. writel(readl(acdev->vbase + OP_MODE) & ~CFHOST_ENB,
  249. acdev->vbase + OP_MODE);
  250. writel(readl(acdev->vbase + OP_MODE) | CFHOST_ENB,
  251. acdev->vbase + OP_MODE);
  252. }
  253. static void cf_card_detect(struct arasan_cf_dev *acdev, bool hotplugged)
  254. {
  255. struct ata_port *ap = acdev->host->ports[0];
  256. struct ata_eh_info *ehi = &ap->link.eh_info;
  257. u32 val = readl(acdev->vbase + CFI_STS);
  258. /* Both CD1 & CD2 should be low if card inserted completely */
  259. if (!(val & (CARD_DETECT1 | CARD_DETECT2))) {
  260. if (acdev->card_present)
  261. return;
  262. acdev->card_present = 1;
  263. cf_card_reset(acdev);
  264. } else {
  265. if (!acdev->card_present)
  266. return;
  267. acdev->card_present = 0;
  268. }
  269. if (hotplugged) {
  270. ata_ehi_hotplugged(ehi);
  271. ata_port_freeze(ap);
  272. }
  273. }
  274. static int cf_init(struct arasan_cf_dev *acdev)
  275. {
  276. struct arasan_cf_pdata *pdata = dev_get_platdata(acdev->host->dev);
  277. unsigned int if_clk;
  278. unsigned long flags;
  279. int ret = 0;
  280. ret = clk_prepare_enable(acdev->clk);
  281. if (ret) {
  282. dev_dbg(acdev->host->dev, "clock enable failed");
  283. return ret;
  284. }
  285. ret = clk_set_rate(acdev->clk, 166000000);
  286. if (ret) {
  287. dev_warn(acdev->host->dev, "clock set rate failed");
  288. clk_disable_unprepare(acdev->clk);
  289. return ret;
  290. }
  291. spin_lock_irqsave(&acdev->host->lock, flags);
  292. /* configure CF interface clock */
  293. /* TODO: read from device tree */
  294. if_clk = CF_IF_CLK_166M;
  295. if (pdata && pdata->cf_if_clk <= CF_IF_CLK_200M)
  296. if_clk = pdata->cf_if_clk;
  297. writel(if_clk, acdev->vbase + CLK_CFG);
  298. writel(TRUE_IDE_MODE | CFHOST_ENB, acdev->vbase + OP_MODE);
  299. cf_interrupt_enable(acdev, CARD_DETECT_IRQ, 1);
  300. cf_ginterrupt_enable(acdev, 1);
  301. spin_unlock_irqrestore(&acdev->host->lock, flags);
  302. return ret;
  303. }
  304. static void cf_exit(struct arasan_cf_dev *acdev)
  305. {
  306. unsigned long flags;
  307. spin_lock_irqsave(&acdev->host->lock, flags);
  308. cf_ginterrupt_enable(acdev, 0);
  309. cf_interrupt_enable(acdev, TRUE_IDE_IRQS, 0);
  310. cf_card_reset(acdev);
  311. writel(readl(acdev->vbase + OP_MODE) & ~CFHOST_ENB,
  312. acdev->vbase + OP_MODE);
  313. spin_unlock_irqrestore(&acdev->host->lock, flags);
  314. clk_disable_unprepare(acdev->clk);
  315. }
  316. static void dma_callback(void *dev)
  317. {
  318. struct arasan_cf_dev *acdev = dev;
  319. complete(&acdev->dma_completion);
  320. }
  321. static inline void dma_complete(struct arasan_cf_dev *acdev)
  322. {
  323. struct ata_queued_cmd *qc = acdev->qc;
  324. unsigned long flags;
  325. acdev->qc = NULL;
  326. ata_sff_interrupt(acdev->irq, acdev->host);
  327. spin_lock_irqsave(&acdev->host->lock, flags);
  328. if (unlikely(qc->err_mask) && ata_is_dma(qc->tf.protocol))
  329. ata_ehi_push_desc(&qc->ap->link.eh_info, "DMA Failed: Timeout");
  330. spin_unlock_irqrestore(&acdev->host->lock, flags);
  331. }
  332. static inline int wait4buf(struct arasan_cf_dev *acdev)
  333. {
  334. if (!wait_for_completion_timeout(&acdev->cf_completion, TIMEOUT)) {
  335. u32 rw = acdev->qc->tf.flags & ATA_TFLAG_WRITE;
  336. dev_err(acdev->host->dev, "%s TimeOut", rw ? "write" : "read");
  337. return -ETIMEDOUT;
  338. }
  339. /* Check if PIO Error interrupt has occurred */
  340. if (acdev->dma_status & ATA_DMA_ERR)
  341. return -EAGAIN;
  342. return 0;
  343. }
  344. static int
  345. dma_xfer(struct arasan_cf_dev *acdev, dma_addr_t src, dma_addr_t dest, u32 len)
  346. {
  347. struct dma_async_tx_descriptor *tx;
  348. struct dma_chan *chan = acdev->dma_chan;
  349. dma_cookie_t cookie;
  350. unsigned long flags = DMA_PREP_INTERRUPT;
  351. int ret = 0;
  352. tx = chan->device->device_prep_dma_memcpy(chan, dest, src, len, flags);
  353. if (!tx) {
  354. dev_err(acdev->host->dev, "device_prep_dma_memcpy failed\n");
  355. return -EAGAIN;
  356. }
  357. tx->callback = dma_callback;
  358. tx->callback_param = acdev;
  359. cookie = tx->tx_submit(tx);
  360. ret = dma_submit_error(cookie);
  361. if (ret) {
  362. dev_err(acdev->host->dev, "dma_submit_error\n");
  363. return ret;
  364. }
  365. chan->device->device_issue_pending(chan);
  366. /* Wait for DMA to complete */
  367. if (!wait_for_completion_timeout(&acdev->dma_completion, TIMEOUT)) {
  368. dmaengine_terminate_all(chan);
  369. dev_err(acdev->host->dev, "wait_for_completion_timeout\n");
  370. return -ETIMEDOUT;
  371. }
  372. return ret;
  373. }
  374. static int sg_xfer(struct arasan_cf_dev *acdev, struct scatterlist *sg)
  375. {
  376. dma_addr_t dest = 0, src = 0;
  377. u32 xfer_cnt, sglen, dma_len, xfer_ctr;
  378. u32 write = acdev->qc->tf.flags & ATA_TFLAG_WRITE;
  379. unsigned long flags;
  380. int ret = 0;
  381. sglen = sg_dma_len(sg);
  382. if (write) {
  383. src = sg_dma_address(sg);
  384. dest = acdev->pbase + EXT_WRITE_PORT;
  385. } else {
  386. dest = sg_dma_address(sg);
  387. src = acdev->pbase + EXT_READ_PORT;
  388. }
  389. /*
  390. * For each sg:
  391. * MAX_XFER_COUNT data will be transferred before we get transfer
  392. * complete interrupt. Between after FIFO_SIZE data
  393. * buffer available interrupt will be generated. At this time we will
  394. * fill FIFO again: max FIFO_SIZE data.
  395. */
  396. while (sglen) {
  397. xfer_cnt = min(sglen, MAX_XFER_COUNT);
  398. spin_lock_irqsave(&acdev->host->lock, flags);
  399. xfer_ctr = readl(acdev->vbase + XFER_CTR) &
  400. ~XFER_COUNT_MASK;
  401. writel(xfer_ctr | xfer_cnt | XFER_START,
  402. acdev->vbase + XFER_CTR);
  403. spin_unlock_irqrestore(&acdev->host->lock, flags);
  404. /* continue dma xfers until current sg is completed */
  405. while (xfer_cnt) {
  406. /* wait for read to complete */
  407. if (!write) {
  408. ret = wait4buf(acdev);
  409. if (ret)
  410. goto fail;
  411. }
  412. /* read/write FIFO in chunk of FIFO_SIZE */
  413. dma_len = min(xfer_cnt, FIFO_SIZE);
  414. ret = dma_xfer(acdev, src, dest, dma_len);
  415. if (ret) {
  416. dev_err(acdev->host->dev, "dma failed");
  417. goto fail;
  418. }
  419. if (write)
  420. src += dma_len;
  421. else
  422. dest += dma_len;
  423. sglen -= dma_len;
  424. xfer_cnt -= dma_len;
  425. /* wait for write to complete */
  426. if (write) {
  427. ret = wait4buf(acdev);
  428. if (ret)
  429. goto fail;
  430. }
  431. }
  432. }
  433. fail:
  434. spin_lock_irqsave(&acdev->host->lock, flags);
  435. writel(readl(acdev->vbase + XFER_CTR) & ~XFER_START,
  436. acdev->vbase + XFER_CTR);
  437. spin_unlock_irqrestore(&acdev->host->lock, flags);
  438. return ret;
  439. }
  440. /*
  441. * This routine uses External DMA controller to read/write data to FIFO of CF
  442. * controller. There are two xfer related interrupt supported by CF controller:
  443. * - buf_avail: This interrupt is generated as soon as we have buffer of 512
  444. * bytes available for reading or empty buffer available for writing.
  445. * - xfer_done: This interrupt is generated on transfer of "xfer_size" amount of
  446. * data to/from FIFO. xfer_size is programmed in XFER_CTR register.
  447. *
  448. * Max buffer size = FIFO_SIZE = 512 Bytes.
  449. * Max xfer_size = MAX_XFER_COUNT = 256 KB.
  450. */
  451. static void data_xfer(struct work_struct *work)
  452. {
  453. struct arasan_cf_dev *acdev = container_of(work, struct arasan_cf_dev,
  454. work);
  455. struct ata_queued_cmd *qc = acdev->qc;
  456. struct scatterlist *sg;
  457. unsigned long flags;
  458. u32 temp;
  459. int ret = 0;
  460. /* request dma channels */
  461. /* dma_request_channel may sleep, so calling from process context */
  462. acdev->dma_chan = dma_request_chan(acdev->host->dev, "data");
  463. if (IS_ERR(acdev->dma_chan)) {
  464. dev_err(acdev->host->dev, "Unable to get dma_chan\n");
  465. acdev->dma_chan = NULL;
  466. goto chan_request_fail;
  467. }
  468. for_each_sg(qc->sg, sg, qc->n_elem, temp) {
  469. ret = sg_xfer(acdev, sg);
  470. if (ret)
  471. break;
  472. }
  473. dma_release_channel(acdev->dma_chan);
  474. acdev->dma_chan = NULL;
  475. /* data xferred successfully */
  476. if (!ret) {
  477. u32 status;
  478. spin_lock_irqsave(&acdev->host->lock, flags);
  479. status = ioread8(qc->ap->ioaddr.altstatus_addr);
  480. spin_unlock_irqrestore(&acdev->host->lock, flags);
  481. if (status & (ATA_BUSY | ATA_DRQ)) {
  482. ata_sff_queue_delayed_work(&acdev->dwork, 1);
  483. return;
  484. }
  485. goto sff_intr;
  486. }
  487. cf_dumpregs(acdev);
  488. chan_request_fail:
  489. spin_lock_irqsave(&acdev->host->lock, flags);
  490. /* error when transferring data to/from memory */
  491. qc->err_mask |= AC_ERR_HOST_BUS;
  492. qc->ap->hsm_task_state = HSM_ST_ERR;
  493. cf_ctrl_reset(acdev);
  494. spin_unlock_irqrestore(&acdev->host->lock, flags);
  495. sff_intr:
  496. dma_complete(acdev);
  497. }
  498. static void delayed_finish(struct work_struct *work)
  499. {
  500. struct arasan_cf_dev *acdev = container_of(work, struct arasan_cf_dev,
  501. dwork.work);
  502. struct ata_queued_cmd *qc = acdev->qc;
  503. unsigned long flags;
  504. u8 status;
  505. spin_lock_irqsave(&acdev->host->lock, flags);
  506. status = ioread8(qc->ap->ioaddr.altstatus_addr);
  507. spin_unlock_irqrestore(&acdev->host->lock, flags);
  508. if (status & (ATA_BUSY | ATA_DRQ))
  509. ata_sff_queue_delayed_work(&acdev->dwork, 1);
  510. else
  511. dma_complete(acdev);
  512. }
  513. static irqreturn_t arasan_cf_interrupt(int irq, void *dev)
  514. {
  515. struct arasan_cf_dev *acdev = ((struct ata_host *)dev)->private_data;
  516. unsigned long flags;
  517. u32 irqsts;
  518. irqsts = readl(acdev->vbase + GIRQ_STS);
  519. if (!(irqsts & GIRQ_CF))
  520. return IRQ_NONE;
  521. spin_lock_irqsave(&acdev->host->lock, flags);
  522. irqsts = readl(acdev->vbase + IRQ_STS);
  523. writel(irqsts, acdev->vbase + IRQ_STS); /* clear irqs */
  524. writel(GIRQ_CF, acdev->vbase + GIRQ_STS); /* clear girqs */
  525. /* handle only relevant interrupts */
  526. irqsts &= ~IGNORED_IRQS;
  527. if (irqsts & CARD_DETECT_IRQ) {
  528. cf_card_detect(acdev, 1);
  529. spin_unlock_irqrestore(&acdev->host->lock, flags);
  530. return IRQ_HANDLED;
  531. }
  532. if (irqsts & PIO_XFER_ERR_IRQ) {
  533. acdev->dma_status = ATA_DMA_ERR;
  534. writel(readl(acdev->vbase + XFER_CTR) & ~XFER_START,
  535. acdev->vbase + XFER_CTR);
  536. spin_unlock_irqrestore(&acdev->host->lock, flags);
  537. complete(&acdev->cf_completion);
  538. dev_err(acdev->host->dev, "pio xfer err irq\n");
  539. return IRQ_HANDLED;
  540. }
  541. spin_unlock_irqrestore(&acdev->host->lock, flags);
  542. if (irqsts & BUF_AVAIL_IRQ) {
  543. complete(&acdev->cf_completion);
  544. return IRQ_HANDLED;
  545. }
  546. if (irqsts & XFER_DONE_IRQ) {
  547. struct ata_queued_cmd *qc = acdev->qc;
  548. /* Send Complete only for write */
  549. if (qc->tf.flags & ATA_TFLAG_WRITE)
  550. complete(&acdev->cf_completion);
  551. }
  552. return IRQ_HANDLED;
  553. }
  554. static void arasan_cf_freeze(struct ata_port *ap)
  555. {
  556. struct arasan_cf_dev *acdev = ap->host->private_data;
  557. /* stop transfer and reset controller */
  558. writel(readl(acdev->vbase + XFER_CTR) & ~XFER_START,
  559. acdev->vbase + XFER_CTR);
  560. cf_ctrl_reset(acdev);
  561. acdev->dma_status = ATA_DMA_ERR;
  562. ata_sff_dma_pause(ap);
  563. ata_sff_freeze(ap);
  564. }
  565. static void arasan_cf_error_handler(struct ata_port *ap)
  566. {
  567. struct arasan_cf_dev *acdev = ap->host->private_data;
  568. /*
  569. * DMA transfers using an external DMA controller may be scheduled.
  570. * Abort them before handling error. Refer data_xfer() for further
  571. * details.
  572. */
  573. cancel_work_sync(&acdev->work);
  574. cancel_delayed_work_sync(&acdev->dwork);
  575. return ata_sff_error_handler(ap);
  576. }
  577. static void arasan_cf_dma_start(struct arasan_cf_dev *acdev)
  578. {
  579. struct ata_queued_cmd *qc = acdev->qc;
  580. struct ata_port *ap = qc->ap;
  581. struct ata_taskfile *tf = &qc->tf;
  582. u32 xfer_ctr = readl(acdev->vbase + XFER_CTR) & ~XFER_DIR_MASK;
  583. u32 write = tf->flags & ATA_TFLAG_WRITE;
  584. xfer_ctr |= write ? XFER_WRITE : XFER_READ;
  585. writel(xfer_ctr, acdev->vbase + XFER_CTR);
  586. ap->ops->sff_exec_command(ap, tf);
  587. ata_sff_queue_work(&acdev->work);
  588. }
  589. static unsigned int arasan_cf_qc_issue(struct ata_queued_cmd *qc)
  590. {
  591. struct ata_port *ap = qc->ap;
  592. struct arasan_cf_dev *acdev = ap->host->private_data;
  593. /* defer PIO handling to sff_qc_issue */
  594. if (!ata_is_dma(qc->tf.protocol))
  595. return ata_sff_qc_issue(qc);
  596. /* select the device */
  597. ata_wait_idle(ap);
  598. ata_sff_dev_select(ap, qc->dev->devno);
  599. ata_wait_idle(ap);
  600. /* start the command */
  601. switch (qc->tf.protocol) {
  602. case ATA_PROT_DMA:
  603. WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING);
  604. ap->ops->sff_tf_load(ap, &qc->tf);
  605. acdev->dma_status = 0;
  606. acdev->qc = qc;
  607. arasan_cf_dma_start(acdev);
  608. ap->hsm_task_state = HSM_ST_LAST;
  609. break;
  610. default:
  611. WARN_ON(1);
  612. return AC_ERR_SYSTEM;
  613. }
  614. return 0;
  615. }
  616. static void arasan_cf_set_piomode(struct ata_port *ap, struct ata_device *adev)
  617. {
  618. struct arasan_cf_dev *acdev = ap->host->private_data;
  619. u8 pio = adev->pio_mode - XFER_PIO_0;
  620. unsigned long flags;
  621. u32 val;
  622. /* Arasan ctrl supports Mode0 -> Mode6 */
  623. if (pio > 6) {
  624. dev_err(ap->dev, "Unknown PIO mode\n");
  625. return;
  626. }
  627. spin_lock_irqsave(&acdev->host->lock, flags);
  628. val = readl(acdev->vbase + OP_MODE) &
  629. ~(ULTRA_DMA_ENB | MULTI_WORD_DMA_ENB | DRQ_BLOCK_SIZE_MASK);
  630. writel(val, acdev->vbase + OP_MODE);
  631. val = readl(acdev->vbase + TM_CFG) & ~TRUEIDE_PIO_TIMING_MASK;
  632. val |= pio << TRUEIDE_PIO_TIMING_SHIFT;
  633. writel(val, acdev->vbase + TM_CFG);
  634. cf_interrupt_enable(acdev, BUF_AVAIL_IRQ | XFER_DONE_IRQ, 0);
  635. cf_interrupt_enable(acdev, PIO_XFER_ERR_IRQ, 1);
  636. spin_unlock_irqrestore(&acdev->host->lock, flags);
  637. }
  638. static void arasan_cf_set_dmamode(struct ata_port *ap, struct ata_device *adev)
  639. {
  640. struct arasan_cf_dev *acdev = ap->host->private_data;
  641. u32 opmode, tmcfg, dma_mode = adev->dma_mode;
  642. unsigned long flags;
  643. spin_lock_irqsave(&acdev->host->lock, flags);
  644. opmode = readl(acdev->vbase + OP_MODE) &
  645. ~(MULTI_WORD_DMA_ENB | ULTRA_DMA_ENB);
  646. tmcfg = readl(acdev->vbase + TM_CFG);
  647. if ((dma_mode >= XFER_UDMA_0) && (dma_mode <= XFER_UDMA_6)) {
  648. opmode |= ULTRA_DMA_ENB;
  649. tmcfg &= ~ULTRA_DMA_TIMING_MASK;
  650. tmcfg |= (dma_mode - XFER_UDMA_0) << ULTRA_DMA_TIMING_SHIFT;
  651. } else if ((dma_mode >= XFER_MW_DMA_0) && (dma_mode <= XFER_MW_DMA_4)) {
  652. opmode |= MULTI_WORD_DMA_ENB;
  653. tmcfg &= ~TRUEIDE_MWORD_DMA_TIMING_MASK;
  654. tmcfg |= (dma_mode - XFER_MW_DMA_0) <<
  655. TRUEIDE_MWORD_DMA_TIMING_SHIFT;
  656. } else {
  657. dev_err(ap->dev, "Unknown DMA mode\n");
  658. spin_unlock_irqrestore(&acdev->host->lock, flags);
  659. return;
  660. }
  661. writel(opmode, acdev->vbase + OP_MODE);
  662. writel(tmcfg, acdev->vbase + TM_CFG);
  663. writel(DMA_XFER_MODE, acdev->vbase + XFER_CTR);
  664. cf_interrupt_enable(acdev, PIO_XFER_ERR_IRQ, 0);
  665. cf_interrupt_enable(acdev, BUF_AVAIL_IRQ | XFER_DONE_IRQ, 1);
  666. spin_unlock_irqrestore(&acdev->host->lock, flags);
  667. }
  668. static struct ata_port_operations arasan_cf_ops = {
  669. .inherits = &ata_sff_port_ops,
  670. .freeze = arasan_cf_freeze,
  671. .error_handler = arasan_cf_error_handler,
  672. .qc_issue = arasan_cf_qc_issue,
  673. .set_piomode = arasan_cf_set_piomode,
  674. .set_dmamode = arasan_cf_set_dmamode,
  675. };
  676. static int arasan_cf_probe(struct platform_device *pdev)
  677. {
  678. struct arasan_cf_dev *acdev;
  679. struct arasan_cf_pdata *pdata = dev_get_platdata(&pdev->dev);
  680. struct ata_host *host;
  681. struct ata_port *ap;
  682. struct resource *res;
  683. u32 quirk;
  684. irq_handler_t irq_handler = NULL;
  685. int ret;
  686. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  687. if (!res)
  688. return -EINVAL;
  689. if (!devm_request_mem_region(&pdev->dev, res->start, resource_size(res),
  690. DRIVER_NAME)) {
  691. dev_warn(&pdev->dev, "Failed to get memory region resource\n");
  692. return -ENOENT;
  693. }
  694. acdev = devm_kzalloc(&pdev->dev, sizeof(*acdev), GFP_KERNEL);
  695. if (!acdev)
  696. return -ENOMEM;
  697. if (pdata)
  698. quirk = pdata->quirk;
  699. else
  700. quirk = CF_BROKEN_UDMA; /* as it is on spear1340 */
  701. /*
  702. * If there's an error getting IRQ (or we do get IRQ0),
  703. * support only PIO
  704. */
  705. ret = platform_get_irq(pdev, 0);
  706. if (ret > 0) {
  707. acdev->irq = ret;
  708. irq_handler = arasan_cf_interrupt;
  709. } else if (ret == -EPROBE_DEFER) {
  710. return ret;
  711. } else {
  712. quirk |= CF_BROKEN_MWDMA | CF_BROKEN_UDMA;
  713. }
  714. acdev->pbase = res->start;
  715. acdev->vbase = devm_ioremap(&pdev->dev, res->start,
  716. resource_size(res));
  717. if (!acdev->vbase) {
  718. dev_warn(&pdev->dev, "ioremap fail\n");
  719. return -ENOMEM;
  720. }
  721. acdev->clk = devm_clk_get(&pdev->dev, NULL);
  722. if (IS_ERR(acdev->clk)) {
  723. dev_warn(&pdev->dev, "Clock not found\n");
  724. return PTR_ERR(acdev->clk);
  725. }
  726. /* allocate host */
  727. host = ata_host_alloc(&pdev->dev, 1);
  728. if (!host) {
  729. dev_warn(&pdev->dev, "alloc host fail\n");
  730. return -ENOMEM;
  731. }
  732. ap = host->ports[0];
  733. host->private_data = acdev;
  734. acdev->host = host;
  735. ap->ops = &arasan_cf_ops;
  736. ap->pio_mask = ATA_PIO6;
  737. ap->mwdma_mask = ATA_MWDMA4;
  738. ap->udma_mask = ATA_UDMA6;
  739. init_completion(&acdev->cf_completion);
  740. init_completion(&acdev->dma_completion);
  741. INIT_WORK(&acdev->work, data_xfer);
  742. INIT_DELAYED_WORK(&acdev->dwork, delayed_finish);
  743. dma_cap_set(DMA_MEMCPY, acdev->mask);
  744. /* Handle platform specific quirks */
  745. if (quirk) {
  746. if (quirk & CF_BROKEN_PIO) {
  747. ap->ops->set_piomode = NULL;
  748. ap->pio_mask = 0;
  749. }
  750. if (quirk & CF_BROKEN_MWDMA)
  751. ap->mwdma_mask = 0;
  752. if (quirk & CF_BROKEN_UDMA)
  753. ap->udma_mask = 0;
  754. }
  755. ap->flags |= ATA_FLAG_PIO_POLLING | ATA_FLAG_NO_ATAPI;
  756. ap->ioaddr.cmd_addr = acdev->vbase + ATA_DATA_PORT;
  757. ap->ioaddr.data_addr = acdev->vbase + ATA_DATA_PORT;
  758. ap->ioaddr.error_addr = acdev->vbase + ATA_ERR_FTR;
  759. ap->ioaddr.feature_addr = acdev->vbase + ATA_ERR_FTR;
  760. ap->ioaddr.nsect_addr = acdev->vbase + ATA_SC;
  761. ap->ioaddr.lbal_addr = acdev->vbase + ATA_SN;
  762. ap->ioaddr.lbam_addr = acdev->vbase + ATA_CL;
  763. ap->ioaddr.lbah_addr = acdev->vbase + ATA_CH;
  764. ap->ioaddr.device_addr = acdev->vbase + ATA_SH;
  765. ap->ioaddr.status_addr = acdev->vbase + ATA_STS_CMD;
  766. ap->ioaddr.command_addr = acdev->vbase + ATA_STS_CMD;
  767. ap->ioaddr.altstatus_addr = acdev->vbase + ATA_ASTS_DCTR;
  768. ap->ioaddr.ctl_addr = acdev->vbase + ATA_ASTS_DCTR;
  769. ata_port_desc(ap, "phy_addr %llx virt_addr %p",
  770. (unsigned long long) res->start, acdev->vbase);
  771. ret = cf_init(acdev);
  772. if (ret)
  773. return ret;
  774. cf_card_detect(acdev, 0);
  775. ret = ata_host_activate(host, acdev->irq, irq_handler, 0,
  776. &arasan_cf_sht);
  777. if (!ret)
  778. return 0;
  779. cf_exit(acdev);
  780. return ret;
  781. }
  782. static int arasan_cf_remove(struct platform_device *pdev)
  783. {
  784. struct ata_host *host = platform_get_drvdata(pdev);
  785. struct arasan_cf_dev *acdev = host->ports[0]->private_data;
  786. ata_host_detach(host);
  787. cf_exit(acdev);
  788. return 0;
  789. }
  790. #ifdef CONFIG_PM_SLEEP
  791. static int arasan_cf_suspend(struct device *dev)
  792. {
  793. struct ata_host *host = dev_get_drvdata(dev);
  794. struct arasan_cf_dev *acdev = host->ports[0]->private_data;
  795. if (acdev->dma_chan)
  796. dmaengine_terminate_all(acdev->dma_chan);
  797. cf_exit(acdev);
  798. return ata_host_suspend(host, PMSG_SUSPEND);
  799. }
  800. static int arasan_cf_resume(struct device *dev)
  801. {
  802. struct ata_host *host = dev_get_drvdata(dev);
  803. struct arasan_cf_dev *acdev = host->ports[0]->private_data;
  804. cf_init(acdev);
  805. ata_host_resume(host);
  806. return 0;
  807. }
  808. #endif
  809. static SIMPLE_DEV_PM_OPS(arasan_cf_pm_ops, arasan_cf_suspend, arasan_cf_resume);
  810. #ifdef CONFIG_OF
  811. static const struct of_device_id arasan_cf_id_table[] = {
  812. { .compatible = "arasan,cf-spear1340" },
  813. {}
  814. };
  815. MODULE_DEVICE_TABLE(of, arasan_cf_id_table);
  816. #endif
  817. static struct platform_driver arasan_cf_driver = {
  818. .probe = arasan_cf_probe,
  819. .remove = arasan_cf_remove,
  820. .driver = {
  821. .name = DRIVER_NAME,
  822. .pm = &arasan_cf_pm_ops,
  823. .of_match_table = of_match_ptr(arasan_cf_id_table),
  824. },
  825. };
  826. module_platform_driver(arasan_cf_driver);
  827. MODULE_AUTHOR("Viresh Kumar <vireshk@kernel.org>");
  828. MODULE_DESCRIPTION("Arasan ATA Compact Flash driver");
  829. MODULE_LICENSE("GPL");
  830. MODULE_ALIAS("platform:" DRIVER_NAME);