libata-sff.c 83 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * libata-sff.c - helper library for PCI IDE BMDMA
  4. *
  5. * Copyright 2003-2006 Red Hat, Inc. All rights reserved.
  6. * Copyright 2003-2006 Jeff Garzik
  7. *
  8. * libata documentation is available via 'make {ps|pdf}docs',
  9. * as Documentation/driver-api/libata.rst
  10. *
  11. * Hardware documentation available from http://www.t13.org/ and
  12. * http://www.sata-io.org/
  13. */
  14. #include <linux/kernel.h>
  15. #include <linux/gfp.h>
  16. #include <linux/pci.h>
  17. #include <linux/module.h>
  18. #include <linux/libata.h>
  19. #include <linux/highmem.h>
  20. #include "libata.h"
  21. static struct workqueue_struct *ata_sff_wq;
  22. const struct ata_port_operations ata_sff_port_ops = {
  23. .inherits = &ata_base_port_ops,
  24. .qc_prep = ata_noop_qc_prep,
  25. .qc_issue = ata_sff_qc_issue,
  26. .qc_fill_rtf = ata_sff_qc_fill_rtf,
  27. .freeze = ata_sff_freeze,
  28. .thaw = ata_sff_thaw,
  29. .prereset = ata_sff_prereset,
  30. .softreset = ata_sff_softreset,
  31. .hardreset = sata_sff_hardreset,
  32. .postreset = ata_sff_postreset,
  33. .error_handler = ata_sff_error_handler,
  34. .sff_dev_select = ata_sff_dev_select,
  35. .sff_check_status = ata_sff_check_status,
  36. .sff_tf_load = ata_sff_tf_load,
  37. .sff_tf_read = ata_sff_tf_read,
  38. .sff_exec_command = ata_sff_exec_command,
  39. .sff_data_xfer = ata_sff_data_xfer,
  40. .sff_drain_fifo = ata_sff_drain_fifo,
  41. .lost_interrupt = ata_sff_lost_interrupt,
  42. };
  43. EXPORT_SYMBOL_GPL(ata_sff_port_ops);
  44. /**
  45. * ata_sff_check_status - Read device status reg & clear interrupt
  46. * @ap: port where the device is
  47. *
  48. * Reads ATA taskfile status register for currently-selected device
  49. * and return its value. This also clears pending interrupts
  50. * from this device
  51. *
  52. * LOCKING:
  53. * Inherited from caller.
  54. */
  55. u8 ata_sff_check_status(struct ata_port *ap)
  56. {
  57. return ioread8(ap->ioaddr.status_addr);
  58. }
  59. EXPORT_SYMBOL_GPL(ata_sff_check_status);
  60. /**
  61. * ata_sff_altstatus - Read device alternate status reg
  62. * @ap: port where the device is
  63. *
  64. * Reads ATA taskfile alternate status register for
  65. * currently-selected device and return its value.
  66. *
  67. * Note: may NOT be used as the check_altstatus() entry in
  68. * ata_port_operations.
  69. *
  70. * LOCKING:
  71. * Inherited from caller.
  72. */
  73. static u8 ata_sff_altstatus(struct ata_port *ap)
  74. {
  75. if (ap->ops->sff_check_altstatus)
  76. return ap->ops->sff_check_altstatus(ap);
  77. return ioread8(ap->ioaddr.altstatus_addr);
  78. }
  79. /**
  80. * ata_sff_irq_status - Check if the device is busy
  81. * @ap: port where the device is
  82. *
  83. * Determine if the port is currently busy. Uses altstatus
  84. * if available in order to avoid clearing shared IRQ status
  85. * when finding an IRQ source. Non ctl capable devices don't
  86. * share interrupt lines fortunately for us.
  87. *
  88. * LOCKING:
  89. * Inherited from caller.
  90. */
  91. static u8 ata_sff_irq_status(struct ata_port *ap)
  92. {
  93. u8 status;
  94. if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) {
  95. status = ata_sff_altstatus(ap);
  96. /* Not us: We are busy */
  97. if (status & ATA_BUSY)
  98. return status;
  99. }
  100. /* Clear INTRQ latch */
  101. status = ap->ops->sff_check_status(ap);
  102. return status;
  103. }
  104. /**
  105. * ata_sff_sync - Flush writes
  106. * @ap: Port to wait for.
  107. *
  108. * CAUTION:
  109. * If we have an mmio device with no ctl and no altstatus
  110. * method this will fail. No such devices are known to exist.
  111. *
  112. * LOCKING:
  113. * Inherited from caller.
  114. */
  115. static void ata_sff_sync(struct ata_port *ap)
  116. {
  117. if (ap->ops->sff_check_altstatus)
  118. ap->ops->sff_check_altstatus(ap);
  119. else if (ap->ioaddr.altstatus_addr)
  120. ioread8(ap->ioaddr.altstatus_addr);
  121. }
  122. /**
  123. * ata_sff_pause - Flush writes and wait 400nS
  124. * @ap: Port to pause for.
  125. *
  126. * CAUTION:
  127. * If we have an mmio device with no ctl and no altstatus
  128. * method this will fail. No such devices are known to exist.
  129. *
  130. * LOCKING:
  131. * Inherited from caller.
  132. */
  133. void ata_sff_pause(struct ata_port *ap)
  134. {
  135. ata_sff_sync(ap);
  136. ndelay(400);
  137. }
  138. EXPORT_SYMBOL_GPL(ata_sff_pause);
  139. /**
  140. * ata_sff_dma_pause - Pause before commencing DMA
  141. * @ap: Port to pause for.
  142. *
  143. * Perform I/O fencing and ensure sufficient cycle delays occur
  144. * for the HDMA1:0 transition
  145. */
  146. void ata_sff_dma_pause(struct ata_port *ap)
  147. {
  148. if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) {
  149. /* An altstatus read will cause the needed delay without
  150. messing up the IRQ status */
  151. ata_sff_altstatus(ap);
  152. return;
  153. }
  154. /* There are no DMA controllers without ctl. BUG here to ensure
  155. we never violate the HDMA1:0 transition timing and risk
  156. corruption. */
  157. BUG();
  158. }
  159. EXPORT_SYMBOL_GPL(ata_sff_dma_pause);
  160. /**
  161. * ata_sff_busy_sleep - sleep until BSY clears, or timeout
  162. * @ap: port containing status register to be polled
  163. * @tmout_pat: impatience timeout in msecs
  164. * @tmout: overall timeout in msecs
  165. *
  166. * Sleep until ATA Status register bit BSY clears,
  167. * or a timeout occurs.
  168. *
  169. * LOCKING:
  170. * Kernel thread context (may sleep).
  171. *
  172. * RETURNS:
  173. * 0 on success, -errno otherwise.
  174. */
  175. int ata_sff_busy_sleep(struct ata_port *ap,
  176. unsigned long tmout_pat, unsigned long tmout)
  177. {
  178. unsigned long timer_start, timeout;
  179. u8 status;
  180. status = ata_sff_busy_wait(ap, ATA_BUSY, 300);
  181. timer_start = jiffies;
  182. timeout = ata_deadline(timer_start, tmout_pat);
  183. while (status != 0xff && (status & ATA_BUSY) &&
  184. time_before(jiffies, timeout)) {
  185. ata_msleep(ap, 50);
  186. status = ata_sff_busy_wait(ap, ATA_BUSY, 3);
  187. }
  188. if (status != 0xff && (status & ATA_BUSY))
  189. ata_port_warn(ap,
  190. "port is slow to respond, please be patient (Status 0x%x)\n",
  191. status);
  192. timeout = ata_deadline(timer_start, tmout);
  193. while (status != 0xff && (status & ATA_BUSY) &&
  194. time_before(jiffies, timeout)) {
  195. ata_msleep(ap, 50);
  196. status = ap->ops->sff_check_status(ap);
  197. }
  198. if (status == 0xff)
  199. return -ENODEV;
  200. if (status & ATA_BUSY) {
  201. ata_port_err(ap,
  202. "port failed to respond (%lu secs, Status 0x%x)\n",
  203. DIV_ROUND_UP(tmout, 1000), status);
  204. return -EBUSY;
  205. }
  206. return 0;
  207. }
  208. EXPORT_SYMBOL_GPL(ata_sff_busy_sleep);
  209. static int ata_sff_check_ready(struct ata_link *link)
  210. {
  211. u8 status = link->ap->ops->sff_check_status(link->ap);
  212. return ata_check_ready(status);
  213. }
  214. /**
  215. * ata_sff_wait_ready - sleep until BSY clears, or timeout
  216. * @link: SFF link to wait ready status for
  217. * @deadline: deadline jiffies for the operation
  218. *
  219. * Sleep until ATA Status register bit BSY clears, or timeout
  220. * occurs.
  221. *
  222. * LOCKING:
  223. * Kernel thread context (may sleep).
  224. *
  225. * RETURNS:
  226. * 0 on success, -errno otherwise.
  227. */
  228. int ata_sff_wait_ready(struct ata_link *link, unsigned long deadline)
  229. {
  230. return ata_wait_ready(link, deadline, ata_sff_check_ready);
  231. }
  232. EXPORT_SYMBOL_GPL(ata_sff_wait_ready);
  233. /**
  234. * ata_sff_set_devctl - Write device control reg
  235. * @ap: port where the device is
  236. * @ctl: value to write
  237. *
  238. * Writes ATA taskfile device control register.
  239. *
  240. * Note: may NOT be used as the sff_set_devctl() entry in
  241. * ata_port_operations.
  242. *
  243. * LOCKING:
  244. * Inherited from caller.
  245. */
  246. static void ata_sff_set_devctl(struct ata_port *ap, u8 ctl)
  247. {
  248. if (ap->ops->sff_set_devctl)
  249. ap->ops->sff_set_devctl(ap, ctl);
  250. else
  251. iowrite8(ctl, ap->ioaddr.ctl_addr);
  252. }
  253. /**
  254. * ata_sff_dev_select - Select device 0/1 on ATA bus
  255. * @ap: ATA channel to manipulate
  256. * @device: ATA device (numbered from zero) to select
  257. *
  258. * Use the method defined in the ATA specification to
  259. * make either device 0, or device 1, active on the
  260. * ATA channel. Works with both PIO and MMIO.
  261. *
  262. * May be used as the dev_select() entry in ata_port_operations.
  263. *
  264. * LOCKING:
  265. * caller.
  266. */
  267. void ata_sff_dev_select(struct ata_port *ap, unsigned int device)
  268. {
  269. u8 tmp;
  270. if (device == 0)
  271. tmp = ATA_DEVICE_OBS;
  272. else
  273. tmp = ATA_DEVICE_OBS | ATA_DEV1;
  274. iowrite8(tmp, ap->ioaddr.device_addr);
  275. ata_sff_pause(ap); /* needed; also flushes, for mmio */
  276. }
  277. EXPORT_SYMBOL_GPL(ata_sff_dev_select);
  278. /**
  279. * ata_dev_select - Select device 0/1 on ATA bus
  280. * @ap: ATA channel to manipulate
  281. * @device: ATA device (numbered from zero) to select
  282. * @wait: non-zero to wait for Status register BSY bit to clear
  283. * @can_sleep: non-zero if context allows sleeping
  284. *
  285. * Use the method defined in the ATA specification to
  286. * make either device 0, or device 1, active on the
  287. * ATA channel.
  288. *
  289. * This is a high-level version of ata_sff_dev_select(), which
  290. * additionally provides the services of inserting the proper
  291. * pauses and status polling, where needed.
  292. *
  293. * LOCKING:
  294. * caller.
  295. */
  296. static void ata_dev_select(struct ata_port *ap, unsigned int device,
  297. unsigned int wait, unsigned int can_sleep)
  298. {
  299. if (ata_msg_probe(ap))
  300. ata_port_info(ap, "ata_dev_select: ENTER, device %u, wait %u\n",
  301. device, wait);
  302. if (wait)
  303. ata_wait_idle(ap);
  304. ap->ops->sff_dev_select(ap, device);
  305. if (wait) {
  306. if (can_sleep && ap->link.device[device].class == ATA_DEV_ATAPI)
  307. ata_msleep(ap, 150);
  308. ata_wait_idle(ap);
  309. }
  310. }
  311. /**
  312. * ata_sff_irq_on - Enable interrupts on a port.
  313. * @ap: Port on which interrupts are enabled.
  314. *
  315. * Enable interrupts on a legacy IDE device using MMIO or PIO,
  316. * wait for idle, clear any pending interrupts.
  317. *
  318. * Note: may NOT be used as the sff_irq_on() entry in
  319. * ata_port_operations.
  320. *
  321. * LOCKING:
  322. * Inherited from caller.
  323. */
  324. void ata_sff_irq_on(struct ata_port *ap)
  325. {
  326. struct ata_ioports *ioaddr = &ap->ioaddr;
  327. if (ap->ops->sff_irq_on) {
  328. ap->ops->sff_irq_on(ap);
  329. return;
  330. }
  331. ap->ctl &= ~ATA_NIEN;
  332. ap->last_ctl = ap->ctl;
  333. if (ap->ops->sff_set_devctl || ioaddr->ctl_addr)
  334. ata_sff_set_devctl(ap, ap->ctl);
  335. ata_wait_idle(ap);
  336. if (ap->ops->sff_irq_clear)
  337. ap->ops->sff_irq_clear(ap);
  338. }
  339. EXPORT_SYMBOL_GPL(ata_sff_irq_on);
  340. /**
  341. * ata_sff_tf_load - send taskfile registers to host controller
  342. * @ap: Port to which output is sent
  343. * @tf: ATA taskfile register set
  344. *
  345. * Outputs ATA taskfile to standard ATA host controller.
  346. *
  347. * LOCKING:
  348. * Inherited from caller.
  349. */
  350. void ata_sff_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
  351. {
  352. struct ata_ioports *ioaddr = &ap->ioaddr;
  353. unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
  354. if (tf->ctl != ap->last_ctl) {
  355. if (ioaddr->ctl_addr)
  356. iowrite8(tf->ctl, ioaddr->ctl_addr);
  357. ap->last_ctl = tf->ctl;
  358. ata_wait_idle(ap);
  359. }
  360. if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
  361. WARN_ON_ONCE(!ioaddr->ctl_addr);
  362. iowrite8(tf->hob_feature, ioaddr->feature_addr);
  363. iowrite8(tf->hob_nsect, ioaddr->nsect_addr);
  364. iowrite8(tf->hob_lbal, ioaddr->lbal_addr);
  365. iowrite8(tf->hob_lbam, ioaddr->lbam_addr);
  366. iowrite8(tf->hob_lbah, ioaddr->lbah_addr);
  367. VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
  368. tf->hob_feature,
  369. tf->hob_nsect,
  370. tf->hob_lbal,
  371. tf->hob_lbam,
  372. tf->hob_lbah);
  373. }
  374. if (is_addr) {
  375. iowrite8(tf->feature, ioaddr->feature_addr);
  376. iowrite8(tf->nsect, ioaddr->nsect_addr);
  377. iowrite8(tf->lbal, ioaddr->lbal_addr);
  378. iowrite8(tf->lbam, ioaddr->lbam_addr);
  379. iowrite8(tf->lbah, ioaddr->lbah_addr);
  380. VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
  381. tf->feature,
  382. tf->nsect,
  383. tf->lbal,
  384. tf->lbam,
  385. tf->lbah);
  386. }
  387. if (tf->flags & ATA_TFLAG_DEVICE) {
  388. iowrite8(tf->device, ioaddr->device_addr);
  389. VPRINTK("device 0x%X\n", tf->device);
  390. }
  391. ata_wait_idle(ap);
  392. }
  393. EXPORT_SYMBOL_GPL(ata_sff_tf_load);
  394. /**
  395. * ata_sff_tf_read - input device's ATA taskfile shadow registers
  396. * @ap: Port from which input is read
  397. * @tf: ATA taskfile register set for storing input
  398. *
  399. * Reads ATA taskfile registers for currently-selected device
  400. * into @tf. Assumes the device has a fully SFF compliant task file
  401. * layout and behaviour. If you device does not (eg has a different
  402. * status method) then you will need to provide a replacement tf_read
  403. *
  404. * LOCKING:
  405. * Inherited from caller.
  406. */
  407. void ata_sff_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
  408. {
  409. struct ata_ioports *ioaddr = &ap->ioaddr;
  410. tf->command = ata_sff_check_status(ap);
  411. tf->feature = ioread8(ioaddr->error_addr);
  412. tf->nsect = ioread8(ioaddr->nsect_addr);
  413. tf->lbal = ioread8(ioaddr->lbal_addr);
  414. tf->lbam = ioread8(ioaddr->lbam_addr);
  415. tf->lbah = ioread8(ioaddr->lbah_addr);
  416. tf->device = ioread8(ioaddr->device_addr);
  417. if (tf->flags & ATA_TFLAG_LBA48) {
  418. if (likely(ioaddr->ctl_addr)) {
  419. iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
  420. tf->hob_feature = ioread8(ioaddr->error_addr);
  421. tf->hob_nsect = ioread8(ioaddr->nsect_addr);
  422. tf->hob_lbal = ioread8(ioaddr->lbal_addr);
  423. tf->hob_lbam = ioread8(ioaddr->lbam_addr);
  424. tf->hob_lbah = ioread8(ioaddr->lbah_addr);
  425. iowrite8(tf->ctl, ioaddr->ctl_addr);
  426. ap->last_ctl = tf->ctl;
  427. } else
  428. WARN_ON_ONCE(1);
  429. }
  430. }
  431. EXPORT_SYMBOL_GPL(ata_sff_tf_read);
  432. /**
  433. * ata_sff_exec_command - issue ATA command to host controller
  434. * @ap: port to which command is being issued
  435. * @tf: ATA taskfile register set
  436. *
  437. * Issues ATA command, with proper synchronization with interrupt
  438. * handler / other threads.
  439. *
  440. * LOCKING:
  441. * spin_lock_irqsave(host lock)
  442. */
  443. void ata_sff_exec_command(struct ata_port *ap, const struct ata_taskfile *tf)
  444. {
  445. DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
  446. iowrite8(tf->command, ap->ioaddr.command_addr);
  447. ata_sff_pause(ap);
  448. }
  449. EXPORT_SYMBOL_GPL(ata_sff_exec_command);
  450. /**
  451. * ata_tf_to_host - issue ATA taskfile to host controller
  452. * @ap: port to which command is being issued
  453. * @tf: ATA taskfile register set
  454. *
  455. * Issues ATA taskfile register set to ATA host controller,
  456. * with proper synchronization with interrupt handler and
  457. * other threads.
  458. *
  459. * LOCKING:
  460. * spin_lock_irqsave(host lock)
  461. */
  462. static inline void ata_tf_to_host(struct ata_port *ap,
  463. const struct ata_taskfile *tf)
  464. {
  465. ap->ops->sff_tf_load(ap, tf);
  466. ap->ops->sff_exec_command(ap, tf);
  467. }
  468. /**
  469. * ata_sff_data_xfer - Transfer data by PIO
  470. * @qc: queued command
  471. * @buf: data buffer
  472. * @buflen: buffer length
  473. * @rw: read/write
  474. *
  475. * Transfer data from/to the device data register by PIO.
  476. *
  477. * LOCKING:
  478. * Inherited from caller.
  479. *
  480. * RETURNS:
  481. * Bytes consumed.
  482. */
  483. unsigned int ata_sff_data_xfer(struct ata_queued_cmd *qc, unsigned char *buf,
  484. unsigned int buflen, int rw)
  485. {
  486. struct ata_port *ap = qc->dev->link->ap;
  487. void __iomem *data_addr = ap->ioaddr.data_addr;
  488. unsigned int words = buflen >> 1;
  489. /* Transfer multiple of 2 bytes */
  490. if (rw == READ)
  491. ioread16_rep(data_addr, buf, words);
  492. else
  493. iowrite16_rep(data_addr, buf, words);
  494. /* Transfer trailing byte, if any. */
  495. if (unlikely(buflen & 0x01)) {
  496. unsigned char pad[2] = { };
  497. /* Point buf to the tail of buffer */
  498. buf += buflen - 1;
  499. /*
  500. * Use io*16_rep() accessors here as well to avoid pointlessly
  501. * swapping bytes to and from on the big endian machines...
  502. */
  503. if (rw == READ) {
  504. ioread16_rep(data_addr, pad, 1);
  505. *buf = pad[0];
  506. } else {
  507. pad[0] = *buf;
  508. iowrite16_rep(data_addr, pad, 1);
  509. }
  510. words++;
  511. }
  512. return words << 1;
  513. }
  514. EXPORT_SYMBOL_GPL(ata_sff_data_xfer);
  515. /**
  516. * ata_sff_data_xfer32 - Transfer data by PIO
  517. * @qc: queued command
  518. * @buf: data buffer
  519. * @buflen: buffer length
  520. * @rw: read/write
  521. *
  522. * Transfer data from/to the device data register by PIO using 32bit
  523. * I/O operations.
  524. *
  525. * LOCKING:
  526. * Inherited from caller.
  527. *
  528. * RETURNS:
  529. * Bytes consumed.
  530. */
  531. unsigned int ata_sff_data_xfer32(struct ata_queued_cmd *qc, unsigned char *buf,
  532. unsigned int buflen, int rw)
  533. {
  534. struct ata_device *dev = qc->dev;
  535. struct ata_port *ap = dev->link->ap;
  536. void __iomem *data_addr = ap->ioaddr.data_addr;
  537. unsigned int words = buflen >> 2;
  538. int slop = buflen & 3;
  539. if (!(ap->pflags & ATA_PFLAG_PIO32))
  540. return ata_sff_data_xfer(qc, buf, buflen, rw);
  541. /* Transfer multiple of 4 bytes */
  542. if (rw == READ)
  543. ioread32_rep(data_addr, buf, words);
  544. else
  545. iowrite32_rep(data_addr, buf, words);
  546. /* Transfer trailing bytes, if any */
  547. if (unlikely(slop)) {
  548. unsigned char pad[4] = { };
  549. /* Point buf to the tail of buffer */
  550. buf += buflen - slop;
  551. /*
  552. * Use io*_rep() accessors here as well to avoid pointlessly
  553. * swapping bytes to and from on the big endian machines...
  554. */
  555. if (rw == READ) {
  556. if (slop < 3)
  557. ioread16_rep(data_addr, pad, 1);
  558. else
  559. ioread32_rep(data_addr, pad, 1);
  560. memcpy(buf, pad, slop);
  561. } else {
  562. memcpy(pad, buf, slop);
  563. if (slop < 3)
  564. iowrite16_rep(data_addr, pad, 1);
  565. else
  566. iowrite32_rep(data_addr, pad, 1);
  567. }
  568. }
  569. return (buflen + 1) & ~1;
  570. }
  571. EXPORT_SYMBOL_GPL(ata_sff_data_xfer32);
  572. static void ata_pio_xfer(struct ata_queued_cmd *qc, struct page *page,
  573. unsigned int offset, size_t xfer_size)
  574. {
  575. bool do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
  576. unsigned char *buf;
  577. buf = kmap_atomic(page);
  578. qc->ap->ops->sff_data_xfer(qc, buf + offset, xfer_size, do_write);
  579. kunmap_atomic(buf);
  580. if (!do_write && !PageSlab(page))
  581. flush_dcache_page(page);
  582. }
  583. /**
  584. * ata_pio_sector - Transfer a sector of data.
  585. * @qc: Command on going
  586. *
  587. * Transfer qc->sect_size bytes of data from/to the ATA device.
  588. *
  589. * LOCKING:
  590. * Inherited from caller.
  591. */
  592. static void ata_pio_sector(struct ata_queued_cmd *qc)
  593. {
  594. struct ata_port *ap = qc->ap;
  595. struct page *page;
  596. unsigned int offset;
  597. if (!qc->cursg) {
  598. qc->curbytes = qc->nbytes;
  599. return;
  600. }
  601. if (qc->curbytes == qc->nbytes - qc->sect_size)
  602. ap->hsm_task_state = HSM_ST_LAST;
  603. page = sg_page(qc->cursg);
  604. offset = qc->cursg->offset + qc->cursg_ofs;
  605. /* get the current page and offset */
  606. page = nth_page(page, (offset >> PAGE_SHIFT));
  607. offset %= PAGE_SIZE;
  608. DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
  609. /*
  610. * Split the transfer when it splits a page boundary. Note that the
  611. * split still has to be dword aligned like all ATA data transfers.
  612. */
  613. WARN_ON_ONCE(offset % 4);
  614. if (offset + qc->sect_size > PAGE_SIZE) {
  615. unsigned int split_len = PAGE_SIZE - offset;
  616. ata_pio_xfer(qc, page, offset, split_len);
  617. ata_pio_xfer(qc, nth_page(page, 1), 0,
  618. qc->sect_size - split_len);
  619. } else {
  620. ata_pio_xfer(qc, page, offset, qc->sect_size);
  621. }
  622. qc->curbytes += qc->sect_size;
  623. qc->cursg_ofs += qc->sect_size;
  624. if (qc->cursg_ofs == qc->cursg->length) {
  625. qc->cursg = sg_next(qc->cursg);
  626. if (!qc->cursg)
  627. ap->hsm_task_state = HSM_ST_LAST;
  628. qc->cursg_ofs = 0;
  629. }
  630. }
  631. /**
  632. * ata_pio_sectors - Transfer one or many sectors.
  633. * @qc: Command on going
  634. *
  635. * Transfer one or many sectors of data from/to the
  636. * ATA device for the DRQ request.
  637. *
  638. * LOCKING:
  639. * Inherited from caller.
  640. */
  641. static void ata_pio_sectors(struct ata_queued_cmd *qc)
  642. {
  643. if (is_multi_taskfile(&qc->tf)) {
  644. /* READ/WRITE MULTIPLE */
  645. unsigned int nsect;
  646. WARN_ON_ONCE(qc->dev->multi_count == 0);
  647. nsect = min((qc->nbytes - qc->curbytes) / qc->sect_size,
  648. qc->dev->multi_count);
  649. while (nsect--)
  650. ata_pio_sector(qc);
  651. } else
  652. ata_pio_sector(qc);
  653. ata_sff_sync(qc->ap); /* flush */
  654. }
  655. /**
  656. * atapi_send_cdb - Write CDB bytes to hardware
  657. * @ap: Port to which ATAPI device is attached.
  658. * @qc: Taskfile currently active
  659. *
  660. * When device has indicated its readiness to accept
  661. * a CDB, this function is called. Send the CDB.
  662. *
  663. * LOCKING:
  664. * caller.
  665. */
  666. static void atapi_send_cdb(struct ata_port *ap, struct ata_queued_cmd *qc)
  667. {
  668. /* send SCSI cdb */
  669. DPRINTK("send cdb\n");
  670. WARN_ON_ONCE(qc->dev->cdb_len < 12);
  671. ap->ops->sff_data_xfer(qc, qc->cdb, qc->dev->cdb_len, 1);
  672. ata_sff_sync(ap);
  673. /* FIXME: If the CDB is for DMA do we need to do the transition delay
  674. or is bmdma_start guaranteed to do it ? */
  675. switch (qc->tf.protocol) {
  676. case ATAPI_PROT_PIO:
  677. ap->hsm_task_state = HSM_ST;
  678. break;
  679. case ATAPI_PROT_NODATA:
  680. ap->hsm_task_state = HSM_ST_LAST;
  681. break;
  682. #ifdef CONFIG_ATA_BMDMA
  683. case ATAPI_PROT_DMA:
  684. ap->hsm_task_state = HSM_ST_LAST;
  685. /* initiate bmdma */
  686. ap->ops->bmdma_start(qc);
  687. break;
  688. #endif /* CONFIG_ATA_BMDMA */
  689. default:
  690. BUG();
  691. }
  692. }
  693. /**
  694. * __atapi_pio_bytes - Transfer data from/to the ATAPI device.
  695. * @qc: Command on going
  696. * @bytes: number of bytes
  697. *
  698. * Transfer Transfer data from/to the ATAPI device.
  699. *
  700. * LOCKING:
  701. * Inherited from caller.
  702. *
  703. */
  704. static int __atapi_pio_bytes(struct ata_queued_cmd *qc, unsigned int bytes)
  705. {
  706. int rw = (qc->tf.flags & ATA_TFLAG_WRITE) ? WRITE : READ;
  707. struct ata_port *ap = qc->ap;
  708. struct ata_device *dev = qc->dev;
  709. struct ata_eh_info *ehi = &dev->link->eh_info;
  710. struct scatterlist *sg;
  711. struct page *page;
  712. unsigned char *buf;
  713. unsigned int offset, count, consumed;
  714. next_sg:
  715. sg = qc->cursg;
  716. if (unlikely(!sg)) {
  717. ata_ehi_push_desc(ehi, "unexpected or too much trailing data "
  718. "buf=%u cur=%u bytes=%u",
  719. qc->nbytes, qc->curbytes, bytes);
  720. return -1;
  721. }
  722. page = sg_page(sg);
  723. offset = sg->offset + qc->cursg_ofs;
  724. /* get the current page and offset */
  725. page = nth_page(page, (offset >> PAGE_SHIFT));
  726. offset %= PAGE_SIZE;
  727. /* don't overrun current sg */
  728. count = min(sg->length - qc->cursg_ofs, bytes);
  729. /* don't cross page boundaries */
  730. count = min(count, (unsigned int)PAGE_SIZE - offset);
  731. DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
  732. /* do the actual data transfer */
  733. buf = kmap_atomic(page);
  734. consumed = ap->ops->sff_data_xfer(qc, buf + offset, count, rw);
  735. kunmap_atomic(buf);
  736. bytes -= min(bytes, consumed);
  737. qc->curbytes += count;
  738. qc->cursg_ofs += count;
  739. if (qc->cursg_ofs == sg->length) {
  740. qc->cursg = sg_next(qc->cursg);
  741. qc->cursg_ofs = 0;
  742. }
  743. /*
  744. * There used to be a WARN_ON_ONCE(qc->cursg && count != consumed);
  745. * Unfortunately __atapi_pio_bytes doesn't know enough to do the WARN
  746. * check correctly as it doesn't know if it is the last request being
  747. * made. Somebody should implement a proper sanity check.
  748. */
  749. if (bytes)
  750. goto next_sg;
  751. return 0;
  752. }
  753. /**
  754. * atapi_pio_bytes - Transfer data from/to the ATAPI device.
  755. * @qc: Command on going
  756. *
  757. * Transfer Transfer data from/to the ATAPI device.
  758. *
  759. * LOCKING:
  760. * Inherited from caller.
  761. */
  762. static void atapi_pio_bytes(struct ata_queued_cmd *qc)
  763. {
  764. struct ata_port *ap = qc->ap;
  765. struct ata_device *dev = qc->dev;
  766. struct ata_eh_info *ehi = &dev->link->eh_info;
  767. unsigned int ireason, bc_lo, bc_hi, bytes;
  768. int i_write, do_write = (qc->tf.flags & ATA_TFLAG_WRITE) ? 1 : 0;
  769. /* Abuse qc->result_tf for temp storage of intermediate TF
  770. * here to save some kernel stack usage.
  771. * For normal completion, qc->result_tf is not relevant. For
  772. * error, qc->result_tf is later overwritten by ata_qc_complete().
  773. * So, the correctness of qc->result_tf is not affected.
  774. */
  775. ap->ops->sff_tf_read(ap, &qc->result_tf);
  776. ireason = qc->result_tf.nsect;
  777. bc_lo = qc->result_tf.lbam;
  778. bc_hi = qc->result_tf.lbah;
  779. bytes = (bc_hi << 8) | bc_lo;
  780. /* shall be cleared to zero, indicating xfer of data */
  781. if (unlikely(ireason & ATAPI_COD))
  782. goto atapi_check;
  783. /* make sure transfer direction matches expected */
  784. i_write = ((ireason & ATAPI_IO) == 0) ? 1 : 0;
  785. if (unlikely(do_write != i_write))
  786. goto atapi_check;
  787. if (unlikely(!bytes))
  788. goto atapi_check;
  789. VPRINTK("ata%u: xfering %d bytes\n", ap->print_id, bytes);
  790. if (unlikely(__atapi_pio_bytes(qc, bytes)))
  791. goto err_out;
  792. ata_sff_sync(ap); /* flush */
  793. return;
  794. atapi_check:
  795. ata_ehi_push_desc(ehi, "ATAPI check failed (ireason=0x%x bytes=%u)",
  796. ireason, bytes);
  797. err_out:
  798. qc->err_mask |= AC_ERR_HSM;
  799. ap->hsm_task_state = HSM_ST_ERR;
  800. }
  801. /**
  802. * ata_hsm_ok_in_wq - Check if the qc can be handled in the workqueue.
  803. * @ap: the target ata_port
  804. * @qc: qc on going
  805. *
  806. * RETURNS:
  807. * 1 if ok in workqueue, 0 otherwise.
  808. */
  809. static inline int ata_hsm_ok_in_wq(struct ata_port *ap,
  810. struct ata_queued_cmd *qc)
  811. {
  812. if (qc->tf.flags & ATA_TFLAG_POLLING)
  813. return 1;
  814. if (ap->hsm_task_state == HSM_ST_FIRST) {
  815. if (qc->tf.protocol == ATA_PROT_PIO &&
  816. (qc->tf.flags & ATA_TFLAG_WRITE))
  817. return 1;
  818. if (ata_is_atapi(qc->tf.protocol) &&
  819. !(qc->dev->flags & ATA_DFLAG_CDB_INTR))
  820. return 1;
  821. }
  822. return 0;
  823. }
  824. /**
  825. * ata_hsm_qc_complete - finish a qc running on standard HSM
  826. * @qc: Command to complete
  827. * @in_wq: 1 if called from workqueue, 0 otherwise
  828. *
  829. * Finish @qc which is running on standard HSM.
  830. *
  831. * LOCKING:
  832. * If @in_wq is zero, spin_lock_irqsave(host lock).
  833. * Otherwise, none on entry and grabs host lock.
  834. */
  835. static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq)
  836. {
  837. struct ata_port *ap = qc->ap;
  838. if (ap->ops->error_handler) {
  839. if (in_wq) {
  840. /* EH might have kicked in while host lock is
  841. * released.
  842. */
  843. qc = ata_qc_from_tag(ap, qc->tag);
  844. if (qc) {
  845. if (likely(!(qc->err_mask & AC_ERR_HSM))) {
  846. ata_sff_irq_on(ap);
  847. ata_qc_complete(qc);
  848. } else
  849. ata_port_freeze(ap);
  850. }
  851. } else {
  852. if (likely(!(qc->err_mask & AC_ERR_HSM)))
  853. ata_qc_complete(qc);
  854. else
  855. ata_port_freeze(ap);
  856. }
  857. } else {
  858. if (in_wq) {
  859. ata_sff_irq_on(ap);
  860. ata_qc_complete(qc);
  861. } else
  862. ata_qc_complete(qc);
  863. }
  864. }
  865. /**
  866. * ata_sff_hsm_move - move the HSM to the next state.
  867. * @ap: the target ata_port
  868. * @qc: qc on going
  869. * @status: current device status
  870. * @in_wq: 1 if called from workqueue, 0 otherwise
  871. *
  872. * RETURNS:
  873. * 1 when poll next status needed, 0 otherwise.
  874. */
  875. int ata_sff_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc,
  876. u8 status, int in_wq)
  877. {
  878. struct ata_link *link = qc->dev->link;
  879. struct ata_eh_info *ehi = &link->eh_info;
  880. int poll_next;
  881. lockdep_assert_held(ap->lock);
  882. WARN_ON_ONCE((qc->flags & ATA_QCFLAG_ACTIVE) == 0);
  883. /* Make sure ata_sff_qc_issue() does not throw things
  884. * like DMA polling into the workqueue. Notice that
  885. * in_wq is not equivalent to (qc->tf.flags & ATA_TFLAG_POLLING).
  886. */
  887. WARN_ON_ONCE(in_wq != ata_hsm_ok_in_wq(ap, qc));
  888. fsm_start:
  889. DPRINTK("ata%u: protocol %d task_state %d (dev_stat 0x%X)\n",
  890. ap->print_id, qc->tf.protocol, ap->hsm_task_state, status);
  891. switch (ap->hsm_task_state) {
  892. case HSM_ST_FIRST:
  893. /* Send first data block or PACKET CDB */
  894. /* If polling, we will stay in the work queue after
  895. * sending the data. Otherwise, interrupt handler
  896. * takes over after sending the data.
  897. */
  898. poll_next = (qc->tf.flags & ATA_TFLAG_POLLING);
  899. /* check device status */
  900. if (unlikely((status & ATA_DRQ) == 0)) {
  901. /* handle BSY=0, DRQ=0 as error */
  902. if (likely(status & (ATA_ERR | ATA_DF)))
  903. /* device stops HSM for abort/error */
  904. qc->err_mask |= AC_ERR_DEV;
  905. else {
  906. /* HSM violation. Let EH handle this */
  907. ata_ehi_push_desc(ehi,
  908. "ST_FIRST: !(DRQ|ERR|DF)");
  909. qc->err_mask |= AC_ERR_HSM;
  910. }
  911. ap->hsm_task_state = HSM_ST_ERR;
  912. goto fsm_start;
  913. }
  914. /* Device should not ask for data transfer (DRQ=1)
  915. * when it finds something wrong.
  916. * We ignore DRQ here and stop the HSM by
  917. * changing hsm_task_state to HSM_ST_ERR and
  918. * let the EH abort the command or reset the device.
  919. */
  920. if (unlikely(status & (ATA_ERR | ATA_DF))) {
  921. /* Some ATAPI tape drives forget to clear the ERR bit
  922. * when doing the next command (mostly request sense).
  923. * We ignore ERR here to workaround and proceed sending
  924. * the CDB.
  925. */
  926. if (!(qc->dev->horkage & ATA_HORKAGE_STUCK_ERR)) {
  927. ata_ehi_push_desc(ehi, "ST_FIRST: "
  928. "DRQ=1 with device error, "
  929. "dev_stat 0x%X", status);
  930. qc->err_mask |= AC_ERR_HSM;
  931. ap->hsm_task_state = HSM_ST_ERR;
  932. goto fsm_start;
  933. }
  934. }
  935. if (qc->tf.protocol == ATA_PROT_PIO) {
  936. /* PIO data out protocol.
  937. * send first data block.
  938. */
  939. /* ata_pio_sectors() might change the state
  940. * to HSM_ST_LAST. so, the state is changed here
  941. * before ata_pio_sectors().
  942. */
  943. ap->hsm_task_state = HSM_ST;
  944. ata_pio_sectors(qc);
  945. } else
  946. /* send CDB */
  947. atapi_send_cdb(ap, qc);
  948. /* if polling, ata_sff_pio_task() handles the rest.
  949. * otherwise, interrupt handler takes over from here.
  950. */
  951. break;
  952. case HSM_ST:
  953. /* complete command or read/write the data register */
  954. if (qc->tf.protocol == ATAPI_PROT_PIO) {
  955. /* ATAPI PIO protocol */
  956. if ((status & ATA_DRQ) == 0) {
  957. /* No more data to transfer or device error.
  958. * Device error will be tagged in HSM_ST_LAST.
  959. */
  960. ap->hsm_task_state = HSM_ST_LAST;
  961. goto fsm_start;
  962. }
  963. /* Device should not ask for data transfer (DRQ=1)
  964. * when it finds something wrong.
  965. * We ignore DRQ here and stop the HSM by
  966. * changing hsm_task_state to HSM_ST_ERR and
  967. * let the EH abort the command or reset the device.
  968. */
  969. if (unlikely(status & (ATA_ERR | ATA_DF))) {
  970. ata_ehi_push_desc(ehi, "ST-ATAPI: "
  971. "DRQ=1 with device error, "
  972. "dev_stat 0x%X", status);
  973. qc->err_mask |= AC_ERR_HSM;
  974. ap->hsm_task_state = HSM_ST_ERR;
  975. goto fsm_start;
  976. }
  977. atapi_pio_bytes(qc);
  978. if (unlikely(ap->hsm_task_state == HSM_ST_ERR))
  979. /* bad ireason reported by device */
  980. goto fsm_start;
  981. } else {
  982. /* ATA PIO protocol */
  983. if (unlikely((status & ATA_DRQ) == 0)) {
  984. /* handle BSY=0, DRQ=0 as error */
  985. if (likely(status & (ATA_ERR | ATA_DF))) {
  986. /* device stops HSM for abort/error */
  987. qc->err_mask |= AC_ERR_DEV;
  988. /* If diagnostic failed and this is
  989. * IDENTIFY, it's likely a phantom
  990. * device. Mark hint.
  991. */
  992. if (qc->dev->horkage &
  993. ATA_HORKAGE_DIAGNOSTIC)
  994. qc->err_mask |=
  995. AC_ERR_NODEV_HINT;
  996. } else {
  997. /* HSM violation. Let EH handle this.
  998. * Phantom devices also trigger this
  999. * condition. Mark hint.
  1000. */
  1001. ata_ehi_push_desc(ehi, "ST-ATA: "
  1002. "DRQ=0 without device error, "
  1003. "dev_stat 0x%X", status);
  1004. qc->err_mask |= AC_ERR_HSM |
  1005. AC_ERR_NODEV_HINT;
  1006. }
  1007. ap->hsm_task_state = HSM_ST_ERR;
  1008. goto fsm_start;
  1009. }
  1010. /* For PIO reads, some devices may ask for
  1011. * data transfer (DRQ=1) alone with ERR=1.
  1012. * We respect DRQ here and transfer one
  1013. * block of junk data before changing the
  1014. * hsm_task_state to HSM_ST_ERR.
  1015. *
  1016. * For PIO writes, ERR=1 DRQ=1 doesn't make
  1017. * sense since the data block has been
  1018. * transferred to the device.
  1019. */
  1020. if (unlikely(status & (ATA_ERR | ATA_DF))) {
  1021. /* data might be corrputed */
  1022. qc->err_mask |= AC_ERR_DEV;
  1023. if (!(qc->tf.flags & ATA_TFLAG_WRITE)) {
  1024. ata_pio_sectors(qc);
  1025. status = ata_wait_idle(ap);
  1026. }
  1027. if (status & (ATA_BUSY | ATA_DRQ)) {
  1028. ata_ehi_push_desc(ehi, "ST-ATA: "
  1029. "BUSY|DRQ persists on ERR|DF, "
  1030. "dev_stat 0x%X", status);
  1031. qc->err_mask |= AC_ERR_HSM;
  1032. }
  1033. /* There are oddball controllers with
  1034. * status register stuck at 0x7f and
  1035. * lbal/m/h at zero which makes it
  1036. * pass all other presence detection
  1037. * mechanisms we have. Set NODEV_HINT
  1038. * for it. Kernel bz#7241.
  1039. */
  1040. if (status == 0x7f)
  1041. qc->err_mask |= AC_ERR_NODEV_HINT;
  1042. /* ata_pio_sectors() might change the
  1043. * state to HSM_ST_LAST. so, the state
  1044. * is changed after ata_pio_sectors().
  1045. */
  1046. ap->hsm_task_state = HSM_ST_ERR;
  1047. goto fsm_start;
  1048. }
  1049. ata_pio_sectors(qc);
  1050. if (ap->hsm_task_state == HSM_ST_LAST &&
  1051. (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
  1052. /* all data read */
  1053. status = ata_wait_idle(ap);
  1054. goto fsm_start;
  1055. }
  1056. }
  1057. poll_next = 1;
  1058. break;
  1059. case HSM_ST_LAST:
  1060. if (unlikely(!ata_ok(status))) {
  1061. qc->err_mask |= __ac_err_mask(status);
  1062. ap->hsm_task_state = HSM_ST_ERR;
  1063. goto fsm_start;
  1064. }
  1065. /* no more data to transfer */
  1066. DPRINTK("ata%u: dev %u command complete, drv_stat 0x%x\n",
  1067. ap->print_id, qc->dev->devno, status);
  1068. WARN_ON_ONCE(qc->err_mask & (AC_ERR_DEV | AC_ERR_HSM));
  1069. ap->hsm_task_state = HSM_ST_IDLE;
  1070. /* complete taskfile transaction */
  1071. ata_hsm_qc_complete(qc, in_wq);
  1072. poll_next = 0;
  1073. break;
  1074. case HSM_ST_ERR:
  1075. ap->hsm_task_state = HSM_ST_IDLE;
  1076. /* complete taskfile transaction */
  1077. ata_hsm_qc_complete(qc, in_wq);
  1078. poll_next = 0;
  1079. break;
  1080. default:
  1081. poll_next = 0;
  1082. WARN(true, "ata%d: SFF host state machine in invalid state %d",
  1083. ap->print_id, ap->hsm_task_state);
  1084. }
  1085. return poll_next;
  1086. }
  1087. EXPORT_SYMBOL_GPL(ata_sff_hsm_move);
  1088. void ata_sff_queue_work(struct work_struct *work)
  1089. {
  1090. queue_work(ata_sff_wq, work);
  1091. }
  1092. EXPORT_SYMBOL_GPL(ata_sff_queue_work);
  1093. void ata_sff_queue_delayed_work(struct delayed_work *dwork, unsigned long delay)
  1094. {
  1095. queue_delayed_work(ata_sff_wq, dwork, delay);
  1096. }
  1097. EXPORT_SYMBOL_GPL(ata_sff_queue_delayed_work);
  1098. void ata_sff_queue_pio_task(struct ata_link *link, unsigned long delay)
  1099. {
  1100. struct ata_port *ap = link->ap;
  1101. WARN_ON((ap->sff_pio_task_link != NULL) &&
  1102. (ap->sff_pio_task_link != link));
  1103. ap->sff_pio_task_link = link;
  1104. /* may fail if ata_sff_flush_pio_task() in progress */
  1105. ata_sff_queue_delayed_work(&ap->sff_pio_task, msecs_to_jiffies(delay));
  1106. }
  1107. EXPORT_SYMBOL_GPL(ata_sff_queue_pio_task);
  1108. void ata_sff_flush_pio_task(struct ata_port *ap)
  1109. {
  1110. DPRINTK("ENTER\n");
  1111. cancel_delayed_work_sync(&ap->sff_pio_task);
  1112. /*
  1113. * We wanna reset the HSM state to IDLE. If we do so without
  1114. * grabbing the port lock, critical sections protected by it which
  1115. * expect the HSM state to stay stable may get surprised. For
  1116. * example, we may set IDLE in between the time
  1117. * __ata_sff_port_intr() checks for HSM_ST_IDLE and before it calls
  1118. * ata_sff_hsm_move() causing ata_sff_hsm_move() to BUG().
  1119. */
  1120. spin_lock_irq(ap->lock);
  1121. ap->hsm_task_state = HSM_ST_IDLE;
  1122. spin_unlock_irq(ap->lock);
  1123. ap->sff_pio_task_link = NULL;
  1124. if (ata_msg_ctl(ap))
  1125. ata_port_dbg(ap, "%s: EXIT\n", __func__);
  1126. }
  1127. static void ata_sff_pio_task(struct work_struct *work)
  1128. {
  1129. struct ata_port *ap =
  1130. container_of(work, struct ata_port, sff_pio_task.work);
  1131. struct ata_link *link = ap->sff_pio_task_link;
  1132. struct ata_queued_cmd *qc;
  1133. u8 status;
  1134. int poll_next;
  1135. spin_lock_irq(ap->lock);
  1136. BUG_ON(ap->sff_pio_task_link == NULL);
  1137. /* qc can be NULL if timeout occurred */
  1138. qc = ata_qc_from_tag(ap, link->active_tag);
  1139. if (!qc) {
  1140. ap->sff_pio_task_link = NULL;
  1141. goto out_unlock;
  1142. }
  1143. fsm_start:
  1144. WARN_ON_ONCE(ap->hsm_task_state == HSM_ST_IDLE);
  1145. /*
  1146. * This is purely heuristic. This is a fast path.
  1147. * Sometimes when we enter, BSY will be cleared in
  1148. * a chk-status or two. If not, the drive is probably seeking
  1149. * or something. Snooze for a couple msecs, then
  1150. * chk-status again. If still busy, queue delayed work.
  1151. */
  1152. status = ata_sff_busy_wait(ap, ATA_BUSY, 5);
  1153. if (status & ATA_BUSY) {
  1154. spin_unlock_irq(ap->lock);
  1155. ata_msleep(ap, 2);
  1156. spin_lock_irq(ap->lock);
  1157. status = ata_sff_busy_wait(ap, ATA_BUSY, 10);
  1158. if (status & ATA_BUSY) {
  1159. ata_sff_queue_pio_task(link, ATA_SHORT_PAUSE);
  1160. goto out_unlock;
  1161. }
  1162. }
  1163. /*
  1164. * hsm_move() may trigger another command to be processed.
  1165. * clean the link beforehand.
  1166. */
  1167. ap->sff_pio_task_link = NULL;
  1168. /* move the HSM */
  1169. poll_next = ata_sff_hsm_move(ap, qc, status, 1);
  1170. /* another command or interrupt handler
  1171. * may be running at this point.
  1172. */
  1173. if (poll_next)
  1174. goto fsm_start;
  1175. out_unlock:
  1176. spin_unlock_irq(ap->lock);
  1177. }
  1178. /**
  1179. * ata_sff_qc_issue - issue taskfile to a SFF controller
  1180. * @qc: command to issue to device
  1181. *
  1182. * This function issues a PIO or NODATA command to a SFF
  1183. * controller.
  1184. *
  1185. * LOCKING:
  1186. * spin_lock_irqsave(host lock)
  1187. *
  1188. * RETURNS:
  1189. * Zero on success, AC_ERR_* mask on failure
  1190. */
  1191. unsigned int ata_sff_qc_issue(struct ata_queued_cmd *qc)
  1192. {
  1193. struct ata_port *ap = qc->ap;
  1194. struct ata_link *link = qc->dev->link;
  1195. /* Use polling pio if the LLD doesn't handle
  1196. * interrupt driven pio and atapi CDB interrupt.
  1197. */
  1198. if (ap->flags & ATA_FLAG_PIO_POLLING)
  1199. qc->tf.flags |= ATA_TFLAG_POLLING;
  1200. /* select the device */
  1201. ata_dev_select(ap, qc->dev->devno, 1, 0);
  1202. /* start the command */
  1203. switch (qc->tf.protocol) {
  1204. case ATA_PROT_NODATA:
  1205. if (qc->tf.flags & ATA_TFLAG_POLLING)
  1206. ata_qc_set_polling(qc);
  1207. ata_tf_to_host(ap, &qc->tf);
  1208. ap->hsm_task_state = HSM_ST_LAST;
  1209. if (qc->tf.flags & ATA_TFLAG_POLLING)
  1210. ata_sff_queue_pio_task(link, 0);
  1211. break;
  1212. case ATA_PROT_PIO:
  1213. if (qc->tf.flags & ATA_TFLAG_POLLING)
  1214. ata_qc_set_polling(qc);
  1215. ata_tf_to_host(ap, &qc->tf);
  1216. if (qc->tf.flags & ATA_TFLAG_WRITE) {
  1217. /* PIO data out protocol */
  1218. ap->hsm_task_state = HSM_ST_FIRST;
  1219. ata_sff_queue_pio_task(link, 0);
  1220. /* always send first data block using the
  1221. * ata_sff_pio_task() codepath.
  1222. */
  1223. } else {
  1224. /* PIO data in protocol */
  1225. ap->hsm_task_state = HSM_ST;
  1226. if (qc->tf.flags & ATA_TFLAG_POLLING)
  1227. ata_sff_queue_pio_task(link, 0);
  1228. /* if polling, ata_sff_pio_task() handles the
  1229. * rest. otherwise, interrupt handler takes
  1230. * over from here.
  1231. */
  1232. }
  1233. break;
  1234. case ATAPI_PROT_PIO:
  1235. case ATAPI_PROT_NODATA:
  1236. if (qc->tf.flags & ATA_TFLAG_POLLING)
  1237. ata_qc_set_polling(qc);
  1238. ata_tf_to_host(ap, &qc->tf);
  1239. ap->hsm_task_state = HSM_ST_FIRST;
  1240. /* send cdb by polling if no cdb interrupt */
  1241. if ((!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) ||
  1242. (qc->tf.flags & ATA_TFLAG_POLLING))
  1243. ata_sff_queue_pio_task(link, 0);
  1244. break;
  1245. default:
  1246. return AC_ERR_SYSTEM;
  1247. }
  1248. return 0;
  1249. }
  1250. EXPORT_SYMBOL_GPL(ata_sff_qc_issue);
  1251. /**
  1252. * ata_sff_qc_fill_rtf - fill result TF using ->sff_tf_read
  1253. * @qc: qc to fill result TF for
  1254. *
  1255. * @qc is finished and result TF needs to be filled. Fill it
  1256. * using ->sff_tf_read.
  1257. *
  1258. * LOCKING:
  1259. * spin_lock_irqsave(host lock)
  1260. *
  1261. * RETURNS:
  1262. * true indicating that result TF is successfully filled.
  1263. */
  1264. bool ata_sff_qc_fill_rtf(struct ata_queued_cmd *qc)
  1265. {
  1266. qc->ap->ops->sff_tf_read(qc->ap, &qc->result_tf);
  1267. return true;
  1268. }
  1269. EXPORT_SYMBOL_GPL(ata_sff_qc_fill_rtf);
  1270. static unsigned int ata_sff_idle_irq(struct ata_port *ap)
  1271. {
  1272. ap->stats.idle_irq++;
  1273. #ifdef ATA_IRQ_TRAP
  1274. if ((ap->stats.idle_irq % 1000) == 0) {
  1275. ap->ops->sff_check_status(ap);
  1276. if (ap->ops->sff_irq_clear)
  1277. ap->ops->sff_irq_clear(ap);
  1278. ata_port_warn(ap, "irq trap\n");
  1279. return 1;
  1280. }
  1281. #endif
  1282. return 0; /* irq not handled */
  1283. }
  1284. static unsigned int __ata_sff_port_intr(struct ata_port *ap,
  1285. struct ata_queued_cmd *qc,
  1286. bool hsmv_on_idle)
  1287. {
  1288. u8 status;
  1289. VPRINTK("ata%u: protocol %d task_state %d\n",
  1290. ap->print_id, qc->tf.protocol, ap->hsm_task_state);
  1291. /* Check whether we are expecting interrupt in this state */
  1292. switch (ap->hsm_task_state) {
  1293. case HSM_ST_FIRST:
  1294. /* Some pre-ATAPI-4 devices assert INTRQ
  1295. * at this state when ready to receive CDB.
  1296. */
  1297. /* Check the ATA_DFLAG_CDB_INTR flag is enough here.
  1298. * The flag was turned on only for atapi devices. No
  1299. * need to check ata_is_atapi(qc->tf.protocol) again.
  1300. */
  1301. if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
  1302. return ata_sff_idle_irq(ap);
  1303. break;
  1304. case HSM_ST_IDLE:
  1305. return ata_sff_idle_irq(ap);
  1306. default:
  1307. break;
  1308. }
  1309. /* check main status, clearing INTRQ if needed */
  1310. status = ata_sff_irq_status(ap);
  1311. if (status & ATA_BUSY) {
  1312. if (hsmv_on_idle) {
  1313. /* BMDMA engine is already stopped, we're screwed */
  1314. qc->err_mask |= AC_ERR_HSM;
  1315. ap->hsm_task_state = HSM_ST_ERR;
  1316. } else
  1317. return ata_sff_idle_irq(ap);
  1318. }
  1319. /* clear irq events */
  1320. if (ap->ops->sff_irq_clear)
  1321. ap->ops->sff_irq_clear(ap);
  1322. ata_sff_hsm_move(ap, qc, status, 0);
  1323. return 1; /* irq handled */
  1324. }
  1325. /**
  1326. * ata_sff_port_intr - Handle SFF port interrupt
  1327. * @ap: Port on which interrupt arrived (possibly...)
  1328. * @qc: Taskfile currently active in engine
  1329. *
  1330. * Handle port interrupt for given queued command.
  1331. *
  1332. * LOCKING:
  1333. * spin_lock_irqsave(host lock)
  1334. *
  1335. * RETURNS:
  1336. * One if interrupt was handled, zero if not (shared irq).
  1337. */
  1338. unsigned int ata_sff_port_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
  1339. {
  1340. return __ata_sff_port_intr(ap, qc, false);
  1341. }
  1342. EXPORT_SYMBOL_GPL(ata_sff_port_intr);
  1343. static inline irqreturn_t __ata_sff_interrupt(int irq, void *dev_instance,
  1344. unsigned int (*port_intr)(struct ata_port *, struct ata_queued_cmd *))
  1345. {
  1346. struct ata_host *host = dev_instance;
  1347. bool retried = false;
  1348. unsigned int i;
  1349. unsigned int handled, idle, polling;
  1350. unsigned long flags;
  1351. /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */
  1352. spin_lock_irqsave(&host->lock, flags);
  1353. retry:
  1354. handled = idle = polling = 0;
  1355. for (i = 0; i < host->n_ports; i++) {
  1356. struct ata_port *ap = host->ports[i];
  1357. struct ata_queued_cmd *qc;
  1358. qc = ata_qc_from_tag(ap, ap->link.active_tag);
  1359. if (qc) {
  1360. if (!(qc->tf.flags & ATA_TFLAG_POLLING))
  1361. handled |= port_intr(ap, qc);
  1362. else
  1363. polling |= 1 << i;
  1364. } else
  1365. idle |= 1 << i;
  1366. }
  1367. /*
  1368. * If no port was expecting IRQ but the controller is actually
  1369. * asserting IRQ line, nobody cared will ensue. Check IRQ
  1370. * pending status if available and clear spurious IRQ.
  1371. */
  1372. if (!handled && !retried) {
  1373. bool retry = false;
  1374. for (i = 0; i < host->n_ports; i++) {
  1375. struct ata_port *ap = host->ports[i];
  1376. if (polling & (1 << i))
  1377. continue;
  1378. if (!ap->ops->sff_irq_check ||
  1379. !ap->ops->sff_irq_check(ap))
  1380. continue;
  1381. if (idle & (1 << i)) {
  1382. ap->ops->sff_check_status(ap);
  1383. if (ap->ops->sff_irq_clear)
  1384. ap->ops->sff_irq_clear(ap);
  1385. } else {
  1386. /* clear INTRQ and check if BUSY cleared */
  1387. if (!(ap->ops->sff_check_status(ap) & ATA_BUSY))
  1388. retry |= true;
  1389. /*
  1390. * With command in flight, we can't do
  1391. * sff_irq_clear() w/o racing with completion.
  1392. */
  1393. }
  1394. }
  1395. if (retry) {
  1396. retried = true;
  1397. goto retry;
  1398. }
  1399. }
  1400. spin_unlock_irqrestore(&host->lock, flags);
  1401. return IRQ_RETVAL(handled);
  1402. }
  1403. /**
  1404. * ata_sff_interrupt - Default SFF ATA host interrupt handler
  1405. * @irq: irq line (unused)
  1406. * @dev_instance: pointer to our ata_host information structure
  1407. *
  1408. * Default interrupt handler for PCI IDE devices. Calls
  1409. * ata_sff_port_intr() for each port that is not disabled.
  1410. *
  1411. * LOCKING:
  1412. * Obtains host lock during operation.
  1413. *
  1414. * RETURNS:
  1415. * IRQ_NONE or IRQ_HANDLED.
  1416. */
  1417. irqreturn_t ata_sff_interrupt(int irq, void *dev_instance)
  1418. {
  1419. return __ata_sff_interrupt(irq, dev_instance, ata_sff_port_intr);
  1420. }
  1421. EXPORT_SYMBOL_GPL(ata_sff_interrupt);
  1422. /**
  1423. * ata_sff_lost_interrupt - Check for an apparent lost interrupt
  1424. * @ap: port that appears to have timed out
  1425. *
  1426. * Called from the libata error handlers when the core code suspects
  1427. * an interrupt has been lost. If it has complete anything we can and
  1428. * then return. Interface must support altstatus for this faster
  1429. * recovery to occur.
  1430. *
  1431. * Locking:
  1432. * Caller holds host lock
  1433. */
  1434. void ata_sff_lost_interrupt(struct ata_port *ap)
  1435. {
  1436. u8 status;
  1437. struct ata_queued_cmd *qc;
  1438. /* Only one outstanding command per SFF channel */
  1439. qc = ata_qc_from_tag(ap, ap->link.active_tag);
  1440. /* We cannot lose an interrupt on a non-existent or polled command */
  1441. if (!qc || qc->tf.flags & ATA_TFLAG_POLLING)
  1442. return;
  1443. /* See if the controller thinks it is still busy - if so the command
  1444. isn't a lost IRQ but is still in progress */
  1445. status = ata_sff_altstatus(ap);
  1446. if (status & ATA_BUSY)
  1447. return;
  1448. /* There was a command running, we are no longer busy and we have
  1449. no interrupt. */
  1450. ata_port_warn(ap, "lost interrupt (Status 0x%x)\n",
  1451. status);
  1452. /* Run the host interrupt logic as if the interrupt had not been
  1453. lost */
  1454. ata_sff_port_intr(ap, qc);
  1455. }
  1456. EXPORT_SYMBOL_GPL(ata_sff_lost_interrupt);
  1457. /**
  1458. * ata_sff_freeze - Freeze SFF controller port
  1459. * @ap: port to freeze
  1460. *
  1461. * Freeze SFF controller port.
  1462. *
  1463. * LOCKING:
  1464. * Inherited from caller.
  1465. */
  1466. void ata_sff_freeze(struct ata_port *ap)
  1467. {
  1468. ap->ctl |= ATA_NIEN;
  1469. ap->last_ctl = ap->ctl;
  1470. if (ap->ops->sff_set_devctl || ap->ioaddr.ctl_addr)
  1471. ata_sff_set_devctl(ap, ap->ctl);
  1472. /* Under certain circumstances, some controllers raise IRQ on
  1473. * ATA_NIEN manipulation. Also, many controllers fail to mask
  1474. * previously pending IRQ on ATA_NIEN assertion. Clear it.
  1475. */
  1476. ap->ops->sff_check_status(ap);
  1477. if (ap->ops->sff_irq_clear)
  1478. ap->ops->sff_irq_clear(ap);
  1479. }
  1480. EXPORT_SYMBOL_GPL(ata_sff_freeze);
  1481. /**
  1482. * ata_sff_thaw - Thaw SFF controller port
  1483. * @ap: port to thaw
  1484. *
  1485. * Thaw SFF controller port.
  1486. *
  1487. * LOCKING:
  1488. * Inherited from caller.
  1489. */
  1490. void ata_sff_thaw(struct ata_port *ap)
  1491. {
  1492. /* clear & re-enable interrupts */
  1493. ap->ops->sff_check_status(ap);
  1494. if (ap->ops->sff_irq_clear)
  1495. ap->ops->sff_irq_clear(ap);
  1496. ata_sff_irq_on(ap);
  1497. }
  1498. EXPORT_SYMBOL_GPL(ata_sff_thaw);
  1499. /**
  1500. * ata_sff_prereset - prepare SFF link for reset
  1501. * @link: SFF link to be reset
  1502. * @deadline: deadline jiffies for the operation
  1503. *
  1504. * SFF link @link is about to be reset. Initialize it. It first
  1505. * calls ata_std_prereset() and wait for !BSY if the port is
  1506. * being softreset.
  1507. *
  1508. * LOCKING:
  1509. * Kernel thread context (may sleep)
  1510. *
  1511. * RETURNS:
  1512. * 0 on success, -errno otherwise.
  1513. */
  1514. int ata_sff_prereset(struct ata_link *link, unsigned long deadline)
  1515. {
  1516. struct ata_eh_context *ehc = &link->eh_context;
  1517. int rc;
  1518. rc = ata_std_prereset(link, deadline);
  1519. if (rc)
  1520. return rc;
  1521. /* if we're about to do hardreset, nothing more to do */
  1522. if (ehc->i.action & ATA_EH_HARDRESET)
  1523. return 0;
  1524. /* wait for !BSY if we don't know that no device is attached */
  1525. if (!ata_link_offline(link)) {
  1526. rc = ata_sff_wait_ready(link, deadline);
  1527. if (rc && rc != -ENODEV) {
  1528. ata_link_warn(link,
  1529. "device not ready (errno=%d), forcing hardreset\n",
  1530. rc);
  1531. ehc->i.action |= ATA_EH_HARDRESET;
  1532. }
  1533. }
  1534. return 0;
  1535. }
  1536. EXPORT_SYMBOL_GPL(ata_sff_prereset);
  1537. /**
  1538. * ata_devchk - PATA device presence detection
  1539. * @ap: ATA channel to examine
  1540. * @device: Device to examine (starting at zero)
  1541. *
  1542. * This technique was originally described in
  1543. * Hale Landis's ATADRVR (www.ata-atapi.com), and
  1544. * later found its way into the ATA/ATAPI spec.
  1545. *
  1546. * Write a pattern to the ATA shadow registers,
  1547. * and if a device is present, it will respond by
  1548. * correctly storing and echoing back the
  1549. * ATA shadow register contents.
  1550. *
  1551. * LOCKING:
  1552. * caller.
  1553. */
  1554. static unsigned int ata_devchk(struct ata_port *ap, unsigned int device)
  1555. {
  1556. struct ata_ioports *ioaddr = &ap->ioaddr;
  1557. u8 nsect, lbal;
  1558. ap->ops->sff_dev_select(ap, device);
  1559. iowrite8(0x55, ioaddr->nsect_addr);
  1560. iowrite8(0xaa, ioaddr->lbal_addr);
  1561. iowrite8(0xaa, ioaddr->nsect_addr);
  1562. iowrite8(0x55, ioaddr->lbal_addr);
  1563. iowrite8(0x55, ioaddr->nsect_addr);
  1564. iowrite8(0xaa, ioaddr->lbal_addr);
  1565. nsect = ioread8(ioaddr->nsect_addr);
  1566. lbal = ioread8(ioaddr->lbal_addr);
  1567. if ((nsect == 0x55) && (lbal == 0xaa))
  1568. return 1; /* we found a device */
  1569. return 0; /* nothing found */
  1570. }
  1571. /**
  1572. * ata_sff_dev_classify - Parse returned ATA device signature
  1573. * @dev: ATA device to classify (starting at zero)
  1574. * @present: device seems present
  1575. * @r_err: Value of error register on completion
  1576. *
  1577. * After an event -- SRST, E.D.D., or SATA COMRESET -- occurs,
  1578. * an ATA/ATAPI-defined set of values is placed in the ATA
  1579. * shadow registers, indicating the results of device detection
  1580. * and diagnostics.
  1581. *
  1582. * Select the ATA device, and read the values from the ATA shadow
  1583. * registers. Then parse according to the Error register value,
  1584. * and the spec-defined values examined by ata_dev_classify().
  1585. *
  1586. * LOCKING:
  1587. * caller.
  1588. *
  1589. * RETURNS:
  1590. * Device type - %ATA_DEV_ATA, %ATA_DEV_ATAPI or %ATA_DEV_NONE.
  1591. */
  1592. unsigned int ata_sff_dev_classify(struct ata_device *dev, int present,
  1593. u8 *r_err)
  1594. {
  1595. struct ata_port *ap = dev->link->ap;
  1596. struct ata_taskfile tf;
  1597. unsigned int class;
  1598. u8 err;
  1599. ap->ops->sff_dev_select(ap, dev->devno);
  1600. memset(&tf, 0, sizeof(tf));
  1601. ap->ops->sff_tf_read(ap, &tf);
  1602. err = tf.feature;
  1603. if (r_err)
  1604. *r_err = err;
  1605. /* see if device passed diags: continue and warn later */
  1606. if (err == 0)
  1607. /* diagnostic fail : do nothing _YET_ */
  1608. dev->horkage |= ATA_HORKAGE_DIAGNOSTIC;
  1609. else if (err == 1)
  1610. /* do nothing */ ;
  1611. else if ((dev->devno == 0) && (err == 0x81))
  1612. /* do nothing */ ;
  1613. else
  1614. return ATA_DEV_NONE;
  1615. /* determine if device is ATA or ATAPI */
  1616. class = ata_dev_classify(&tf);
  1617. if (class == ATA_DEV_UNKNOWN) {
  1618. /* If the device failed diagnostic, it's likely to
  1619. * have reported incorrect device signature too.
  1620. * Assume ATA device if the device seems present but
  1621. * device signature is invalid with diagnostic
  1622. * failure.
  1623. */
  1624. if (present && (dev->horkage & ATA_HORKAGE_DIAGNOSTIC))
  1625. class = ATA_DEV_ATA;
  1626. else
  1627. class = ATA_DEV_NONE;
  1628. } else if ((class == ATA_DEV_ATA) &&
  1629. (ap->ops->sff_check_status(ap) == 0))
  1630. class = ATA_DEV_NONE;
  1631. return class;
  1632. }
  1633. EXPORT_SYMBOL_GPL(ata_sff_dev_classify);
  1634. /**
  1635. * ata_sff_wait_after_reset - wait for devices to become ready after reset
  1636. * @link: SFF link which is just reset
  1637. * @devmask: mask of present devices
  1638. * @deadline: deadline jiffies for the operation
  1639. *
  1640. * Wait devices attached to SFF @link to become ready after
  1641. * reset. It contains preceding 150ms wait to avoid accessing TF
  1642. * status register too early.
  1643. *
  1644. * LOCKING:
  1645. * Kernel thread context (may sleep).
  1646. *
  1647. * RETURNS:
  1648. * 0 on success, -ENODEV if some or all of devices in @devmask
  1649. * don't seem to exist. -errno on other errors.
  1650. */
  1651. int ata_sff_wait_after_reset(struct ata_link *link, unsigned int devmask,
  1652. unsigned long deadline)
  1653. {
  1654. struct ata_port *ap = link->ap;
  1655. struct ata_ioports *ioaddr = &ap->ioaddr;
  1656. unsigned int dev0 = devmask & (1 << 0);
  1657. unsigned int dev1 = devmask & (1 << 1);
  1658. int rc, ret = 0;
  1659. ata_msleep(ap, ATA_WAIT_AFTER_RESET);
  1660. /* always check readiness of the master device */
  1661. rc = ata_sff_wait_ready(link, deadline);
  1662. /* -ENODEV means the odd clown forgot the D7 pulldown resistor
  1663. * and TF status is 0xff, bail out on it too.
  1664. */
  1665. if (rc)
  1666. return rc;
  1667. /* if device 1 was found in ata_devchk, wait for register
  1668. * access briefly, then wait for BSY to clear.
  1669. */
  1670. if (dev1) {
  1671. int i;
  1672. ap->ops->sff_dev_select(ap, 1);
  1673. /* Wait for register access. Some ATAPI devices fail
  1674. * to set nsect/lbal after reset, so don't waste too
  1675. * much time on it. We're gonna wait for !BSY anyway.
  1676. */
  1677. for (i = 0; i < 2; i++) {
  1678. u8 nsect, lbal;
  1679. nsect = ioread8(ioaddr->nsect_addr);
  1680. lbal = ioread8(ioaddr->lbal_addr);
  1681. if ((nsect == 1) && (lbal == 1))
  1682. break;
  1683. ata_msleep(ap, 50); /* give drive a breather */
  1684. }
  1685. rc = ata_sff_wait_ready(link, deadline);
  1686. if (rc) {
  1687. if (rc != -ENODEV)
  1688. return rc;
  1689. ret = rc;
  1690. }
  1691. }
  1692. /* is all this really necessary? */
  1693. ap->ops->sff_dev_select(ap, 0);
  1694. if (dev1)
  1695. ap->ops->sff_dev_select(ap, 1);
  1696. if (dev0)
  1697. ap->ops->sff_dev_select(ap, 0);
  1698. return ret;
  1699. }
  1700. EXPORT_SYMBOL_GPL(ata_sff_wait_after_reset);
  1701. static int ata_bus_softreset(struct ata_port *ap, unsigned int devmask,
  1702. unsigned long deadline)
  1703. {
  1704. struct ata_ioports *ioaddr = &ap->ioaddr;
  1705. DPRINTK("ata%u: bus reset via SRST\n", ap->print_id);
  1706. if (ap->ioaddr.ctl_addr) {
  1707. /* software reset. causes dev0 to be selected */
  1708. iowrite8(ap->ctl, ioaddr->ctl_addr);
  1709. udelay(20); /* FIXME: flush */
  1710. iowrite8(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
  1711. udelay(20); /* FIXME: flush */
  1712. iowrite8(ap->ctl, ioaddr->ctl_addr);
  1713. ap->last_ctl = ap->ctl;
  1714. }
  1715. /* wait the port to become ready */
  1716. return ata_sff_wait_after_reset(&ap->link, devmask, deadline);
  1717. }
  1718. /**
  1719. * ata_sff_softreset - reset host port via ATA SRST
  1720. * @link: ATA link to reset
  1721. * @classes: resulting classes of attached devices
  1722. * @deadline: deadline jiffies for the operation
  1723. *
  1724. * Reset host port using ATA SRST.
  1725. *
  1726. * LOCKING:
  1727. * Kernel thread context (may sleep)
  1728. *
  1729. * RETURNS:
  1730. * 0 on success, -errno otherwise.
  1731. */
  1732. int ata_sff_softreset(struct ata_link *link, unsigned int *classes,
  1733. unsigned long deadline)
  1734. {
  1735. struct ata_port *ap = link->ap;
  1736. unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
  1737. unsigned int devmask = 0;
  1738. int rc;
  1739. u8 err;
  1740. DPRINTK("ENTER\n");
  1741. /* determine if device 0/1 are present */
  1742. if (ata_devchk(ap, 0))
  1743. devmask |= (1 << 0);
  1744. if (slave_possible && ata_devchk(ap, 1))
  1745. devmask |= (1 << 1);
  1746. /* select device 0 again */
  1747. ap->ops->sff_dev_select(ap, 0);
  1748. /* issue bus reset */
  1749. DPRINTK("about to softreset, devmask=%x\n", devmask);
  1750. rc = ata_bus_softreset(ap, devmask, deadline);
  1751. /* if link is occupied, -ENODEV too is an error */
  1752. if (rc && (rc != -ENODEV || sata_scr_valid(link))) {
  1753. ata_link_err(link, "SRST failed (errno=%d)\n", rc);
  1754. return rc;
  1755. }
  1756. /* determine by signature whether we have ATA or ATAPI devices */
  1757. classes[0] = ata_sff_dev_classify(&link->device[0],
  1758. devmask & (1 << 0), &err);
  1759. if (slave_possible && err != 0x81)
  1760. classes[1] = ata_sff_dev_classify(&link->device[1],
  1761. devmask & (1 << 1), &err);
  1762. DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]);
  1763. return 0;
  1764. }
  1765. EXPORT_SYMBOL_GPL(ata_sff_softreset);
  1766. /**
  1767. * sata_sff_hardreset - reset host port via SATA phy reset
  1768. * @link: link to reset
  1769. * @class: resulting class of attached device
  1770. * @deadline: deadline jiffies for the operation
  1771. *
  1772. * SATA phy-reset host port using DET bits of SControl register,
  1773. * wait for !BSY and classify the attached device.
  1774. *
  1775. * LOCKING:
  1776. * Kernel thread context (may sleep)
  1777. *
  1778. * RETURNS:
  1779. * 0 on success, -errno otherwise.
  1780. */
  1781. int sata_sff_hardreset(struct ata_link *link, unsigned int *class,
  1782. unsigned long deadline)
  1783. {
  1784. struct ata_eh_context *ehc = &link->eh_context;
  1785. const unsigned long *timing = sata_ehc_deb_timing(ehc);
  1786. bool online;
  1787. int rc;
  1788. rc = sata_link_hardreset(link, timing, deadline, &online,
  1789. ata_sff_check_ready);
  1790. if (online)
  1791. *class = ata_sff_dev_classify(link->device, 1, NULL);
  1792. DPRINTK("EXIT, class=%u\n", *class);
  1793. return rc;
  1794. }
  1795. EXPORT_SYMBOL_GPL(sata_sff_hardreset);
  1796. /**
  1797. * ata_sff_postreset - SFF postreset callback
  1798. * @link: the target SFF ata_link
  1799. * @classes: classes of attached devices
  1800. *
  1801. * This function is invoked after a successful reset. It first
  1802. * calls ata_std_postreset() and performs SFF specific postreset
  1803. * processing.
  1804. *
  1805. * LOCKING:
  1806. * Kernel thread context (may sleep)
  1807. */
  1808. void ata_sff_postreset(struct ata_link *link, unsigned int *classes)
  1809. {
  1810. struct ata_port *ap = link->ap;
  1811. ata_std_postreset(link, classes);
  1812. /* is double-select really necessary? */
  1813. if (classes[0] != ATA_DEV_NONE)
  1814. ap->ops->sff_dev_select(ap, 1);
  1815. if (classes[1] != ATA_DEV_NONE)
  1816. ap->ops->sff_dev_select(ap, 0);
  1817. /* bail out if no device is present */
  1818. if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
  1819. DPRINTK("EXIT, no device\n");
  1820. return;
  1821. }
  1822. /* set up device control */
  1823. if (ap->ops->sff_set_devctl || ap->ioaddr.ctl_addr) {
  1824. ata_sff_set_devctl(ap, ap->ctl);
  1825. ap->last_ctl = ap->ctl;
  1826. }
  1827. }
  1828. EXPORT_SYMBOL_GPL(ata_sff_postreset);
  1829. /**
  1830. * ata_sff_drain_fifo - Stock FIFO drain logic for SFF controllers
  1831. * @qc: command
  1832. *
  1833. * Drain the FIFO and device of any stuck data following a command
  1834. * failing to complete. In some cases this is necessary before a
  1835. * reset will recover the device.
  1836. *
  1837. */
  1838. void ata_sff_drain_fifo(struct ata_queued_cmd *qc)
  1839. {
  1840. int count;
  1841. struct ata_port *ap;
  1842. /* We only need to flush incoming data when a command was running */
  1843. if (qc == NULL || qc->dma_dir == DMA_TO_DEVICE)
  1844. return;
  1845. ap = qc->ap;
  1846. /* Drain up to 64K of data before we give up this recovery method */
  1847. for (count = 0; (ap->ops->sff_check_status(ap) & ATA_DRQ)
  1848. && count < 65536; count += 2)
  1849. ioread16(ap->ioaddr.data_addr);
  1850. /* Can become DEBUG later */
  1851. if (count)
  1852. ata_port_dbg(ap, "drained %d bytes to clear DRQ\n", count);
  1853. }
  1854. EXPORT_SYMBOL_GPL(ata_sff_drain_fifo);
  1855. /**
  1856. * ata_sff_error_handler - Stock error handler for SFF controller
  1857. * @ap: port to handle error for
  1858. *
  1859. * Stock error handler for SFF controller. It can handle both
  1860. * PATA and SATA controllers. Many controllers should be able to
  1861. * use this EH as-is or with some added handling before and
  1862. * after.
  1863. *
  1864. * LOCKING:
  1865. * Kernel thread context (may sleep)
  1866. */
  1867. void ata_sff_error_handler(struct ata_port *ap)
  1868. {
  1869. ata_reset_fn_t softreset = ap->ops->softreset;
  1870. ata_reset_fn_t hardreset = ap->ops->hardreset;
  1871. struct ata_queued_cmd *qc;
  1872. unsigned long flags;
  1873. qc = __ata_qc_from_tag(ap, ap->link.active_tag);
  1874. if (qc && !(qc->flags & ATA_QCFLAG_FAILED))
  1875. qc = NULL;
  1876. spin_lock_irqsave(ap->lock, flags);
  1877. /*
  1878. * We *MUST* do FIFO draining before we issue a reset as
  1879. * several devices helpfully clear their internal state and
  1880. * will lock solid if we touch the data port post reset. Pass
  1881. * qc in case anyone wants to do different PIO/DMA recovery or
  1882. * has per command fixups
  1883. */
  1884. if (ap->ops->sff_drain_fifo)
  1885. ap->ops->sff_drain_fifo(qc);
  1886. spin_unlock_irqrestore(ap->lock, flags);
  1887. /* ignore built-in hardresets if SCR access is not available */
  1888. if ((hardreset == sata_std_hardreset ||
  1889. hardreset == sata_sff_hardreset) && !sata_scr_valid(&ap->link))
  1890. hardreset = NULL;
  1891. ata_do_eh(ap, ap->ops->prereset, softreset, hardreset,
  1892. ap->ops->postreset);
  1893. }
  1894. EXPORT_SYMBOL_GPL(ata_sff_error_handler);
  1895. /**
  1896. * ata_sff_std_ports - initialize ioaddr with standard port offsets.
  1897. * @ioaddr: IO address structure to be initialized
  1898. *
  1899. * Utility function which initializes data_addr, error_addr,
  1900. * feature_addr, nsect_addr, lbal_addr, lbam_addr, lbah_addr,
  1901. * device_addr, status_addr, and command_addr to standard offsets
  1902. * relative to cmd_addr.
  1903. *
  1904. * Does not set ctl_addr, altstatus_addr, bmdma_addr, or scr_addr.
  1905. */
  1906. void ata_sff_std_ports(struct ata_ioports *ioaddr)
  1907. {
  1908. ioaddr->data_addr = ioaddr->cmd_addr + ATA_REG_DATA;
  1909. ioaddr->error_addr = ioaddr->cmd_addr + ATA_REG_ERR;
  1910. ioaddr->feature_addr = ioaddr->cmd_addr + ATA_REG_FEATURE;
  1911. ioaddr->nsect_addr = ioaddr->cmd_addr + ATA_REG_NSECT;
  1912. ioaddr->lbal_addr = ioaddr->cmd_addr + ATA_REG_LBAL;
  1913. ioaddr->lbam_addr = ioaddr->cmd_addr + ATA_REG_LBAM;
  1914. ioaddr->lbah_addr = ioaddr->cmd_addr + ATA_REG_LBAH;
  1915. ioaddr->device_addr = ioaddr->cmd_addr + ATA_REG_DEVICE;
  1916. ioaddr->status_addr = ioaddr->cmd_addr + ATA_REG_STATUS;
  1917. ioaddr->command_addr = ioaddr->cmd_addr + ATA_REG_CMD;
  1918. }
  1919. EXPORT_SYMBOL_GPL(ata_sff_std_ports);
  1920. #ifdef CONFIG_PCI
  1921. static int ata_resources_present(struct pci_dev *pdev, int port)
  1922. {
  1923. int i;
  1924. /* Check the PCI resources for this channel are enabled */
  1925. port = port * 2;
  1926. for (i = 0; i < 2; i++) {
  1927. if (pci_resource_start(pdev, port + i) == 0 ||
  1928. pci_resource_len(pdev, port + i) == 0)
  1929. return 0;
  1930. }
  1931. return 1;
  1932. }
  1933. /**
  1934. * ata_pci_sff_init_host - acquire native PCI ATA resources and init host
  1935. * @host: target ATA host
  1936. *
  1937. * Acquire native PCI ATA resources for @host and initialize the
  1938. * first two ports of @host accordingly. Ports marked dummy are
  1939. * skipped and allocation failure makes the port dummy.
  1940. *
  1941. * Note that native PCI resources are valid even for legacy hosts
  1942. * as we fix up pdev resources array early in boot, so this
  1943. * function can be used for both native and legacy SFF hosts.
  1944. *
  1945. * LOCKING:
  1946. * Inherited from calling layer (may sleep).
  1947. *
  1948. * RETURNS:
  1949. * 0 if at least one port is initialized, -ENODEV if no port is
  1950. * available.
  1951. */
  1952. int ata_pci_sff_init_host(struct ata_host *host)
  1953. {
  1954. struct device *gdev = host->dev;
  1955. struct pci_dev *pdev = to_pci_dev(gdev);
  1956. unsigned int mask = 0;
  1957. int i, rc;
  1958. /* request, iomap BARs and init port addresses accordingly */
  1959. for (i = 0; i < 2; i++) {
  1960. struct ata_port *ap = host->ports[i];
  1961. int base = i * 2;
  1962. void __iomem * const *iomap;
  1963. if (ata_port_is_dummy(ap))
  1964. continue;
  1965. /* Discard disabled ports. Some controllers show
  1966. * their unused channels this way. Disabled ports are
  1967. * made dummy.
  1968. */
  1969. if (!ata_resources_present(pdev, i)) {
  1970. ap->ops = &ata_dummy_port_ops;
  1971. continue;
  1972. }
  1973. rc = pcim_iomap_regions(pdev, 0x3 << base,
  1974. dev_driver_string(gdev));
  1975. if (rc) {
  1976. dev_warn(gdev,
  1977. "failed to request/iomap BARs for port %d (errno=%d)\n",
  1978. i, rc);
  1979. if (rc == -EBUSY)
  1980. pcim_pin_device(pdev);
  1981. ap->ops = &ata_dummy_port_ops;
  1982. continue;
  1983. }
  1984. host->iomap = iomap = pcim_iomap_table(pdev);
  1985. ap->ioaddr.cmd_addr = iomap[base];
  1986. ap->ioaddr.altstatus_addr =
  1987. ap->ioaddr.ctl_addr = (void __iomem *)
  1988. ((unsigned long)iomap[base + 1] | ATA_PCI_CTL_OFS);
  1989. ata_sff_std_ports(&ap->ioaddr);
  1990. ata_port_desc(ap, "cmd 0x%llx ctl 0x%llx",
  1991. (unsigned long long)pci_resource_start(pdev, base),
  1992. (unsigned long long)pci_resource_start(pdev, base + 1));
  1993. mask |= 1 << i;
  1994. }
  1995. if (!mask) {
  1996. dev_err(gdev, "no available native port\n");
  1997. return -ENODEV;
  1998. }
  1999. return 0;
  2000. }
  2001. EXPORT_SYMBOL_GPL(ata_pci_sff_init_host);
  2002. /**
  2003. * ata_pci_sff_prepare_host - helper to prepare PCI PIO-only SFF ATA host
  2004. * @pdev: target PCI device
  2005. * @ppi: array of port_info, must be enough for two ports
  2006. * @r_host: out argument for the initialized ATA host
  2007. *
  2008. * Helper to allocate PIO-only SFF ATA host for @pdev, acquire
  2009. * all PCI resources and initialize it accordingly in one go.
  2010. *
  2011. * LOCKING:
  2012. * Inherited from calling layer (may sleep).
  2013. *
  2014. * RETURNS:
  2015. * 0 on success, -errno otherwise.
  2016. */
  2017. int ata_pci_sff_prepare_host(struct pci_dev *pdev,
  2018. const struct ata_port_info * const *ppi,
  2019. struct ata_host **r_host)
  2020. {
  2021. struct ata_host *host;
  2022. int rc;
  2023. if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL))
  2024. return -ENOMEM;
  2025. host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
  2026. if (!host) {
  2027. dev_err(&pdev->dev, "failed to allocate ATA host\n");
  2028. rc = -ENOMEM;
  2029. goto err_out;
  2030. }
  2031. rc = ata_pci_sff_init_host(host);
  2032. if (rc)
  2033. goto err_out;
  2034. devres_remove_group(&pdev->dev, NULL);
  2035. *r_host = host;
  2036. return 0;
  2037. err_out:
  2038. devres_release_group(&pdev->dev, NULL);
  2039. return rc;
  2040. }
  2041. EXPORT_SYMBOL_GPL(ata_pci_sff_prepare_host);
  2042. /**
  2043. * ata_pci_sff_activate_host - start SFF host, request IRQ and register it
  2044. * @host: target SFF ATA host
  2045. * @irq_handler: irq_handler used when requesting IRQ(s)
  2046. * @sht: scsi_host_template to use when registering the host
  2047. *
  2048. * This is the counterpart of ata_host_activate() for SFF ATA
  2049. * hosts. This separate helper is necessary because SFF hosts
  2050. * use two separate interrupts in legacy mode.
  2051. *
  2052. * LOCKING:
  2053. * Inherited from calling layer (may sleep).
  2054. *
  2055. * RETURNS:
  2056. * 0 on success, -errno otherwise.
  2057. */
  2058. int ata_pci_sff_activate_host(struct ata_host *host,
  2059. irq_handler_t irq_handler,
  2060. struct scsi_host_template *sht)
  2061. {
  2062. struct device *dev = host->dev;
  2063. struct pci_dev *pdev = to_pci_dev(dev);
  2064. const char *drv_name = dev_driver_string(host->dev);
  2065. int legacy_mode = 0, rc;
  2066. rc = ata_host_start(host);
  2067. if (rc)
  2068. return rc;
  2069. if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
  2070. u8 tmp8, mask = 0;
  2071. /*
  2072. * ATA spec says we should use legacy mode when one
  2073. * port is in legacy mode, but disabled ports on some
  2074. * PCI hosts appear as fixed legacy ports, e.g SB600/700
  2075. * on which the secondary port is not wired, so
  2076. * ignore ports that are marked as 'dummy' during
  2077. * this check
  2078. */
  2079. pci_read_config_byte(pdev, PCI_CLASS_PROG, &tmp8);
  2080. if (!ata_port_is_dummy(host->ports[0]))
  2081. mask |= (1 << 0);
  2082. if (!ata_port_is_dummy(host->ports[1]))
  2083. mask |= (1 << 2);
  2084. if ((tmp8 & mask) != mask)
  2085. legacy_mode = 1;
  2086. }
  2087. if (!devres_open_group(dev, NULL, GFP_KERNEL))
  2088. return -ENOMEM;
  2089. if (!legacy_mode && pdev->irq) {
  2090. int i;
  2091. rc = devm_request_irq(dev, pdev->irq, irq_handler,
  2092. IRQF_SHARED, drv_name, host);
  2093. if (rc)
  2094. goto out;
  2095. for (i = 0; i < 2; i++) {
  2096. if (ata_port_is_dummy(host->ports[i]))
  2097. continue;
  2098. ata_port_desc(host->ports[i], "irq %d", pdev->irq);
  2099. }
  2100. } else if (legacy_mode) {
  2101. if (!ata_port_is_dummy(host->ports[0])) {
  2102. rc = devm_request_irq(dev, ATA_PRIMARY_IRQ(pdev),
  2103. irq_handler, IRQF_SHARED,
  2104. drv_name, host);
  2105. if (rc)
  2106. goto out;
  2107. ata_port_desc(host->ports[0], "irq %d",
  2108. ATA_PRIMARY_IRQ(pdev));
  2109. }
  2110. if (!ata_port_is_dummy(host->ports[1])) {
  2111. rc = devm_request_irq(dev, ATA_SECONDARY_IRQ(pdev),
  2112. irq_handler, IRQF_SHARED,
  2113. drv_name, host);
  2114. if (rc)
  2115. goto out;
  2116. ata_port_desc(host->ports[1], "irq %d",
  2117. ATA_SECONDARY_IRQ(pdev));
  2118. }
  2119. }
  2120. rc = ata_host_register(host, sht);
  2121. out:
  2122. if (rc == 0)
  2123. devres_remove_group(dev, NULL);
  2124. else
  2125. devres_release_group(dev, NULL);
  2126. return rc;
  2127. }
  2128. EXPORT_SYMBOL_GPL(ata_pci_sff_activate_host);
  2129. static const struct ata_port_info *ata_sff_find_valid_pi(
  2130. const struct ata_port_info * const *ppi)
  2131. {
  2132. int i;
  2133. /* look up the first valid port_info */
  2134. for (i = 0; i < 2 && ppi[i]; i++)
  2135. if (ppi[i]->port_ops != &ata_dummy_port_ops)
  2136. return ppi[i];
  2137. return NULL;
  2138. }
  2139. static int ata_pci_init_one(struct pci_dev *pdev,
  2140. const struct ata_port_info * const *ppi,
  2141. struct scsi_host_template *sht, void *host_priv,
  2142. int hflags, bool bmdma)
  2143. {
  2144. struct device *dev = &pdev->dev;
  2145. const struct ata_port_info *pi;
  2146. struct ata_host *host = NULL;
  2147. int rc;
  2148. DPRINTK("ENTER\n");
  2149. pi = ata_sff_find_valid_pi(ppi);
  2150. if (!pi) {
  2151. dev_err(&pdev->dev, "no valid port_info specified\n");
  2152. return -EINVAL;
  2153. }
  2154. if (!devres_open_group(dev, NULL, GFP_KERNEL))
  2155. return -ENOMEM;
  2156. rc = pcim_enable_device(pdev);
  2157. if (rc)
  2158. goto out;
  2159. #ifdef CONFIG_ATA_BMDMA
  2160. if (bmdma)
  2161. /* prepare and activate BMDMA host */
  2162. rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
  2163. else
  2164. #endif
  2165. /* prepare and activate SFF host */
  2166. rc = ata_pci_sff_prepare_host(pdev, ppi, &host);
  2167. if (rc)
  2168. goto out;
  2169. host->private_data = host_priv;
  2170. host->flags |= hflags;
  2171. #ifdef CONFIG_ATA_BMDMA
  2172. if (bmdma) {
  2173. pci_set_master(pdev);
  2174. rc = ata_pci_sff_activate_host(host, ata_bmdma_interrupt, sht);
  2175. } else
  2176. #endif
  2177. rc = ata_pci_sff_activate_host(host, ata_sff_interrupt, sht);
  2178. out:
  2179. if (rc == 0)
  2180. devres_remove_group(&pdev->dev, NULL);
  2181. else
  2182. devres_release_group(&pdev->dev, NULL);
  2183. return rc;
  2184. }
  2185. /**
  2186. * ata_pci_sff_init_one - Initialize/register PIO-only PCI IDE controller
  2187. * @pdev: Controller to be initialized
  2188. * @ppi: array of port_info, must be enough for two ports
  2189. * @sht: scsi_host_template to use when registering the host
  2190. * @host_priv: host private_data
  2191. * @hflag: host flags
  2192. *
  2193. * This is a helper function which can be called from a driver's
  2194. * xxx_init_one() probe function if the hardware uses traditional
  2195. * IDE taskfile registers and is PIO only.
  2196. *
  2197. * ASSUMPTION:
  2198. * Nobody makes a single channel controller that appears solely as
  2199. * the secondary legacy port on PCI.
  2200. *
  2201. * LOCKING:
  2202. * Inherited from PCI layer (may sleep).
  2203. *
  2204. * RETURNS:
  2205. * Zero on success, negative on errno-based value on error.
  2206. */
  2207. int ata_pci_sff_init_one(struct pci_dev *pdev,
  2208. const struct ata_port_info * const *ppi,
  2209. struct scsi_host_template *sht, void *host_priv, int hflag)
  2210. {
  2211. return ata_pci_init_one(pdev, ppi, sht, host_priv, hflag, 0);
  2212. }
  2213. EXPORT_SYMBOL_GPL(ata_pci_sff_init_one);
  2214. #endif /* CONFIG_PCI */
  2215. /*
  2216. * BMDMA support
  2217. */
  2218. #ifdef CONFIG_ATA_BMDMA
  2219. const struct ata_port_operations ata_bmdma_port_ops = {
  2220. .inherits = &ata_sff_port_ops,
  2221. .error_handler = ata_bmdma_error_handler,
  2222. .post_internal_cmd = ata_bmdma_post_internal_cmd,
  2223. .qc_prep = ata_bmdma_qc_prep,
  2224. .qc_issue = ata_bmdma_qc_issue,
  2225. .sff_irq_clear = ata_bmdma_irq_clear,
  2226. .bmdma_setup = ata_bmdma_setup,
  2227. .bmdma_start = ata_bmdma_start,
  2228. .bmdma_stop = ata_bmdma_stop,
  2229. .bmdma_status = ata_bmdma_status,
  2230. .port_start = ata_bmdma_port_start,
  2231. };
  2232. EXPORT_SYMBOL_GPL(ata_bmdma_port_ops);
  2233. const struct ata_port_operations ata_bmdma32_port_ops = {
  2234. .inherits = &ata_bmdma_port_ops,
  2235. .sff_data_xfer = ata_sff_data_xfer32,
  2236. .port_start = ata_bmdma_port_start32,
  2237. };
  2238. EXPORT_SYMBOL_GPL(ata_bmdma32_port_ops);
  2239. /**
  2240. * ata_bmdma_fill_sg - Fill PCI IDE PRD table
  2241. * @qc: Metadata associated with taskfile to be transferred
  2242. *
  2243. * Fill PCI IDE PRD (scatter-gather) table with segments
  2244. * associated with the current disk command.
  2245. *
  2246. * LOCKING:
  2247. * spin_lock_irqsave(host lock)
  2248. *
  2249. */
  2250. static void ata_bmdma_fill_sg(struct ata_queued_cmd *qc)
  2251. {
  2252. struct ata_port *ap = qc->ap;
  2253. struct ata_bmdma_prd *prd = ap->bmdma_prd;
  2254. struct scatterlist *sg;
  2255. unsigned int si, pi;
  2256. pi = 0;
  2257. for_each_sg(qc->sg, sg, qc->n_elem, si) {
  2258. u32 addr, offset;
  2259. u32 sg_len, len;
  2260. /* determine if physical DMA addr spans 64K boundary.
  2261. * Note h/w doesn't support 64-bit, so we unconditionally
  2262. * truncate dma_addr_t to u32.
  2263. */
  2264. addr = (u32) sg_dma_address(sg);
  2265. sg_len = sg_dma_len(sg);
  2266. while (sg_len) {
  2267. offset = addr & 0xffff;
  2268. len = sg_len;
  2269. if ((offset + sg_len) > 0x10000)
  2270. len = 0x10000 - offset;
  2271. prd[pi].addr = cpu_to_le32(addr);
  2272. prd[pi].flags_len = cpu_to_le32(len & 0xffff);
  2273. VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len);
  2274. pi++;
  2275. sg_len -= len;
  2276. addr += len;
  2277. }
  2278. }
  2279. prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
  2280. }
  2281. /**
  2282. * ata_bmdma_fill_sg_dumb - Fill PCI IDE PRD table
  2283. * @qc: Metadata associated with taskfile to be transferred
  2284. *
  2285. * Fill PCI IDE PRD (scatter-gather) table with segments
  2286. * associated with the current disk command. Perform the fill
  2287. * so that we avoid writing any length 64K records for
  2288. * controllers that don't follow the spec.
  2289. *
  2290. * LOCKING:
  2291. * spin_lock_irqsave(host lock)
  2292. *
  2293. */
  2294. static void ata_bmdma_fill_sg_dumb(struct ata_queued_cmd *qc)
  2295. {
  2296. struct ata_port *ap = qc->ap;
  2297. struct ata_bmdma_prd *prd = ap->bmdma_prd;
  2298. struct scatterlist *sg;
  2299. unsigned int si, pi;
  2300. pi = 0;
  2301. for_each_sg(qc->sg, sg, qc->n_elem, si) {
  2302. u32 addr, offset;
  2303. u32 sg_len, len, blen;
  2304. /* determine if physical DMA addr spans 64K boundary.
  2305. * Note h/w doesn't support 64-bit, so we unconditionally
  2306. * truncate dma_addr_t to u32.
  2307. */
  2308. addr = (u32) sg_dma_address(sg);
  2309. sg_len = sg_dma_len(sg);
  2310. while (sg_len) {
  2311. offset = addr & 0xffff;
  2312. len = sg_len;
  2313. if ((offset + sg_len) > 0x10000)
  2314. len = 0x10000 - offset;
  2315. blen = len & 0xffff;
  2316. prd[pi].addr = cpu_to_le32(addr);
  2317. if (blen == 0) {
  2318. /* Some PATA chipsets like the CS5530 can't
  2319. cope with 0x0000 meaning 64K as the spec
  2320. says */
  2321. prd[pi].flags_len = cpu_to_le32(0x8000);
  2322. blen = 0x8000;
  2323. prd[++pi].addr = cpu_to_le32(addr + 0x8000);
  2324. }
  2325. prd[pi].flags_len = cpu_to_le32(blen);
  2326. VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len);
  2327. pi++;
  2328. sg_len -= len;
  2329. addr += len;
  2330. }
  2331. }
  2332. prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
  2333. }
  2334. /**
  2335. * ata_bmdma_qc_prep - Prepare taskfile for submission
  2336. * @qc: Metadata associated with taskfile to be prepared
  2337. *
  2338. * Prepare ATA taskfile for submission.
  2339. *
  2340. * LOCKING:
  2341. * spin_lock_irqsave(host lock)
  2342. */
  2343. enum ata_completion_errors ata_bmdma_qc_prep(struct ata_queued_cmd *qc)
  2344. {
  2345. if (!(qc->flags & ATA_QCFLAG_DMAMAP))
  2346. return AC_ERR_OK;
  2347. ata_bmdma_fill_sg(qc);
  2348. return AC_ERR_OK;
  2349. }
  2350. EXPORT_SYMBOL_GPL(ata_bmdma_qc_prep);
  2351. /**
  2352. * ata_bmdma_dumb_qc_prep - Prepare taskfile for submission
  2353. * @qc: Metadata associated with taskfile to be prepared
  2354. *
  2355. * Prepare ATA taskfile for submission.
  2356. *
  2357. * LOCKING:
  2358. * spin_lock_irqsave(host lock)
  2359. */
  2360. enum ata_completion_errors ata_bmdma_dumb_qc_prep(struct ata_queued_cmd *qc)
  2361. {
  2362. if (!(qc->flags & ATA_QCFLAG_DMAMAP))
  2363. return AC_ERR_OK;
  2364. ata_bmdma_fill_sg_dumb(qc);
  2365. return AC_ERR_OK;
  2366. }
  2367. EXPORT_SYMBOL_GPL(ata_bmdma_dumb_qc_prep);
  2368. /**
  2369. * ata_bmdma_qc_issue - issue taskfile to a BMDMA controller
  2370. * @qc: command to issue to device
  2371. *
  2372. * This function issues a PIO, NODATA or DMA command to a
  2373. * SFF/BMDMA controller. PIO and NODATA are handled by
  2374. * ata_sff_qc_issue().
  2375. *
  2376. * LOCKING:
  2377. * spin_lock_irqsave(host lock)
  2378. *
  2379. * RETURNS:
  2380. * Zero on success, AC_ERR_* mask on failure
  2381. */
  2382. unsigned int ata_bmdma_qc_issue(struct ata_queued_cmd *qc)
  2383. {
  2384. struct ata_port *ap = qc->ap;
  2385. struct ata_link *link = qc->dev->link;
  2386. /* defer PIO handling to sff_qc_issue */
  2387. if (!ata_is_dma(qc->tf.protocol))
  2388. return ata_sff_qc_issue(qc);
  2389. /* select the device */
  2390. ata_dev_select(ap, qc->dev->devno, 1, 0);
  2391. /* start the command */
  2392. switch (qc->tf.protocol) {
  2393. case ATA_PROT_DMA:
  2394. WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING);
  2395. ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */
  2396. ap->ops->bmdma_setup(qc); /* set up bmdma */
  2397. ap->ops->bmdma_start(qc); /* initiate bmdma */
  2398. ap->hsm_task_state = HSM_ST_LAST;
  2399. break;
  2400. case ATAPI_PROT_DMA:
  2401. WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING);
  2402. ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */
  2403. ap->ops->bmdma_setup(qc); /* set up bmdma */
  2404. ap->hsm_task_state = HSM_ST_FIRST;
  2405. /* send cdb by polling if no cdb interrupt */
  2406. if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
  2407. ata_sff_queue_pio_task(link, 0);
  2408. break;
  2409. default:
  2410. WARN_ON(1);
  2411. return AC_ERR_SYSTEM;
  2412. }
  2413. return 0;
  2414. }
  2415. EXPORT_SYMBOL_GPL(ata_bmdma_qc_issue);
  2416. /**
  2417. * ata_bmdma_port_intr - Handle BMDMA port interrupt
  2418. * @ap: Port on which interrupt arrived (possibly...)
  2419. * @qc: Taskfile currently active in engine
  2420. *
  2421. * Handle port interrupt for given queued command.
  2422. *
  2423. * LOCKING:
  2424. * spin_lock_irqsave(host lock)
  2425. *
  2426. * RETURNS:
  2427. * One if interrupt was handled, zero if not (shared irq).
  2428. */
  2429. unsigned int ata_bmdma_port_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
  2430. {
  2431. struct ata_eh_info *ehi = &ap->link.eh_info;
  2432. u8 host_stat = 0;
  2433. bool bmdma_stopped = false;
  2434. unsigned int handled;
  2435. if (ap->hsm_task_state == HSM_ST_LAST && ata_is_dma(qc->tf.protocol)) {
  2436. /* check status of DMA engine */
  2437. host_stat = ap->ops->bmdma_status(ap);
  2438. VPRINTK("ata%u: host_stat 0x%X\n", ap->print_id, host_stat);
  2439. /* if it's not our irq... */
  2440. if (!(host_stat & ATA_DMA_INTR))
  2441. return ata_sff_idle_irq(ap);
  2442. /* before we do anything else, clear DMA-Start bit */
  2443. ap->ops->bmdma_stop(qc);
  2444. bmdma_stopped = true;
  2445. if (unlikely(host_stat & ATA_DMA_ERR)) {
  2446. /* error when transferring data to/from memory */
  2447. qc->err_mask |= AC_ERR_HOST_BUS;
  2448. ap->hsm_task_state = HSM_ST_ERR;
  2449. }
  2450. }
  2451. handled = __ata_sff_port_intr(ap, qc, bmdma_stopped);
  2452. if (unlikely(qc->err_mask) && ata_is_dma(qc->tf.protocol))
  2453. ata_ehi_push_desc(ehi, "BMDMA stat 0x%x", host_stat);
  2454. return handled;
  2455. }
  2456. EXPORT_SYMBOL_GPL(ata_bmdma_port_intr);
  2457. /**
  2458. * ata_bmdma_interrupt - Default BMDMA ATA host interrupt handler
  2459. * @irq: irq line (unused)
  2460. * @dev_instance: pointer to our ata_host information structure
  2461. *
  2462. * Default interrupt handler for PCI IDE devices. Calls
  2463. * ata_bmdma_port_intr() for each port that is not disabled.
  2464. *
  2465. * LOCKING:
  2466. * Obtains host lock during operation.
  2467. *
  2468. * RETURNS:
  2469. * IRQ_NONE or IRQ_HANDLED.
  2470. */
  2471. irqreturn_t ata_bmdma_interrupt(int irq, void *dev_instance)
  2472. {
  2473. return __ata_sff_interrupt(irq, dev_instance, ata_bmdma_port_intr);
  2474. }
  2475. EXPORT_SYMBOL_GPL(ata_bmdma_interrupt);
  2476. /**
  2477. * ata_bmdma_error_handler - Stock error handler for BMDMA controller
  2478. * @ap: port to handle error for
  2479. *
  2480. * Stock error handler for BMDMA controller. It can handle both
  2481. * PATA and SATA controllers. Most BMDMA controllers should be
  2482. * able to use this EH as-is or with some added handling before
  2483. * and after.
  2484. *
  2485. * LOCKING:
  2486. * Kernel thread context (may sleep)
  2487. */
  2488. void ata_bmdma_error_handler(struct ata_port *ap)
  2489. {
  2490. struct ata_queued_cmd *qc;
  2491. unsigned long flags;
  2492. bool thaw = false;
  2493. qc = __ata_qc_from_tag(ap, ap->link.active_tag);
  2494. if (qc && !(qc->flags & ATA_QCFLAG_FAILED))
  2495. qc = NULL;
  2496. /* reset PIO HSM and stop DMA engine */
  2497. spin_lock_irqsave(ap->lock, flags);
  2498. if (qc && ata_is_dma(qc->tf.protocol)) {
  2499. u8 host_stat;
  2500. host_stat = ap->ops->bmdma_status(ap);
  2501. /* BMDMA controllers indicate host bus error by
  2502. * setting DMA_ERR bit and timing out. As it wasn't
  2503. * really a timeout event, adjust error mask and
  2504. * cancel frozen state.
  2505. */
  2506. if (qc->err_mask == AC_ERR_TIMEOUT && (host_stat & ATA_DMA_ERR)) {
  2507. qc->err_mask = AC_ERR_HOST_BUS;
  2508. thaw = true;
  2509. }
  2510. ap->ops->bmdma_stop(qc);
  2511. /* if we're gonna thaw, make sure IRQ is clear */
  2512. if (thaw) {
  2513. ap->ops->sff_check_status(ap);
  2514. if (ap->ops->sff_irq_clear)
  2515. ap->ops->sff_irq_clear(ap);
  2516. }
  2517. }
  2518. spin_unlock_irqrestore(ap->lock, flags);
  2519. if (thaw)
  2520. ata_eh_thaw_port(ap);
  2521. ata_sff_error_handler(ap);
  2522. }
  2523. EXPORT_SYMBOL_GPL(ata_bmdma_error_handler);
  2524. /**
  2525. * ata_bmdma_post_internal_cmd - Stock post_internal_cmd for BMDMA
  2526. * @qc: internal command to clean up
  2527. *
  2528. * LOCKING:
  2529. * Kernel thread context (may sleep)
  2530. */
  2531. void ata_bmdma_post_internal_cmd(struct ata_queued_cmd *qc)
  2532. {
  2533. struct ata_port *ap = qc->ap;
  2534. unsigned long flags;
  2535. if (ata_is_dma(qc->tf.protocol)) {
  2536. spin_lock_irqsave(ap->lock, flags);
  2537. ap->ops->bmdma_stop(qc);
  2538. spin_unlock_irqrestore(ap->lock, flags);
  2539. }
  2540. }
  2541. EXPORT_SYMBOL_GPL(ata_bmdma_post_internal_cmd);
  2542. /**
  2543. * ata_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt.
  2544. * @ap: Port associated with this ATA transaction.
  2545. *
  2546. * Clear interrupt and error flags in DMA status register.
  2547. *
  2548. * May be used as the irq_clear() entry in ata_port_operations.
  2549. *
  2550. * LOCKING:
  2551. * spin_lock_irqsave(host lock)
  2552. */
  2553. void ata_bmdma_irq_clear(struct ata_port *ap)
  2554. {
  2555. void __iomem *mmio = ap->ioaddr.bmdma_addr;
  2556. if (!mmio)
  2557. return;
  2558. iowrite8(ioread8(mmio + ATA_DMA_STATUS), mmio + ATA_DMA_STATUS);
  2559. }
  2560. EXPORT_SYMBOL_GPL(ata_bmdma_irq_clear);
  2561. /**
  2562. * ata_bmdma_setup - Set up PCI IDE BMDMA transaction
  2563. * @qc: Info associated with this ATA transaction.
  2564. *
  2565. * LOCKING:
  2566. * spin_lock_irqsave(host lock)
  2567. */
  2568. void ata_bmdma_setup(struct ata_queued_cmd *qc)
  2569. {
  2570. struct ata_port *ap = qc->ap;
  2571. unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
  2572. u8 dmactl;
  2573. /* load PRD table addr. */
  2574. mb(); /* make sure PRD table writes are visible to controller */
  2575. iowrite32(ap->bmdma_prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
  2576. /* specify data direction, triple-check start bit is clear */
  2577. dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
  2578. dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
  2579. if (!rw)
  2580. dmactl |= ATA_DMA_WR;
  2581. iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
  2582. /* issue r/w command */
  2583. ap->ops->sff_exec_command(ap, &qc->tf);
  2584. }
  2585. EXPORT_SYMBOL_GPL(ata_bmdma_setup);
  2586. /**
  2587. * ata_bmdma_start - Start a PCI IDE BMDMA transaction
  2588. * @qc: Info associated with this ATA transaction.
  2589. *
  2590. * LOCKING:
  2591. * spin_lock_irqsave(host lock)
  2592. */
  2593. void ata_bmdma_start(struct ata_queued_cmd *qc)
  2594. {
  2595. struct ata_port *ap = qc->ap;
  2596. u8 dmactl;
  2597. /* start host DMA transaction */
  2598. dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
  2599. iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
  2600. /* Strictly, one may wish to issue an ioread8() here, to
  2601. * flush the mmio write. However, control also passes
  2602. * to the hardware at this point, and it will interrupt
  2603. * us when we are to resume control. So, in effect,
  2604. * we don't care when the mmio write flushes.
  2605. * Further, a read of the DMA status register _immediately_
  2606. * following the write may not be what certain flaky hardware
  2607. * is expected, so I think it is best to not add a readb()
  2608. * without first all the MMIO ATA cards/mobos.
  2609. * Or maybe I'm just being paranoid.
  2610. *
  2611. * FIXME: The posting of this write means I/O starts are
  2612. * unnecessarily delayed for MMIO
  2613. */
  2614. }
  2615. EXPORT_SYMBOL_GPL(ata_bmdma_start);
  2616. /**
  2617. * ata_bmdma_stop - Stop PCI IDE BMDMA transfer
  2618. * @qc: Command we are ending DMA for
  2619. *
  2620. * Clears the ATA_DMA_START flag in the dma control register
  2621. *
  2622. * May be used as the bmdma_stop() entry in ata_port_operations.
  2623. *
  2624. * LOCKING:
  2625. * spin_lock_irqsave(host lock)
  2626. */
  2627. void ata_bmdma_stop(struct ata_queued_cmd *qc)
  2628. {
  2629. struct ata_port *ap = qc->ap;
  2630. void __iomem *mmio = ap->ioaddr.bmdma_addr;
  2631. /* clear start/stop bit */
  2632. iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ATA_DMA_START,
  2633. mmio + ATA_DMA_CMD);
  2634. /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
  2635. ata_sff_dma_pause(ap);
  2636. }
  2637. EXPORT_SYMBOL_GPL(ata_bmdma_stop);
  2638. /**
  2639. * ata_bmdma_status - Read PCI IDE BMDMA status
  2640. * @ap: Port associated with this ATA transaction.
  2641. *
  2642. * Read and return BMDMA status register.
  2643. *
  2644. * May be used as the bmdma_status() entry in ata_port_operations.
  2645. *
  2646. * LOCKING:
  2647. * spin_lock_irqsave(host lock)
  2648. */
  2649. u8 ata_bmdma_status(struct ata_port *ap)
  2650. {
  2651. return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
  2652. }
  2653. EXPORT_SYMBOL_GPL(ata_bmdma_status);
  2654. /**
  2655. * ata_bmdma_port_start - Set port up for bmdma.
  2656. * @ap: Port to initialize
  2657. *
  2658. * Called just after data structures for each port are
  2659. * initialized. Allocates space for PRD table.
  2660. *
  2661. * May be used as the port_start() entry in ata_port_operations.
  2662. *
  2663. * LOCKING:
  2664. * Inherited from caller.
  2665. */
  2666. int ata_bmdma_port_start(struct ata_port *ap)
  2667. {
  2668. if (ap->mwdma_mask || ap->udma_mask) {
  2669. ap->bmdma_prd =
  2670. dmam_alloc_coherent(ap->host->dev, ATA_PRD_TBL_SZ,
  2671. &ap->bmdma_prd_dma, GFP_KERNEL);
  2672. if (!ap->bmdma_prd)
  2673. return -ENOMEM;
  2674. }
  2675. return 0;
  2676. }
  2677. EXPORT_SYMBOL_GPL(ata_bmdma_port_start);
  2678. /**
  2679. * ata_bmdma_port_start32 - Set port up for dma.
  2680. * @ap: Port to initialize
  2681. *
  2682. * Called just after data structures for each port are
  2683. * initialized. Enables 32bit PIO and allocates space for PRD
  2684. * table.
  2685. *
  2686. * May be used as the port_start() entry in ata_port_operations for
  2687. * devices that are capable of 32bit PIO.
  2688. *
  2689. * LOCKING:
  2690. * Inherited from caller.
  2691. */
  2692. int ata_bmdma_port_start32(struct ata_port *ap)
  2693. {
  2694. ap->pflags |= ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE;
  2695. return ata_bmdma_port_start(ap);
  2696. }
  2697. EXPORT_SYMBOL_GPL(ata_bmdma_port_start32);
  2698. #ifdef CONFIG_PCI
  2699. /**
  2700. * ata_pci_bmdma_clear_simplex - attempt to kick device out of simplex
  2701. * @pdev: PCI device
  2702. *
  2703. * Some PCI ATA devices report simplex mode but in fact can be told to
  2704. * enter non simplex mode. This implements the necessary logic to
  2705. * perform the task on such devices. Calling it on other devices will
  2706. * have -undefined- behaviour.
  2707. */
  2708. int ata_pci_bmdma_clear_simplex(struct pci_dev *pdev)
  2709. {
  2710. unsigned long bmdma = pci_resource_start(pdev, 4);
  2711. u8 simplex;
  2712. if (bmdma == 0)
  2713. return -ENOENT;
  2714. simplex = inb(bmdma + 0x02);
  2715. outb(simplex & 0x60, bmdma + 0x02);
  2716. simplex = inb(bmdma + 0x02);
  2717. if (simplex & 0x80)
  2718. return -EOPNOTSUPP;
  2719. return 0;
  2720. }
  2721. EXPORT_SYMBOL_GPL(ata_pci_bmdma_clear_simplex);
  2722. static void ata_bmdma_nodma(struct ata_host *host, const char *reason)
  2723. {
  2724. int i;
  2725. dev_err(host->dev, "BMDMA: %s, falling back to PIO\n", reason);
  2726. for (i = 0; i < 2; i++) {
  2727. host->ports[i]->mwdma_mask = 0;
  2728. host->ports[i]->udma_mask = 0;
  2729. }
  2730. }
  2731. /**
  2732. * ata_pci_bmdma_init - acquire PCI BMDMA resources and init ATA host
  2733. * @host: target ATA host
  2734. *
  2735. * Acquire PCI BMDMA resources and initialize @host accordingly.
  2736. *
  2737. * LOCKING:
  2738. * Inherited from calling layer (may sleep).
  2739. */
  2740. void ata_pci_bmdma_init(struct ata_host *host)
  2741. {
  2742. struct device *gdev = host->dev;
  2743. struct pci_dev *pdev = to_pci_dev(gdev);
  2744. int i, rc;
  2745. /* No BAR4 allocation: No DMA */
  2746. if (pci_resource_start(pdev, 4) == 0) {
  2747. ata_bmdma_nodma(host, "BAR4 is zero");
  2748. return;
  2749. }
  2750. /*
  2751. * Some controllers require BMDMA region to be initialized
  2752. * even if DMA is not in use to clear IRQ status via
  2753. * ->sff_irq_clear method. Try to initialize bmdma_addr
  2754. * regardless of dma masks.
  2755. */
  2756. rc = dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK);
  2757. if (rc)
  2758. ata_bmdma_nodma(host, "failed to set dma mask");
  2759. /* request and iomap DMA region */
  2760. rc = pcim_iomap_regions(pdev, 1 << 4, dev_driver_string(gdev));
  2761. if (rc) {
  2762. ata_bmdma_nodma(host, "failed to request/iomap BAR4");
  2763. return;
  2764. }
  2765. host->iomap = pcim_iomap_table(pdev);
  2766. for (i = 0; i < 2; i++) {
  2767. struct ata_port *ap = host->ports[i];
  2768. void __iomem *bmdma = host->iomap[4] + 8 * i;
  2769. if (ata_port_is_dummy(ap))
  2770. continue;
  2771. ap->ioaddr.bmdma_addr = bmdma;
  2772. if ((!(ap->flags & ATA_FLAG_IGN_SIMPLEX)) &&
  2773. (ioread8(bmdma + 2) & 0x80))
  2774. host->flags |= ATA_HOST_SIMPLEX;
  2775. ata_port_desc(ap, "bmdma 0x%llx",
  2776. (unsigned long long)pci_resource_start(pdev, 4) + 8 * i);
  2777. }
  2778. }
  2779. EXPORT_SYMBOL_GPL(ata_pci_bmdma_init);
  2780. /**
  2781. * ata_pci_bmdma_prepare_host - helper to prepare PCI BMDMA ATA host
  2782. * @pdev: target PCI device
  2783. * @ppi: array of port_info, must be enough for two ports
  2784. * @r_host: out argument for the initialized ATA host
  2785. *
  2786. * Helper to allocate BMDMA ATA host for @pdev, acquire all PCI
  2787. * resources and initialize it accordingly in one go.
  2788. *
  2789. * LOCKING:
  2790. * Inherited from calling layer (may sleep).
  2791. *
  2792. * RETURNS:
  2793. * 0 on success, -errno otherwise.
  2794. */
  2795. int ata_pci_bmdma_prepare_host(struct pci_dev *pdev,
  2796. const struct ata_port_info * const * ppi,
  2797. struct ata_host **r_host)
  2798. {
  2799. int rc;
  2800. rc = ata_pci_sff_prepare_host(pdev, ppi, r_host);
  2801. if (rc)
  2802. return rc;
  2803. ata_pci_bmdma_init(*r_host);
  2804. return 0;
  2805. }
  2806. EXPORT_SYMBOL_GPL(ata_pci_bmdma_prepare_host);
  2807. /**
  2808. * ata_pci_bmdma_init_one - Initialize/register BMDMA PCI IDE controller
  2809. * @pdev: Controller to be initialized
  2810. * @ppi: array of port_info, must be enough for two ports
  2811. * @sht: scsi_host_template to use when registering the host
  2812. * @host_priv: host private_data
  2813. * @hflags: host flags
  2814. *
  2815. * This function is similar to ata_pci_sff_init_one() but also
  2816. * takes care of BMDMA initialization.
  2817. *
  2818. * LOCKING:
  2819. * Inherited from PCI layer (may sleep).
  2820. *
  2821. * RETURNS:
  2822. * Zero on success, negative on errno-based value on error.
  2823. */
  2824. int ata_pci_bmdma_init_one(struct pci_dev *pdev,
  2825. const struct ata_port_info * const * ppi,
  2826. struct scsi_host_template *sht, void *host_priv,
  2827. int hflags)
  2828. {
  2829. return ata_pci_init_one(pdev, ppi, sht, host_priv, hflags, 1);
  2830. }
  2831. EXPORT_SYMBOL_GPL(ata_pci_bmdma_init_one);
  2832. #endif /* CONFIG_PCI */
  2833. #endif /* CONFIG_ATA_BMDMA */
  2834. /**
  2835. * ata_sff_port_init - Initialize SFF/BMDMA ATA port
  2836. * @ap: Port to initialize
  2837. *
  2838. * Called on port allocation to initialize SFF/BMDMA specific
  2839. * fields.
  2840. *
  2841. * LOCKING:
  2842. * None.
  2843. */
  2844. void ata_sff_port_init(struct ata_port *ap)
  2845. {
  2846. INIT_DELAYED_WORK(&ap->sff_pio_task, ata_sff_pio_task);
  2847. ap->ctl = ATA_DEVCTL_OBS;
  2848. ap->last_ctl = 0xFF;
  2849. }
  2850. int __init ata_sff_init(void)
  2851. {
  2852. ata_sff_wq = alloc_workqueue("ata_sff", WQ_MEM_RECLAIM, WQ_MAX_ACTIVE);
  2853. if (!ata_sff_wq)
  2854. return -ENOMEM;
  2855. return 0;
  2856. }
  2857. void ata_sff_exit(void)
  2858. {
  2859. destroy_workqueue(ata_sff_wq);
  2860. }