ahci_xgene.c 26 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888
  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * AppliedMicro X-Gene SoC SATA Host Controller Driver
  4. *
  5. * Copyright (c) 2014, Applied Micro Circuits Corporation
  6. * Author: Loc Ho <lho@apm.com>
  7. * Tuan Phan <tphan@apm.com>
  8. * Suman Tripathi <stripathi@apm.com>
  9. *
  10. * NOTE: PM support is not currently available.
  11. */
  12. #include <linux/acpi.h>
  13. #include <linux/module.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/ahci_platform.h>
  16. #include <linux/of_address.h>
  17. #include <linux/of_device.h>
  18. #include <linux/of_irq.h>
  19. #include <linux/phy/phy.h>
  20. #include "ahci.h"
  21. #define DRV_NAME "xgene-ahci"
  22. /* Max # of disk per a controller */
  23. #define MAX_AHCI_CHN_PERCTR 2
  24. /* MUX CSR */
  25. #define SATA_ENET_CONFIG_REG 0x00000000
  26. #define CFG_SATA_ENET_SELECT_MASK 0x00000001
  27. /* SATA core host controller CSR */
  28. #define SLVRDERRATTRIBUTES 0x00000000
  29. #define SLVWRERRATTRIBUTES 0x00000004
  30. #define MSTRDERRATTRIBUTES 0x00000008
  31. #define MSTWRERRATTRIBUTES 0x0000000c
  32. #define BUSCTLREG 0x00000014
  33. #define IOFMSTRWAUX 0x00000018
  34. #define INTSTATUSMASK 0x0000002c
  35. #define ERRINTSTATUS 0x00000030
  36. #define ERRINTSTATUSMASK 0x00000034
  37. /* SATA host AHCI CSR */
  38. #define PORTCFG 0x000000a4
  39. #define PORTADDR_SET(dst, src) \
  40. (((dst) & ~0x0000003f) | (((u32)(src)) & 0x0000003f))
  41. #define PORTPHY1CFG 0x000000a8
  42. #define PORTPHY1CFG_FRCPHYRDY_SET(dst, src) \
  43. (((dst) & ~0x00100000) | (((u32)(src) << 0x14) & 0x00100000))
  44. #define PORTPHY2CFG 0x000000ac
  45. #define PORTPHY3CFG 0x000000b0
  46. #define PORTPHY4CFG 0x000000b4
  47. #define PORTPHY5CFG 0x000000b8
  48. #define SCTL0 0x0000012C
  49. #define PORTPHY5CFG_RTCHG_SET(dst, src) \
  50. (((dst) & ~0xfff00000) | (((u32)(src) << 0x14) & 0xfff00000))
  51. #define PORTAXICFG_EN_CONTEXT_SET(dst, src) \
  52. (((dst) & ~0x01000000) | (((u32)(src) << 0x18) & 0x01000000))
  53. #define PORTAXICFG 0x000000bc
  54. #define PORTAXICFG_OUTTRANS_SET(dst, src) \
  55. (((dst) & ~0x00f00000) | (((u32)(src) << 0x14) & 0x00f00000))
  56. #define PORTRANSCFG 0x000000c8
  57. #define PORTRANSCFG_RXWM_SET(dst, src) \
  58. (((dst) & ~0x0000007f) | (((u32)(src)) & 0x0000007f))
  59. /* SATA host controller AXI CSR */
  60. #define INT_SLV_TMOMASK 0x00000010
  61. /* SATA diagnostic CSR */
  62. #define CFG_MEM_RAM_SHUTDOWN 0x00000070
  63. #define BLOCK_MEM_RDY 0x00000074
  64. /* Max retry for link down */
  65. #define MAX_LINK_DOWN_RETRY 3
  66. enum xgene_ahci_version {
  67. XGENE_AHCI_V1 = 1,
  68. XGENE_AHCI_V2,
  69. };
  70. struct xgene_ahci_context {
  71. struct ahci_host_priv *hpriv;
  72. struct device *dev;
  73. u8 last_cmd[MAX_AHCI_CHN_PERCTR]; /* tracking the last command issued*/
  74. u32 class[MAX_AHCI_CHN_PERCTR]; /* tracking the class of device */
  75. void __iomem *csr_core; /* Core CSR address of IP */
  76. void __iomem *csr_diag; /* Diag CSR address of IP */
  77. void __iomem *csr_axi; /* AXI CSR address of IP */
  78. void __iomem *csr_mux; /* MUX CSR address of IP */
  79. };
  80. static int xgene_ahci_init_memram(struct xgene_ahci_context *ctx)
  81. {
  82. dev_dbg(ctx->dev, "Release memory from shutdown\n");
  83. writel(0x0, ctx->csr_diag + CFG_MEM_RAM_SHUTDOWN);
  84. readl(ctx->csr_diag + CFG_MEM_RAM_SHUTDOWN); /* Force a barrier */
  85. msleep(1); /* reset may take up to 1ms */
  86. if (readl(ctx->csr_diag + BLOCK_MEM_RDY) != 0xFFFFFFFF) {
  87. dev_err(ctx->dev, "failed to release memory from shutdown\n");
  88. return -ENODEV;
  89. }
  90. return 0;
  91. }
  92. /**
  93. * xgene_ahci_poll_reg_val- Poll a register on a specific value.
  94. * @ap : ATA port of interest.
  95. * @reg : Register of interest.
  96. * @val : Value to be attained.
  97. * @interval : waiting interval for polling.
  98. * @timeout : timeout for achieving the value.
  99. */
  100. static int xgene_ahci_poll_reg_val(struct ata_port *ap,
  101. void __iomem *reg, unsigned
  102. int val, unsigned long interval,
  103. unsigned long timeout)
  104. {
  105. unsigned long deadline;
  106. unsigned int tmp;
  107. tmp = ioread32(reg);
  108. deadline = ata_deadline(jiffies, timeout);
  109. while (tmp != val && time_before(jiffies, deadline)) {
  110. ata_msleep(ap, interval);
  111. tmp = ioread32(reg);
  112. }
  113. return tmp;
  114. }
  115. /**
  116. * xgene_ahci_restart_engine - Restart the dma engine.
  117. * @ap : ATA port of interest
  118. *
  119. * Waits for completion of multiple commands and restarts
  120. * the DMA engine inside the controller.
  121. */
  122. static int xgene_ahci_restart_engine(struct ata_port *ap)
  123. {
  124. struct ahci_host_priv *hpriv = ap->host->private_data;
  125. struct ahci_port_priv *pp = ap->private_data;
  126. void __iomem *port_mmio = ahci_port_base(ap);
  127. u32 fbs;
  128. /*
  129. * In case of PMP multiple IDENTIFY DEVICE commands can be
  130. * issued inside PxCI. So need to poll PxCI for the
  131. * completion of outstanding IDENTIFY DEVICE commands before
  132. * we restart the DMA engine.
  133. */
  134. if (xgene_ahci_poll_reg_val(ap, port_mmio +
  135. PORT_CMD_ISSUE, 0x0, 1, 100))
  136. return -EBUSY;
  137. hpriv->stop_engine(ap);
  138. ahci_start_fis_rx(ap);
  139. /*
  140. * Enable the PxFBS.FBS_EN bit as it
  141. * gets cleared due to stopping the engine.
  142. */
  143. if (pp->fbs_supported) {
  144. fbs = readl(port_mmio + PORT_FBS);
  145. writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
  146. fbs = readl(port_mmio + PORT_FBS);
  147. }
  148. hpriv->start_engine(ap);
  149. return 0;
  150. }
  151. /**
  152. * xgene_ahci_qc_issue - Issue commands to the device
  153. * @qc: Command to issue
  154. *
  155. * Due to Hardware errata for IDENTIFY DEVICE command, the controller cannot
  156. * clear the BSY bit after receiving the PIO setup FIS. This results in the dma
  157. * state machine goes into the CMFatalErrorUpdate state and locks up. By
  158. * restarting the dma engine, it removes the controller out of lock up state.
  159. *
  160. * Due to H/W errata, the controller is unable to save the PMP
  161. * field fetched from command header before sending the H2D FIS.
  162. * When the device returns the PMP port field in the D2H FIS, there is
  163. * a mismatch and results in command completion failure. The
  164. * workaround is to write the pmp value to PxFBS.DEV field before issuing
  165. * any command to PMP.
  166. */
  167. static unsigned int xgene_ahci_qc_issue(struct ata_queued_cmd *qc)
  168. {
  169. struct ata_port *ap = qc->ap;
  170. struct ahci_host_priv *hpriv = ap->host->private_data;
  171. struct xgene_ahci_context *ctx = hpriv->plat_data;
  172. int rc = 0;
  173. u32 port_fbs;
  174. void *port_mmio = ahci_port_base(ap);
  175. /*
  176. * Write the pmp value to PxFBS.DEV
  177. * for case of Port Mulitplier.
  178. */
  179. if (ctx->class[ap->port_no] == ATA_DEV_PMP) {
  180. port_fbs = readl(port_mmio + PORT_FBS);
  181. port_fbs &= ~PORT_FBS_DEV_MASK;
  182. port_fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
  183. writel(port_fbs, port_mmio + PORT_FBS);
  184. }
  185. if (unlikely((ctx->last_cmd[ap->port_no] == ATA_CMD_ID_ATA) ||
  186. (ctx->last_cmd[ap->port_no] == ATA_CMD_PACKET) ||
  187. (ctx->last_cmd[ap->port_no] == ATA_CMD_SMART)))
  188. xgene_ahci_restart_engine(ap);
  189. rc = ahci_qc_issue(qc);
  190. /* Save the last command issued */
  191. ctx->last_cmd[ap->port_no] = qc->tf.command;
  192. return rc;
  193. }
  194. static bool xgene_ahci_is_memram_inited(struct xgene_ahci_context *ctx)
  195. {
  196. void __iomem *diagcsr = ctx->csr_diag;
  197. return (readl(diagcsr + CFG_MEM_RAM_SHUTDOWN) == 0 &&
  198. readl(diagcsr + BLOCK_MEM_RDY) == 0xFFFFFFFF);
  199. }
  200. /**
  201. * xgene_ahci_read_id - Read ID data from the specified device
  202. * @dev: device
  203. * @tf: proposed taskfile
  204. * @id: data buffer
  205. *
  206. * This custom read ID function is required due to the fact that the HW
  207. * does not support DEVSLP.
  208. */
  209. static unsigned int xgene_ahci_read_id(struct ata_device *dev,
  210. struct ata_taskfile *tf, u16 *id)
  211. {
  212. u32 err_mask;
  213. err_mask = ata_do_dev_read_id(dev, tf, id);
  214. if (err_mask)
  215. return err_mask;
  216. /*
  217. * Mask reserved area. Word78 spec of Link Power Management
  218. * bit15-8: reserved
  219. * bit7: NCQ autosence
  220. * bit6: Software settings preservation supported
  221. * bit5: reserved
  222. * bit4: In-order sata delivery supported
  223. * bit3: DIPM requests supported
  224. * bit2: DMA Setup FIS Auto-Activate optimization supported
  225. * bit1: DMA Setup FIX non-Zero buffer offsets supported
  226. * bit0: Reserved
  227. *
  228. * Clear reserved bit 8 (DEVSLP bit) as we don't support DEVSLP
  229. */
  230. id[ATA_ID_FEATURE_SUPP] &= cpu_to_le16(~(1 << 8));
  231. return 0;
  232. }
  233. static void xgene_ahci_set_phy_cfg(struct xgene_ahci_context *ctx, int channel)
  234. {
  235. void __iomem *mmio = ctx->hpriv->mmio;
  236. u32 val;
  237. dev_dbg(ctx->dev, "port configure mmio 0x%p channel %d\n",
  238. mmio, channel);
  239. val = readl(mmio + PORTCFG);
  240. val = PORTADDR_SET(val, channel == 0 ? 2 : 3);
  241. writel(val, mmio + PORTCFG);
  242. readl(mmio + PORTCFG); /* Force a barrier */
  243. /* Disable fix rate */
  244. writel(0x0001fffe, mmio + PORTPHY1CFG);
  245. readl(mmio + PORTPHY1CFG); /* Force a barrier */
  246. writel(0x28183219, mmio + PORTPHY2CFG);
  247. readl(mmio + PORTPHY2CFG); /* Force a barrier */
  248. writel(0x13081008, mmio + PORTPHY3CFG);
  249. readl(mmio + PORTPHY3CFG); /* Force a barrier */
  250. writel(0x00480815, mmio + PORTPHY4CFG);
  251. readl(mmio + PORTPHY4CFG); /* Force a barrier */
  252. /* Set window negotiation */
  253. val = readl(mmio + PORTPHY5CFG);
  254. val = PORTPHY5CFG_RTCHG_SET(val, 0x300);
  255. writel(val, mmio + PORTPHY5CFG);
  256. readl(mmio + PORTPHY5CFG); /* Force a barrier */
  257. val = readl(mmio + PORTAXICFG);
  258. val = PORTAXICFG_EN_CONTEXT_SET(val, 0x1); /* Enable context mgmt */
  259. val = PORTAXICFG_OUTTRANS_SET(val, 0xe); /* Set outstanding */
  260. writel(val, mmio + PORTAXICFG);
  261. readl(mmio + PORTAXICFG); /* Force a barrier */
  262. /* Set the watermark threshold of the receive FIFO */
  263. val = readl(mmio + PORTRANSCFG);
  264. val = PORTRANSCFG_RXWM_SET(val, 0x30);
  265. writel(val, mmio + PORTRANSCFG);
  266. }
  267. /**
  268. * xgene_ahci_do_hardreset - Issue the actual COMRESET
  269. * @link: link to reset
  270. * @deadline: deadline jiffies for the operation
  271. * @online: Return value to indicate if device online
  272. *
  273. * Due to the limitation of the hardware PHY, a difference set of setting is
  274. * required for each supported disk speed - Gen3 (6.0Gbps), Gen2 (3.0Gbps),
  275. * and Gen1 (1.5Gbps). Otherwise during long IO stress test, the PHY will
  276. * report disparity error and etc. In addition, during COMRESET, there can
  277. * be error reported in the register PORT_SCR_ERR. For SERR_DISPARITY and
  278. * SERR_10B_8B_ERR, the PHY receiver line must be reseted. Also during long
  279. * reboot cycle regression, sometimes the PHY reports link down even if the
  280. * device is present because of speed negotiation failure. so need to retry
  281. * the COMRESET to get the link up. The following algorithm is followed to
  282. * proper configure the hardware PHY during COMRESET:
  283. *
  284. * Alg Part 1:
  285. * 1. Start the PHY at Gen3 speed (default setting)
  286. * 2. Issue the COMRESET
  287. * 3. If no link, go to Alg Part 3
  288. * 4. If link up, determine if the negotiated speed matches the PHY
  289. * configured speed
  290. * 5. If they matched, go to Alg Part 2
  291. * 6. If they do not matched and first time, configure the PHY for the linked
  292. * up disk speed and repeat step 2
  293. * 7. Go to Alg Part 2
  294. *
  295. * Alg Part 2:
  296. * 1. On link up, if there are any SERR_DISPARITY and SERR_10B_8B_ERR error
  297. * reported in the register PORT_SCR_ERR, then reset the PHY receiver line
  298. * 2. Go to Alg Part 4
  299. *
  300. * Alg Part 3:
  301. * 1. Check the PORT_SCR_STAT to see whether device presence detected but PHY
  302. * communication establishment failed and maximum link down attempts are
  303. * less than Max attempts 3 then goto Alg Part 1.
  304. * 2. Go to Alg Part 4.
  305. *
  306. * Alg Part 4:
  307. * 1. Clear any pending from register PORT_SCR_ERR.
  308. *
  309. * NOTE: For the initial version, we will NOT support Gen1/Gen2. In addition
  310. * and until the underlying PHY supports an method to reset the receiver
  311. * line, on detection of SERR_DISPARITY or SERR_10B_8B_ERR errors,
  312. * an warning message will be printed.
  313. */
  314. static int xgene_ahci_do_hardreset(struct ata_link *link,
  315. unsigned long deadline, bool *online)
  316. {
  317. const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
  318. struct ata_port *ap = link->ap;
  319. struct ahci_host_priv *hpriv = ap->host->private_data;
  320. struct xgene_ahci_context *ctx = hpriv->plat_data;
  321. struct ahci_port_priv *pp = ap->private_data;
  322. u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
  323. void __iomem *port_mmio = ahci_port_base(ap);
  324. struct ata_taskfile tf;
  325. int link_down_retry = 0;
  326. int rc;
  327. u32 val, sstatus;
  328. do {
  329. /* clear D2H reception area to properly wait for D2H FIS */
  330. ata_tf_init(link->device, &tf);
  331. tf.command = ATA_BUSY;
  332. ata_tf_to_fis(&tf, 0, 0, d2h_fis);
  333. rc = sata_link_hardreset(link, timing, deadline, online,
  334. ahci_check_ready);
  335. if (*online) {
  336. val = readl(port_mmio + PORT_SCR_ERR);
  337. if (val & (SERR_DISPARITY | SERR_10B_8B_ERR))
  338. dev_warn(ctx->dev, "link has error\n");
  339. break;
  340. }
  341. sata_scr_read(link, SCR_STATUS, &sstatus);
  342. } while (link_down_retry++ < MAX_LINK_DOWN_RETRY &&
  343. (sstatus & 0xff) == 0x1);
  344. /* clear all errors if any pending */
  345. val = readl(port_mmio + PORT_SCR_ERR);
  346. writel(val, port_mmio + PORT_SCR_ERR);
  347. return rc;
  348. }
  349. static int xgene_ahci_hardreset(struct ata_link *link, unsigned int *class,
  350. unsigned long deadline)
  351. {
  352. struct ata_port *ap = link->ap;
  353. struct ahci_host_priv *hpriv = ap->host->private_data;
  354. void __iomem *port_mmio = ahci_port_base(ap);
  355. bool online;
  356. int rc;
  357. u32 portcmd_saved;
  358. u32 portclb_saved;
  359. u32 portclbhi_saved;
  360. u32 portrxfis_saved;
  361. u32 portrxfishi_saved;
  362. /* As hardreset resets these CSR, save it to restore later */
  363. portcmd_saved = readl(port_mmio + PORT_CMD);
  364. portclb_saved = readl(port_mmio + PORT_LST_ADDR);
  365. portclbhi_saved = readl(port_mmio + PORT_LST_ADDR_HI);
  366. portrxfis_saved = readl(port_mmio + PORT_FIS_ADDR);
  367. portrxfishi_saved = readl(port_mmio + PORT_FIS_ADDR_HI);
  368. hpriv->stop_engine(ap);
  369. rc = xgene_ahci_do_hardreset(link, deadline, &online);
  370. /* As controller hardreset clears them, restore them */
  371. writel(portcmd_saved, port_mmio + PORT_CMD);
  372. writel(portclb_saved, port_mmio + PORT_LST_ADDR);
  373. writel(portclbhi_saved, port_mmio + PORT_LST_ADDR_HI);
  374. writel(portrxfis_saved, port_mmio + PORT_FIS_ADDR);
  375. writel(portrxfishi_saved, port_mmio + PORT_FIS_ADDR_HI);
  376. hpriv->start_engine(ap);
  377. if (online)
  378. *class = ahci_dev_classify(ap);
  379. return rc;
  380. }
  381. static void xgene_ahci_host_stop(struct ata_host *host)
  382. {
  383. struct ahci_host_priv *hpriv = host->private_data;
  384. ahci_platform_disable_resources(hpriv);
  385. }
  386. /**
  387. * xgene_ahci_pmp_softreset - Issue the softreset to the drives connected
  388. * to Port Multiplier.
  389. * @link: link to reset
  390. * @class: Return value to indicate class of device
  391. * @deadline: deadline jiffies for the operation
  392. *
  393. * Due to H/W errata, the controller is unable to save the PMP
  394. * field fetched from command header before sending the H2D FIS.
  395. * When the device returns the PMP port field in the D2H FIS, there is
  396. * a mismatch and results in command completion failure. The workaround
  397. * is to write the pmp value to PxFBS.DEV field before issuing any command
  398. * to PMP.
  399. */
  400. static int xgene_ahci_pmp_softreset(struct ata_link *link, unsigned int *class,
  401. unsigned long deadline)
  402. {
  403. int pmp = sata_srst_pmp(link);
  404. struct ata_port *ap = link->ap;
  405. u32 rc;
  406. void *port_mmio = ahci_port_base(ap);
  407. u32 port_fbs;
  408. /*
  409. * Set PxFBS.DEV field with pmp
  410. * value.
  411. */
  412. port_fbs = readl(port_mmio + PORT_FBS);
  413. port_fbs &= ~PORT_FBS_DEV_MASK;
  414. port_fbs |= pmp << PORT_FBS_DEV_OFFSET;
  415. writel(port_fbs, port_mmio + PORT_FBS);
  416. rc = ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
  417. return rc;
  418. }
  419. /**
  420. * xgene_ahci_softreset - Issue the softreset to the drive.
  421. * @link: link to reset
  422. * @class: Return value to indicate class of device
  423. * @deadline: deadline jiffies for the operation
  424. *
  425. * Due to H/W errata, the controller is unable to save the PMP
  426. * field fetched from command header before sending the H2D FIS.
  427. * When the device returns the PMP port field in the D2H FIS, there is
  428. * a mismatch and results in command completion failure. The workaround
  429. * is to write the pmp value to PxFBS.DEV field before issuing any command
  430. * to PMP. Here is the algorithm to detect PMP :
  431. *
  432. * 1. Save the PxFBS value
  433. * 2. Program PxFBS.DEV with pmp value send by framework. Framework sends
  434. * 0xF for both PMP/NON-PMP initially
  435. * 3. Issue softreset
  436. * 4. If signature class is PMP goto 6
  437. * 5. restore the original PxFBS and goto 3
  438. * 6. return
  439. */
  440. static int xgene_ahci_softreset(struct ata_link *link, unsigned int *class,
  441. unsigned long deadline)
  442. {
  443. int pmp = sata_srst_pmp(link);
  444. struct ata_port *ap = link->ap;
  445. struct ahci_host_priv *hpriv = ap->host->private_data;
  446. struct xgene_ahci_context *ctx = hpriv->plat_data;
  447. void *port_mmio = ahci_port_base(ap);
  448. u32 port_fbs;
  449. u32 port_fbs_save;
  450. u32 retry = 1;
  451. u32 rc;
  452. port_fbs_save = readl(port_mmio + PORT_FBS);
  453. /*
  454. * Set PxFBS.DEV field with pmp
  455. * value.
  456. */
  457. port_fbs = readl(port_mmio + PORT_FBS);
  458. port_fbs &= ~PORT_FBS_DEV_MASK;
  459. port_fbs |= pmp << PORT_FBS_DEV_OFFSET;
  460. writel(port_fbs, port_mmio + PORT_FBS);
  461. softreset_retry:
  462. rc = ahci_do_softreset(link, class, pmp,
  463. deadline, ahci_check_ready);
  464. ctx->class[ap->port_no] = *class;
  465. if (*class != ATA_DEV_PMP) {
  466. /*
  467. * Retry for normal drives without
  468. * setting PxFBS.DEV field with pmp value.
  469. */
  470. if (retry--) {
  471. writel(port_fbs_save, port_mmio + PORT_FBS);
  472. goto softreset_retry;
  473. }
  474. }
  475. return rc;
  476. }
  477. /**
  478. * xgene_ahci_handle_broken_edge_irq - Handle the broken irq.
  479. * @ata_host: Host that recieved the irq
  480. * @irq_masked: HOST_IRQ_STAT value
  481. *
  482. * For hardware with broken edge trigger latch
  483. * the HOST_IRQ_STAT register misses the edge interrupt
  484. * when clearing of HOST_IRQ_STAT register and hardware
  485. * reporting the PORT_IRQ_STAT register at the
  486. * same clock cycle.
  487. * As such, the algorithm below outlines the workaround.
  488. *
  489. * 1. Read HOST_IRQ_STAT register and save the state.
  490. * 2. Clear the HOST_IRQ_STAT register.
  491. * 3. Read back the HOST_IRQ_STAT register.
  492. * 4. If HOST_IRQ_STAT register equals to zero, then
  493. * traverse the rest of port's PORT_IRQ_STAT register
  494. * to check if an interrupt is triggered at that point else
  495. * go to step 6.
  496. * 5. If PORT_IRQ_STAT register of rest ports is not equal to zero
  497. * then update the state of HOST_IRQ_STAT saved in step 1.
  498. * 6. Handle port interrupts.
  499. * 7. Exit
  500. */
  501. static int xgene_ahci_handle_broken_edge_irq(struct ata_host *host,
  502. u32 irq_masked)
  503. {
  504. struct ahci_host_priv *hpriv = host->private_data;
  505. void __iomem *port_mmio;
  506. int i;
  507. if (!readl(hpriv->mmio + HOST_IRQ_STAT)) {
  508. for (i = 0; i < host->n_ports; i++) {
  509. if (irq_masked & (1 << i))
  510. continue;
  511. port_mmio = ahci_port_base(host->ports[i]);
  512. if (readl(port_mmio + PORT_IRQ_STAT))
  513. irq_masked |= (1 << i);
  514. }
  515. }
  516. return ahci_handle_port_intr(host, irq_masked);
  517. }
  518. static irqreturn_t xgene_ahci_irq_intr(int irq, void *dev_instance)
  519. {
  520. struct ata_host *host = dev_instance;
  521. struct ahci_host_priv *hpriv;
  522. unsigned int rc = 0;
  523. void __iomem *mmio;
  524. u32 irq_stat, irq_masked;
  525. VPRINTK("ENTER\n");
  526. hpriv = host->private_data;
  527. mmio = hpriv->mmio;
  528. /* sigh. 0xffffffff is a valid return from h/w */
  529. irq_stat = readl(mmio + HOST_IRQ_STAT);
  530. if (!irq_stat)
  531. return IRQ_NONE;
  532. irq_masked = irq_stat & hpriv->port_map;
  533. spin_lock(&host->lock);
  534. /*
  535. * HOST_IRQ_STAT behaves as edge triggered latch meaning that
  536. * it should be cleared before all the port events are cleared.
  537. */
  538. writel(irq_stat, mmio + HOST_IRQ_STAT);
  539. rc = xgene_ahci_handle_broken_edge_irq(host, irq_masked);
  540. spin_unlock(&host->lock);
  541. VPRINTK("EXIT\n");
  542. return IRQ_RETVAL(rc);
  543. }
  544. static struct ata_port_operations xgene_ahci_v1_ops = {
  545. .inherits = &ahci_ops,
  546. .host_stop = xgene_ahci_host_stop,
  547. .hardreset = xgene_ahci_hardreset,
  548. .read_id = xgene_ahci_read_id,
  549. .qc_issue = xgene_ahci_qc_issue,
  550. .softreset = xgene_ahci_softreset,
  551. .pmp_softreset = xgene_ahci_pmp_softreset
  552. };
  553. static const struct ata_port_info xgene_ahci_v1_port_info = {
  554. .flags = AHCI_FLAG_COMMON | ATA_FLAG_PMP,
  555. .pio_mask = ATA_PIO4,
  556. .udma_mask = ATA_UDMA6,
  557. .port_ops = &xgene_ahci_v1_ops,
  558. };
  559. static struct ata_port_operations xgene_ahci_v2_ops = {
  560. .inherits = &ahci_ops,
  561. .host_stop = xgene_ahci_host_stop,
  562. .hardreset = xgene_ahci_hardreset,
  563. .read_id = xgene_ahci_read_id,
  564. };
  565. static const struct ata_port_info xgene_ahci_v2_port_info = {
  566. .flags = AHCI_FLAG_COMMON | ATA_FLAG_PMP,
  567. .pio_mask = ATA_PIO4,
  568. .udma_mask = ATA_UDMA6,
  569. .port_ops = &xgene_ahci_v2_ops,
  570. };
  571. static int xgene_ahci_hw_init(struct ahci_host_priv *hpriv)
  572. {
  573. struct xgene_ahci_context *ctx = hpriv->plat_data;
  574. int i;
  575. int rc;
  576. u32 val;
  577. /* Remove IP RAM out of shutdown */
  578. rc = xgene_ahci_init_memram(ctx);
  579. if (rc)
  580. return rc;
  581. for (i = 0; i < MAX_AHCI_CHN_PERCTR; i++)
  582. xgene_ahci_set_phy_cfg(ctx, i);
  583. /* AXI disable Mask */
  584. writel(0xffffffff, hpriv->mmio + HOST_IRQ_STAT);
  585. readl(hpriv->mmio + HOST_IRQ_STAT); /* Force a barrier */
  586. writel(0, ctx->csr_core + INTSTATUSMASK);
  587. val = readl(ctx->csr_core + INTSTATUSMASK); /* Force a barrier */
  588. dev_dbg(ctx->dev, "top level interrupt mask 0x%X value 0x%08X\n",
  589. INTSTATUSMASK, val);
  590. writel(0x0, ctx->csr_core + ERRINTSTATUSMASK);
  591. readl(ctx->csr_core + ERRINTSTATUSMASK); /* Force a barrier */
  592. writel(0x0, ctx->csr_axi + INT_SLV_TMOMASK);
  593. readl(ctx->csr_axi + INT_SLV_TMOMASK);
  594. /* Enable AXI Interrupt */
  595. writel(0xffffffff, ctx->csr_core + SLVRDERRATTRIBUTES);
  596. writel(0xffffffff, ctx->csr_core + SLVWRERRATTRIBUTES);
  597. writel(0xffffffff, ctx->csr_core + MSTRDERRATTRIBUTES);
  598. writel(0xffffffff, ctx->csr_core + MSTWRERRATTRIBUTES);
  599. /* Enable coherency */
  600. val = readl(ctx->csr_core + BUSCTLREG);
  601. val &= ~0x00000002; /* Enable write coherency */
  602. val &= ~0x00000001; /* Enable read coherency */
  603. writel(val, ctx->csr_core + BUSCTLREG);
  604. val = readl(ctx->csr_core + IOFMSTRWAUX);
  605. val |= (1 << 3); /* Enable read coherency */
  606. val |= (1 << 9); /* Enable write coherency */
  607. writel(val, ctx->csr_core + IOFMSTRWAUX);
  608. val = readl(ctx->csr_core + IOFMSTRWAUX);
  609. dev_dbg(ctx->dev, "coherency 0x%X value 0x%08X\n",
  610. IOFMSTRWAUX, val);
  611. return rc;
  612. }
  613. static int xgene_ahci_mux_select(struct xgene_ahci_context *ctx)
  614. {
  615. u32 val;
  616. /* Check for optional MUX resource */
  617. if (!ctx->csr_mux)
  618. return 0;
  619. val = readl(ctx->csr_mux + SATA_ENET_CONFIG_REG);
  620. val &= ~CFG_SATA_ENET_SELECT_MASK;
  621. writel(val, ctx->csr_mux + SATA_ENET_CONFIG_REG);
  622. val = readl(ctx->csr_mux + SATA_ENET_CONFIG_REG);
  623. return val & CFG_SATA_ENET_SELECT_MASK ? -1 : 0;
  624. }
  625. static struct scsi_host_template ahci_platform_sht = {
  626. AHCI_SHT(DRV_NAME),
  627. };
  628. #ifdef CONFIG_ACPI
  629. static const struct acpi_device_id xgene_ahci_acpi_match[] = {
  630. { "APMC0D0D", XGENE_AHCI_V1},
  631. { "APMC0D32", XGENE_AHCI_V2},
  632. {},
  633. };
  634. MODULE_DEVICE_TABLE(acpi, xgene_ahci_acpi_match);
  635. #endif
  636. static const struct of_device_id xgene_ahci_of_match[] = {
  637. {.compatible = "apm,xgene-ahci", .data = (void *) XGENE_AHCI_V1},
  638. {.compatible = "apm,xgene-ahci-v2", .data = (void *) XGENE_AHCI_V2},
  639. {},
  640. };
  641. MODULE_DEVICE_TABLE(of, xgene_ahci_of_match);
  642. static int xgene_ahci_probe(struct platform_device *pdev)
  643. {
  644. struct device *dev = &pdev->dev;
  645. struct ahci_host_priv *hpriv;
  646. struct xgene_ahci_context *ctx;
  647. struct resource *res;
  648. const struct of_device_id *of_devid;
  649. enum xgene_ahci_version version = XGENE_AHCI_V1;
  650. const struct ata_port_info *ppi[] = { &xgene_ahci_v1_port_info,
  651. &xgene_ahci_v2_port_info };
  652. int rc;
  653. hpriv = ahci_platform_get_resources(pdev, 0);
  654. if (IS_ERR(hpriv))
  655. return PTR_ERR(hpriv);
  656. ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
  657. if (!ctx)
  658. return -ENOMEM;
  659. hpriv->plat_data = ctx;
  660. ctx->hpriv = hpriv;
  661. ctx->dev = dev;
  662. /* Retrieve the IP core resource */
  663. res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  664. ctx->csr_core = devm_ioremap_resource(dev, res);
  665. if (IS_ERR(ctx->csr_core))
  666. return PTR_ERR(ctx->csr_core);
  667. /* Retrieve the IP diagnostic resource */
  668. res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
  669. ctx->csr_diag = devm_ioremap_resource(dev, res);
  670. if (IS_ERR(ctx->csr_diag))
  671. return PTR_ERR(ctx->csr_diag);
  672. /* Retrieve the IP AXI resource */
  673. res = platform_get_resource(pdev, IORESOURCE_MEM, 3);
  674. ctx->csr_axi = devm_ioremap_resource(dev, res);
  675. if (IS_ERR(ctx->csr_axi))
  676. return PTR_ERR(ctx->csr_axi);
  677. /* Retrieve the optional IP mux resource */
  678. res = platform_get_resource(pdev, IORESOURCE_MEM, 4);
  679. if (res) {
  680. void __iomem *csr = devm_ioremap_resource(dev, res);
  681. if (IS_ERR(csr))
  682. return PTR_ERR(csr);
  683. ctx->csr_mux = csr;
  684. }
  685. of_devid = of_match_device(xgene_ahci_of_match, dev);
  686. if (of_devid) {
  687. if (of_devid->data)
  688. version = (enum xgene_ahci_version) of_devid->data;
  689. }
  690. #ifdef CONFIG_ACPI
  691. else {
  692. const struct acpi_device_id *acpi_id;
  693. struct acpi_device_info *info;
  694. acpi_status status;
  695. acpi_id = acpi_match_device(xgene_ahci_acpi_match, &pdev->dev);
  696. if (!acpi_id) {
  697. dev_warn(&pdev->dev, "No node entry in ACPI table. Assume version1\n");
  698. version = XGENE_AHCI_V1;
  699. } else if (acpi_id->driver_data) {
  700. version = (enum xgene_ahci_version) acpi_id->driver_data;
  701. status = acpi_get_object_info(ACPI_HANDLE(&pdev->dev), &info);
  702. if (ACPI_FAILURE(status)) {
  703. dev_warn(&pdev->dev, "%s: Error reading device info. Assume version1\n",
  704. __func__);
  705. version = XGENE_AHCI_V1;
  706. } else {
  707. if (info->valid & ACPI_VALID_CID)
  708. version = XGENE_AHCI_V2;
  709. kfree(info);
  710. }
  711. }
  712. }
  713. #endif
  714. dev_dbg(dev, "VAddr 0x%p Mmio VAddr 0x%p\n", ctx->csr_core,
  715. hpriv->mmio);
  716. /* Select ATA */
  717. if ((rc = xgene_ahci_mux_select(ctx))) {
  718. dev_err(dev, "SATA mux selection failed error %d\n", rc);
  719. return -ENODEV;
  720. }
  721. if (xgene_ahci_is_memram_inited(ctx)) {
  722. dev_info(dev, "skip clock and PHY initialization\n");
  723. goto skip_clk_phy;
  724. }
  725. /* Due to errata, HW requires full toggle transition */
  726. rc = ahci_platform_enable_clks(hpriv);
  727. if (rc)
  728. goto disable_resources;
  729. ahci_platform_disable_clks(hpriv);
  730. rc = ahci_platform_enable_resources(hpriv);
  731. if (rc)
  732. goto disable_resources;
  733. /* Configure the host controller */
  734. xgene_ahci_hw_init(hpriv);
  735. skip_clk_phy:
  736. switch (version) {
  737. case XGENE_AHCI_V1:
  738. hpriv->flags = AHCI_HFLAG_NO_NCQ;
  739. break;
  740. case XGENE_AHCI_V2:
  741. hpriv->flags |= AHCI_HFLAG_YES_FBS;
  742. hpriv->irq_handler = xgene_ahci_irq_intr;
  743. break;
  744. default:
  745. break;
  746. }
  747. rc = ahci_platform_init_host(pdev, hpriv, ppi[version - 1],
  748. &ahci_platform_sht);
  749. if (rc)
  750. goto disable_resources;
  751. dev_dbg(dev, "X-Gene SATA host controller initialized\n");
  752. return 0;
  753. disable_resources:
  754. ahci_platform_disable_resources(hpriv);
  755. return rc;
  756. }
  757. static struct platform_driver xgene_ahci_driver = {
  758. .probe = xgene_ahci_probe,
  759. .remove = ata_platform_remove_one,
  760. .driver = {
  761. .name = DRV_NAME,
  762. .of_match_table = xgene_ahci_of_match,
  763. .acpi_match_table = ACPI_PTR(xgene_ahci_acpi_match),
  764. },
  765. };
  766. module_platform_driver(xgene_ahci_driver);
  767. MODULE_DESCRIPTION("APM X-Gene AHCI SATA driver");
  768. MODULE_AUTHOR("Loc Ho <lho@apm.com>");
  769. MODULE_LICENSE("GPL");
  770. MODULE_VERSION("0.4");