ahci_qoriq.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Freescale QorIQ AHCI SATA platform driver
  4. *
  5. * Copyright 2015 Freescale, Inc.
  6. * Tang Yuantian <Yuantian.Tang@freescale.com>
  7. */
  8. #include <linux/acpi.h>
  9. #include <linux/kernel.h>
  10. #include <linux/module.h>
  11. #include <linux/pm.h>
  12. #include <linux/ahci_platform.h>
  13. #include <linux/device.h>
  14. #include <linux/of_address.h>
  15. #include <linux/of.h>
  16. #include <linux/of_device.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/libata.h>
  19. #include "ahci.h"
  20. #define DRV_NAME "ahci-qoriq"
  21. /* port register definition */
  22. #define PORT_PHY1 0xA8
  23. #define PORT_PHY2 0xAC
  24. #define PORT_PHY3 0xB0
  25. #define PORT_PHY4 0xB4
  26. #define PORT_PHY5 0xB8
  27. #define PORT_AXICC 0xBC
  28. #define PORT_TRANS 0xC8
  29. /* port register default value */
  30. #define AHCI_PORT_PHY_1_CFG 0xa003fffe
  31. #define AHCI_PORT_PHY2_CFG 0x28184d1f
  32. #define AHCI_PORT_PHY3_CFG 0x0e081509
  33. #define AHCI_PORT_TRANS_CFG 0x08000029
  34. #define AHCI_PORT_AXICC_CFG 0x3fffffff
  35. /* for ls1021a */
  36. #define LS1021A_PORT_PHY2 0x28183414
  37. #define LS1021A_PORT_PHY3 0x0e080e06
  38. #define LS1021A_PORT_PHY4 0x064a080b
  39. #define LS1021A_PORT_PHY5 0x2aa86470
  40. #define LS1021A_AXICC_ADDR 0xC0
  41. #define SATA_ECC_DISABLE 0x00020000
  42. #define ECC_DIS_ARMV8_CH2 0x80000000
  43. #define ECC_DIS_LS1088A 0x40000000
  44. enum ahci_qoriq_type {
  45. AHCI_LS1021A,
  46. AHCI_LS1028A,
  47. AHCI_LS1043A,
  48. AHCI_LS2080A,
  49. AHCI_LS1046A,
  50. AHCI_LS1088A,
  51. AHCI_LS2088A,
  52. AHCI_LX2160A,
  53. };
  54. struct ahci_qoriq_priv {
  55. struct ccsr_ahci *reg_base;
  56. enum ahci_qoriq_type type;
  57. void __iomem *ecc_addr;
  58. bool is_dmacoherent;
  59. };
  60. static bool ecc_initialized;
  61. static const struct of_device_id ahci_qoriq_of_match[] = {
  62. { .compatible = "fsl,ls1021a-ahci", .data = (void *)AHCI_LS1021A},
  63. { .compatible = "fsl,ls1028a-ahci", .data = (void *)AHCI_LS1028A},
  64. { .compatible = "fsl,ls1043a-ahci", .data = (void *)AHCI_LS1043A},
  65. { .compatible = "fsl,ls2080a-ahci", .data = (void *)AHCI_LS2080A},
  66. { .compatible = "fsl,ls1046a-ahci", .data = (void *)AHCI_LS1046A},
  67. { .compatible = "fsl,ls1088a-ahci", .data = (void *)AHCI_LS1088A},
  68. { .compatible = "fsl,ls2088a-ahci", .data = (void *)AHCI_LS2088A},
  69. { .compatible = "fsl,lx2160a-ahci", .data = (void *)AHCI_LX2160A},
  70. {},
  71. };
  72. MODULE_DEVICE_TABLE(of, ahci_qoriq_of_match);
  73. static const struct acpi_device_id ahci_qoriq_acpi_match[] = {
  74. {"NXP0004", .driver_data = (kernel_ulong_t)AHCI_LX2160A},
  75. { }
  76. };
  77. MODULE_DEVICE_TABLE(acpi, ahci_qoriq_acpi_match);
  78. static int ahci_qoriq_hardreset(struct ata_link *link, unsigned int *class,
  79. unsigned long deadline)
  80. {
  81. const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
  82. void __iomem *port_mmio = ahci_port_base(link->ap);
  83. u32 px_cmd, px_is, px_val;
  84. struct ata_port *ap = link->ap;
  85. struct ahci_port_priv *pp = ap->private_data;
  86. struct ahci_host_priv *hpriv = ap->host->private_data;
  87. struct ahci_qoriq_priv *qoriq_priv = hpriv->plat_data;
  88. u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
  89. struct ata_taskfile tf;
  90. bool online;
  91. int rc;
  92. bool ls1021a_workaround = (qoriq_priv->type == AHCI_LS1021A);
  93. DPRINTK("ENTER\n");
  94. hpriv->stop_engine(ap);
  95. /*
  96. * There is a errata on ls1021a Rev1.0 and Rev2.0 which is:
  97. * A-009042: The device detection initialization sequence
  98. * mistakenly resets some registers.
  99. *
  100. * Workaround for this is:
  101. * The software should read and store PxCMD and PxIS values
  102. * before issuing the device detection initialization sequence.
  103. * After the sequence is complete, software should restore the
  104. * PxCMD and PxIS with the stored values.
  105. */
  106. if (ls1021a_workaround) {
  107. px_cmd = readl(port_mmio + PORT_CMD);
  108. px_is = readl(port_mmio + PORT_IRQ_STAT);
  109. }
  110. /* clear D2H reception area to properly wait for D2H FIS */
  111. ata_tf_init(link->device, &tf);
  112. tf.command = ATA_BUSY;
  113. ata_tf_to_fis(&tf, 0, 0, d2h_fis);
  114. rc = sata_link_hardreset(link, timing, deadline, &online,
  115. ahci_check_ready);
  116. /* restore the PxCMD and PxIS on ls1021 */
  117. if (ls1021a_workaround) {
  118. px_val = readl(port_mmio + PORT_CMD);
  119. if (px_val != px_cmd)
  120. writel(px_cmd, port_mmio + PORT_CMD);
  121. px_val = readl(port_mmio + PORT_IRQ_STAT);
  122. if (px_val != px_is)
  123. writel(px_is, port_mmio + PORT_IRQ_STAT);
  124. }
  125. hpriv->start_engine(ap);
  126. if (online)
  127. *class = ahci_dev_classify(ap);
  128. DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
  129. return rc;
  130. }
  131. static struct ata_port_operations ahci_qoriq_ops = {
  132. .inherits = &ahci_ops,
  133. .hardreset = ahci_qoriq_hardreset,
  134. };
  135. static const struct ata_port_info ahci_qoriq_port_info = {
  136. .flags = AHCI_FLAG_COMMON | ATA_FLAG_NCQ,
  137. .pio_mask = ATA_PIO4,
  138. .udma_mask = ATA_UDMA6,
  139. .port_ops = &ahci_qoriq_ops,
  140. };
  141. static struct scsi_host_template ahci_qoriq_sht = {
  142. AHCI_SHT(DRV_NAME),
  143. };
  144. static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
  145. {
  146. struct ahci_qoriq_priv *qpriv = hpriv->plat_data;
  147. void __iomem *reg_base = hpriv->mmio;
  148. switch (qpriv->type) {
  149. case AHCI_LS1021A:
  150. if (!(qpriv->ecc_addr || ecc_initialized))
  151. return -EINVAL;
  152. else if (qpriv->ecc_addr && !ecc_initialized)
  153. writel(SATA_ECC_DISABLE, qpriv->ecc_addr);
  154. writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
  155. writel(LS1021A_PORT_PHY2, reg_base + PORT_PHY2);
  156. writel(LS1021A_PORT_PHY3, reg_base + PORT_PHY3);
  157. writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4);
  158. writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5);
  159. writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
  160. if (qpriv->is_dmacoherent)
  161. writel(AHCI_PORT_AXICC_CFG,
  162. reg_base + LS1021A_AXICC_ADDR);
  163. break;
  164. case AHCI_LS1043A:
  165. if (!(qpriv->ecc_addr || ecc_initialized))
  166. return -EINVAL;
  167. else if (qpriv->ecc_addr && !ecc_initialized)
  168. writel(readl(qpriv->ecc_addr) |
  169. ECC_DIS_ARMV8_CH2,
  170. qpriv->ecc_addr);
  171. writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
  172. writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
  173. writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
  174. writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
  175. if (qpriv->is_dmacoherent)
  176. writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
  177. break;
  178. case AHCI_LS2080A:
  179. writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
  180. writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
  181. writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
  182. writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
  183. if (qpriv->is_dmacoherent)
  184. writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
  185. break;
  186. case AHCI_LS1046A:
  187. if (!(qpriv->ecc_addr || ecc_initialized))
  188. return -EINVAL;
  189. else if (qpriv->ecc_addr && !ecc_initialized)
  190. writel(readl(qpriv->ecc_addr) |
  191. ECC_DIS_ARMV8_CH2,
  192. qpriv->ecc_addr);
  193. writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
  194. writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
  195. writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
  196. writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
  197. if (qpriv->is_dmacoherent)
  198. writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
  199. break;
  200. case AHCI_LS1028A:
  201. case AHCI_LS1088A:
  202. case AHCI_LX2160A:
  203. if (!(qpriv->ecc_addr || ecc_initialized))
  204. return -EINVAL;
  205. else if (qpriv->ecc_addr && !ecc_initialized)
  206. writel(readl(qpriv->ecc_addr) |
  207. ECC_DIS_LS1088A,
  208. qpriv->ecc_addr);
  209. writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
  210. writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
  211. writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
  212. writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
  213. if (qpriv->is_dmacoherent)
  214. writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
  215. break;
  216. case AHCI_LS2088A:
  217. writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
  218. writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
  219. writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
  220. writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
  221. if (qpriv->is_dmacoherent)
  222. writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
  223. break;
  224. }
  225. ecc_initialized = true;
  226. return 0;
  227. }
  228. static int ahci_qoriq_probe(struct platform_device *pdev)
  229. {
  230. struct device_node *np = pdev->dev.of_node;
  231. const struct acpi_device_id *acpi_id;
  232. struct device *dev = &pdev->dev;
  233. struct ahci_host_priv *hpriv;
  234. struct ahci_qoriq_priv *qoriq_priv;
  235. const struct of_device_id *of_id;
  236. struct resource *res;
  237. int rc;
  238. hpriv = ahci_platform_get_resources(pdev, 0);
  239. if (IS_ERR(hpriv))
  240. return PTR_ERR(hpriv);
  241. of_id = of_match_node(ahci_qoriq_of_match, np);
  242. acpi_id = acpi_match_device(ahci_qoriq_acpi_match, &pdev->dev);
  243. if (!(of_id || acpi_id))
  244. return -ENODEV;
  245. qoriq_priv = devm_kzalloc(dev, sizeof(*qoriq_priv), GFP_KERNEL);
  246. if (!qoriq_priv)
  247. return -ENOMEM;
  248. if (of_id)
  249. qoriq_priv->type = (enum ahci_qoriq_type)of_id->data;
  250. else
  251. qoriq_priv->type = (enum ahci_qoriq_type)acpi_id->driver_data;
  252. if (unlikely(!ecc_initialized)) {
  253. res = platform_get_resource_byname(pdev,
  254. IORESOURCE_MEM,
  255. "sata-ecc");
  256. if (res) {
  257. qoriq_priv->ecc_addr =
  258. devm_ioremap_resource(dev, res);
  259. if (IS_ERR(qoriq_priv->ecc_addr))
  260. return PTR_ERR(qoriq_priv->ecc_addr);
  261. }
  262. }
  263. if (device_get_dma_attr(&pdev->dev) == DEV_DMA_COHERENT)
  264. qoriq_priv->is_dmacoherent = true;
  265. rc = ahci_platform_enable_resources(hpriv);
  266. if (rc)
  267. return rc;
  268. hpriv->plat_data = qoriq_priv;
  269. rc = ahci_qoriq_phy_init(hpriv);
  270. if (rc)
  271. goto disable_resources;
  272. rc = ahci_platform_init_host(pdev, hpriv, &ahci_qoriq_port_info,
  273. &ahci_qoriq_sht);
  274. if (rc)
  275. goto disable_resources;
  276. return 0;
  277. disable_resources:
  278. ahci_platform_disable_resources(hpriv);
  279. return rc;
  280. }
  281. #ifdef CONFIG_PM_SLEEP
  282. static int ahci_qoriq_resume(struct device *dev)
  283. {
  284. struct ata_host *host = dev_get_drvdata(dev);
  285. struct ahci_host_priv *hpriv = host->private_data;
  286. int rc;
  287. rc = ahci_platform_enable_resources(hpriv);
  288. if (rc)
  289. return rc;
  290. rc = ahci_qoriq_phy_init(hpriv);
  291. if (rc)
  292. goto disable_resources;
  293. rc = ahci_platform_resume_host(dev);
  294. if (rc)
  295. goto disable_resources;
  296. /* We resumed so update PM runtime state */
  297. pm_runtime_disable(dev);
  298. pm_runtime_set_active(dev);
  299. pm_runtime_enable(dev);
  300. return 0;
  301. disable_resources:
  302. ahci_platform_disable_resources(hpriv);
  303. return rc;
  304. }
  305. #endif
  306. static SIMPLE_DEV_PM_OPS(ahci_qoriq_pm_ops, ahci_platform_suspend,
  307. ahci_qoriq_resume);
  308. static struct platform_driver ahci_qoriq_driver = {
  309. .probe = ahci_qoriq_probe,
  310. .remove = ata_platform_remove_one,
  311. .driver = {
  312. .name = DRV_NAME,
  313. .of_match_table = ahci_qoriq_of_match,
  314. .acpi_match_table = ahci_qoriq_acpi_match,
  315. .pm = &ahci_qoriq_pm_ops,
  316. },
  317. };
  318. module_platform_driver(ahci_qoriq_driver);
  319. MODULE_DESCRIPTION("Freescale QorIQ AHCI SATA platform driver");
  320. MODULE_AUTHOR("Tang Yuantian <Yuantian.Tang@freescale.com>");
  321. MODULE_LICENSE("GPL");