ahci_mtk.c 4.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * MediaTek AHCI SATA driver
  4. *
  5. * Copyright (c) 2017 MediaTek Inc.
  6. * Author: Ryder Lee <ryder.lee@mediatek.com>
  7. */
  8. #include <linux/ahci_platform.h>
  9. #include <linux/kernel.h>
  10. #include <linux/libata.h>
  11. #include <linux/mfd/syscon.h>
  12. #include <linux/module.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/pm.h>
  15. #include <linux/regmap.h>
  16. #include <linux/reset.h>
  17. #include "ahci.h"
  18. #define DRV_NAME "ahci-mtk"
  19. #define SYS_CFG 0x14
  20. #define SYS_CFG_SATA_MSK GENMASK(31, 30)
  21. #define SYS_CFG_SATA_EN BIT(31)
  22. struct mtk_ahci_plat {
  23. struct regmap *mode;
  24. struct reset_control *axi_rst;
  25. struct reset_control *sw_rst;
  26. struct reset_control *reg_rst;
  27. };
  28. static const struct ata_port_info ahci_port_info = {
  29. .flags = AHCI_FLAG_COMMON,
  30. .pio_mask = ATA_PIO4,
  31. .udma_mask = ATA_UDMA6,
  32. .port_ops = &ahci_platform_ops,
  33. };
  34. static struct scsi_host_template ahci_platform_sht = {
  35. AHCI_SHT(DRV_NAME),
  36. };
  37. static int mtk_ahci_platform_resets(struct ahci_host_priv *hpriv,
  38. struct device *dev)
  39. {
  40. struct mtk_ahci_plat *plat = hpriv->plat_data;
  41. int err;
  42. /* reset AXI bus and PHY part */
  43. plat->axi_rst = devm_reset_control_get_optional_exclusive(dev, "axi");
  44. if (PTR_ERR(plat->axi_rst) == -EPROBE_DEFER)
  45. return PTR_ERR(plat->axi_rst);
  46. plat->sw_rst = devm_reset_control_get_optional_exclusive(dev, "sw");
  47. if (PTR_ERR(plat->sw_rst) == -EPROBE_DEFER)
  48. return PTR_ERR(plat->sw_rst);
  49. plat->reg_rst = devm_reset_control_get_optional_exclusive(dev, "reg");
  50. if (PTR_ERR(plat->reg_rst) == -EPROBE_DEFER)
  51. return PTR_ERR(plat->reg_rst);
  52. err = reset_control_assert(plat->axi_rst);
  53. if (err) {
  54. dev_err(dev, "failed to assert AXI bus\n");
  55. return err;
  56. }
  57. err = reset_control_assert(plat->sw_rst);
  58. if (err) {
  59. dev_err(dev, "failed to assert PHY digital part\n");
  60. return err;
  61. }
  62. err = reset_control_assert(plat->reg_rst);
  63. if (err) {
  64. dev_err(dev, "failed to assert PHY register part\n");
  65. return err;
  66. }
  67. err = reset_control_deassert(plat->reg_rst);
  68. if (err) {
  69. dev_err(dev, "failed to deassert PHY register part\n");
  70. return err;
  71. }
  72. err = reset_control_deassert(plat->sw_rst);
  73. if (err) {
  74. dev_err(dev, "failed to deassert PHY digital part\n");
  75. return err;
  76. }
  77. err = reset_control_deassert(plat->axi_rst);
  78. if (err) {
  79. dev_err(dev, "failed to deassert AXI bus\n");
  80. return err;
  81. }
  82. return 0;
  83. }
  84. static int mtk_ahci_parse_property(struct ahci_host_priv *hpriv,
  85. struct device *dev)
  86. {
  87. struct mtk_ahci_plat *plat = hpriv->plat_data;
  88. struct device_node *np = dev->of_node;
  89. /* enable SATA function if needed */
  90. if (of_find_property(np, "mediatek,phy-mode", NULL)) {
  91. plat->mode = syscon_regmap_lookup_by_phandle(
  92. np, "mediatek,phy-mode");
  93. if (IS_ERR(plat->mode)) {
  94. dev_err(dev, "missing phy-mode phandle\n");
  95. return PTR_ERR(plat->mode);
  96. }
  97. regmap_update_bits(plat->mode, SYS_CFG, SYS_CFG_SATA_MSK,
  98. SYS_CFG_SATA_EN);
  99. }
  100. of_property_read_u32(np, "ports-implemented", &hpriv->force_port_map);
  101. return 0;
  102. }
  103. static int mtk_ahci_probe(struct platform_device *pdev)
  104. {
  105. struct device *dev = &pdev->dev;
  106. struct mtk_ahci_plat *plat;
  107. struct ahci_host_priv *hpriv;
  108. int err;
  109. plat = devm_kzalloc(dev, sizeof(*plat), GFP_KERNEL);
  110. if (!plat)
  111. return -ENOMEM;
  112. hpriv = ahci_platform_get_resources(pdev, 0);
  113. if (IS_ERR(hpriv))
  114. return PTR_ERR(hpriv);
  115. hpriv->plat_data = plat;
  116. err = mtk_ahci_parse_property(hpriv, dev);
  117. if (err)
  118. return err;
  119. err = mtk_ahci_platform_resets(hpriv, dev);
  120. if (err)
  121. return err;
  122. err = ahci_platform_enable_resources(hpriv);
  123. if (err)
  124. return err;
  125. err = ahci_platform_init_host(pdev, hpriv, &ahci_port_info,
  126. &ahci_platform_sht);
  127. if (err)
  128. goto disable_resources;
  129. return 0;
  130. disable_resources:
  131. ahci_platform_disable_resources(hpriv);
  132. return err;
  133. }
  134. static SIMPLE_DEV_PM_OPS(ahci_pm_ops, ahci_platform_suspend,
  135. ahci_platform_resume);
  136. static const struct of_device_id ahci_of_match[] = {
  137. { .compatible = "mediatek,mtk-ahci", },
  138. {},
  139. };
  140. MODULE_DEVICE_TABLE(of, ahci_of_match);
  141. static struct platform_driver mtk_ahci_driver = {
  142. .probe = mtk_ahci_probe,
  143. .remove = ata_platform_remove_one,
  144. .driver = {
  145. .name = DRV_NAME,
  146. .of_match_table = ahci_of_match,
  147. .pm = &ahci_pm_ops,
  148. },
  149. };
  150. module_platform_driver(mtk_ahci_driver);
  151. MODULE_DESCRIPTION("MediaTek SATA AHCI Driver");
  152. MODULE_LICENSE("GPL v2");