ahci_imx.c 33 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * copyright (c) 2013 Freescale Semiconductor, Inc.
  4. * Freescale IMX AHCI SATA platform driver
  5. *
  6. * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
  7. */
  8. #include <linux/kernel.h>
  9. #include <linux/module.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/regmap.h>
  12. #include <linux/ahci_platform.h>
  13. #include <linux/gpio/consumer.h>
  14. #include <linux/of_device.h>
  15. #include <linux/mfd/syscon.h>
  16. #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
  17. #include <linux/libata.h>
  18. #include <linux/hwmon.h>
  19. #include <linux/hwmon-sysfs.h>
  20. #include <linux/thermal.h>
  21. #include "ahci.h"
  22. #define DRV_NAME "ahci-imx"
  23. enum {
  24. /* Timer 1-ms Register */
  25. IMX_TIMER1MS = 0x00e0,
  26. /* Port0 PHY Control Register */
  27. IMX_P0PHYCR = 0x0178,
  28. IMX_P0PHYCR_TEST_PDDQ = 1 << 20,
  29. IMX_P0PHYCR_CR_READ = 1 << 19,
  30. IMX_P0PHYCR_CR_WRITE = 1 << 18,
  31. IMX_P0PHYCR_CR_CAP_DATA = 1 << 17,
  32. IMX_P0PHYCR_CR_CAP_ADDR = 1 << 16,
  33. /* Port0 PHY Status Register */
  34. IMX_P0PHYSR = 0x017c,
  35. IMX_P0PHYSR_CR_ACK = 1 << 18,
  36. IMX_P0PHYSR_CR_DATA_OUT = 0xffff << 0,
  37. /* Lane0 Output Status Register */
  38. IMX_LANE0_OUT_STAT = 0x2003,
  39. IMX_LANE0_OUT_STAT_RX_PLL_STATE = 1 << 1,
  40. /* Clock Reset Register */
  41. IMX_CLOCK_RESET = 0x7f3f,
  42. IMX_CLOCK_RESET_RESET = 1 << 0,
  43. /* IMX8QM HSIO AHCI definitions */
  44. IMX8QM_SATA_PHY_RX_IMPED_RATIO_OFFSET = 0x03,
  45. IMX8QM_SATA_PHY_TX_IMPED_RATIO_OFFSET = 0x09,
  46. IMX8QM_SATA_PHY_IMPED_RATIO_85OHM = 0x6c,
  47. IMX8QM_LPCG_PHYX2_OFFSET = 0x00000,
  48. IMX8QM_CSR_PHYX2_OFFSET = 0x90000,
  49. IMX8QM_CSR_PHYX1_OFFSET = 0xa0000,
  50. IMX8QM_CSR_PHYX_STTS0_OFFSET = 0x4,
  51. IMX8QM_CSR_PCIEA_OFFSET = 0xb0000,
  52. IMX8QM_CSR_PCIEB_OFFSET = 0xc0000,
  53. IMX8QM_CSR_SATA_OFFSET = 0xd0000,
  54. IMX8QM_CSR_PCIE_CTRL2_OFFSET = 0x8,
  55. IMX8QM_CSR_MISC_OFFSET = 0xe0000,
  56. IMX8QM_LPCG_PHYX2_PCLK0_MASK = (0x3 << 16),
  57. IMX8QM_LPCG_PHYX2_PCLK1_MASK = (0x3 << 20),
  58. IMX8QM_PHY_APB_RSTN_0 = BIT(0),
  59. IMX8QM_PHY_MODE_SATA = BIT(19),
  60. IMX8QM_PHY_MODE_MASK = (0xf << 17),
  61. IMX8QM_PHY_PIPE_RSTN_0 = BIT(24),
  62. IMX8QM_PHY_PIPE_RSTN_OVERRIDE_0 = BIT(25),
  63. IMX8QM_PHY_PIPE_RSTN_1 = BIT(26),
  64. IMX8QM_PHY_PIPE_RSTN_OVERRIDE_1 = BIT(27),
  65. IMX8QM_STTS0_LANE0_TX_PLL_LOCK = BIT(4),
  66. IMX8QM_MISC_IOB_RXENA = BIT(0),
  67. IMX8QM_MISC_IOB_TXENA = BIT(1),
  68. IMX8QM_MISC_PHYX1_EPCS_SEL = BIT(12),
  69. IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_1 = BIT(24),
  70. IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_0 = BIT(25),
  71. IMX8QM_MISC_CLKREQN_IN_OVERRIDE_1 = BIT(28),
  72. IMX8QM_MISC_CLKREQN_IN_OVERRIDE_0 = BIT(29),
  73. IMX8QM_SATA_CTRL_RESET_N = BIT(12),
  74. IMX8QM_SATA_CTRL_EPCS_PHYRESET_N = BIT(7),
  75. IMX8QM_CTRL_BUTTON_RST_N = BIT(21),
  76. IMX8QM_CTRL_POWER_UP_RST_N = BIT(23),
  77. IMX8QM_CTRL_LTSSM_ENABLE = BIT(4),
  78. };
  79. enum ahci_imx_type {
  80. AHCI_IMX53,
  81. AHCI_IMX6Q,
  82. AHCI_IMX6QP,
  83. AHCI_IMX8QM,
  84. };
  85. struct imx_ahci_priv {
  86. struct platform_device *ahci_pdev;
  87. enum ahci_imx_type type;
  88. struct clk *sata_clk;
  89. struct clk *sata_ref_clk;
  90. struct clk *ahb_clk;
  91. struct clk *epcs_tx_clk;
  92. struct clk *epcs_rx_clk;
  93. struct clk *phy_apbclk;
  94. struct clk *phy_pclk0;
  95. struct clk *phy_pclk1;
  96. void __iomem *phy_base;
  97. struct gpio_desc *clkreq_gpiod;
  98. struct regmap *gpr;
  99. bool no_device;
  100. bool first_time;
  101. u32 phy_params;
  102. u32 imped_ratio;
  103. };
  104. static int ahci_imx_hotplug;
  105. module_param_named(hotplug, ahci_imx_hotplug, int, 0644);
  106. MODULE_PARM_DESC(hotplug, "AHCI IMX hot-plug support (0=Don't support, 1=support)");
  107. static void ahci_imx_host_stop(struct ata_host *host);
  108. static int imx_phy_crbit_assert(void __iomem *mmio, u32 bit, bool assert)
  109. {
  110. int timeout = 10;
  111. u32 crval;
  112. u32 srval;
  113. /* Assert or deassert the bit */
  114. crval = readl(mmio + IMX_P0PHYCR);
  115. if (assert)
  116. crval |= bit;
  117. else
  118. crval &= ~bit;
  119. writel(crval, mmio + IMX_P0PHYCR);
  120. /* Wait for the cr_ack signal */
  121. do {
  122. srval = readl(mmio + IMX_P0PHYSR);
  123. if ((assert ? srval : ~srval) & IMX_P0PHYSR_CR_ACK)
  124. break;
  125. usleep_range(100, 200);
  126. } while (--timeout);
  127. return timeout ? 0 : -ETIMEDOUT;
  128. }
  129. static int imx_phy_reg_addressing(u16 addr, void __iomem *mmio)
  130. {
  131. u32 crval = addr;
  132. int ret;
  133. /* Supply the address on cr_data_in */
  134. writel(crval, mmio + IMX_P0PHYCR);
  135. /* Assert the cr_cap_addr signal */
  136. ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, true);
  137. if (ret)
  138. return ret;
  139. /* Deassert cr_cap_addr */
  140. ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, false);
  141. if (ret)
  142. return ret;
  143. return 0;
  144. }
  145. static int imx_phy_reg_write(u16 val, void __iomem *mmio)
  146. {
  147. u32 crval = val;
  148. int ret;
  149. /* Supply the data on cr_data_in */
  150. writel(crval, mmio + IMX_P0PHYCR);
  151. /* Assert the cr_cap_data signal */
  152. ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_DATA, true);
  153. if (ret)
  154. return ret;
  155. /* Deassert cr_cap_data */
  156. ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_DATA, false);
  157. if (ret)
  158. return ret;
  159. if (val & IMX_CLOCK_RESET_RESET) {
  160. /*
  161. * In case we're resetting the phy, it's unable to acknowledge,
  162. * so we return immediately here.
  163. */
  164. crval |= IMX_P0PHYCR_CR_WRITE;
  165. writel(crval, mmio + IMX_P0PHYCR);
  166. goto out;
  167. }
  168. /* Assert the cr_write signal */
  169. ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_WRITE, true);
  170. if (ret)
  171. return ret;
  172. /* Deassert cr_write */
  173. ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_WRITE, false);
  174. if (ret)
  175. return ret;
  176. out:
  177. return 0;
  178. }
  179. static int imx_phy_reg_read(u16 *val, void __iomem *mmio)
  180. {
  181. int ret;
  182. /* Assert the cr_read signal */
  183. ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_READ, true);
  184. if (ret)
  185. return ret;
  186. /* Capture the data from cr_data_out[] */
  187. *val = readl(mmio + IMX_P0PHYSR) & IMX_P0PHYSR_CR_DATA_OUT;
  188. /* Deassert cr_read */
  189. ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_READ, false);
  190. if (ret)
  191. return ret;
  192. return 0;
  193. }
  194. static int imx_sata_phy_reset(struct ahci_host_priv *hpriv)
  195. {
  196. struct imx_ahci_priv *imxpriv = hpriv->plat_data;
  197. void __iomem *mmio = hpriv->mmio;
  198. int timeout = 10;
  199. u16 val;
  200. int ret;
  201. if (imxpriv->type == AHCI_IMX6QP) {
  202. /* 6qp adds the sata reset mechanism, use it for 6qp sata */
  203. regmap_update_bits(imxpriv->gpr, IOMUXC_GPR5,
  204. IMX6Q_GPR5_SATA_SW_PD, 0);
  205. regmap_update_bits(imxpriv->gpr, IOMUXC_GPR5,
  206. IMX6Q_GPR5_SATA_SW_RST, 0);
  207. udelay(50);
  208. regmap_update_bits(imxpriv->gpr, IOMUXC_GPR5,
  209. IMX6Q_GPR5_SATA_SW_RST,
  210. IMX6Q_GPR5_SATA_SW_RST);
  211. return 0;
  212. }
  213. /* Reset SATA PHY by setting RESET bit of PHY register CLOCK_RESET */
  214. ret = imx_phy_reg_addressing(IMX_CLOCK_RESET, mmio);
  215. if (ret)
  216. return ret;
  217. ret = imx_phy_reg_write(IMX_CLOCK_RESET_RESET, mmio);
  218. if (ret)
  219. return ret;
  220. /* Wait for PHY RX_PLL to be stable */
  221. do {
  222. usleep_range(100, 200);
  223. ret = imx_phy_reg_addressing(IMX_LANE0_OUT_STAT, mmio);
  224. if (ret)
  225. return ret;
  226. ret = imx_phy_reg_read(&val, mmio);
  227. if (ret)
  228. return ret;
  229. if (val & IMX_LANE0_OUT_STAT_RX_PLL_STATE)
  230. break;
  231. } while (--timeout);
  232. return timeout ? 0 : -ETIMEDOUT;
  233. }
  234. enum {
  235. /* SATA PHY Register */
  236. SATA_PHY_CR_CLOCK_CRCMP_LT_LIMIT = 0x0001,
  237. SATA_PHY_CR_CLOCK_DAC_CTL = 0x0008,
  238. SATA_PHY_CR_CLOCK_RTUNE_CTL = 0x0009,
  239. SATA_PHY_CR_CLOCK_ADC_OUT = 0x000A,
  240. SATA_PHY_CR_CLOCK_MPLL_TST = 0x0017,
  241. };
  242. static int read_adc_sum(void *dev, u16 rtune_ctl_reg, void __iomem * mmio)
  243. {
  244. u16 adc_out_reg, read_sum;
  245. u32 index, read_attempt;
  246. const u32 attempt_limit = 200;
  247. imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_RTUNE_CTL, mmio);
  248. imx_phy_reg_write(rtune_ctl_reg, mmio);
  249. /* two dummy read */
  250. index = 0;
  251. read_attempt = 0;
  252. adc_out_reg = 0;
  253. imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_ADC_OUT, mmio);
  254. while (index < 2) {
  255. imx_phy_reg_read(&adc_out_reg, mmio);
  256. /* check if valid */
  257. if (adc_out_reg & 0x400)
  258. index++;
  259. read_attempt++;
  260. if (read_attempt > attempt_limit) {
  261. dev_err(dev, "Read REG more than %d times!\n",
  262. attempt_limit);
  263. break;
  264. }
  265. }
  266. index = 0;
  267. read_attempt = 0;
  268. read_sum = 0;
  269. while (index < 80) {
  270. imx_phy_reg_read(&adc_out_reg, mmio);
  271. if (adc_out_reg & 0x400) {
  272. read_sum = read_sum + (adc_out_reg & 0x3FF);
  273. index++;
  274. }
  275. read_attempt++;
  276. if (read_attempt > attempt_limit) {
  277. dev_err(dev, "Read REG more than %d times!\n",
  278. attempt_limit);
  279. break;
  280. }
  281. }
  282. /* Use the U32 to make 1000 precision */
  283. return (read_sum * 1000) / 80;
  284. }
  285. /* SATA AHCI temperature monitor */
  286. static int sata_ahci_read_temperature(void *dev, int *temp)
  287. {
  288. u16 mpll_test_reg, rtune_ctl_reg, dac_ctl_reg, read_sum;
  289. u32 str1, str2, str3, str4;
  290. int m1, m2, a;
  291. struct ahci_host_priv *hpriv = dev_get_drvdata(dev);
  292. void __iomem *mmio = hpriv->mmio;
  293. /* check rd-wr to reg */
  294. read_sum = 0;
  295. imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_CRCMP_LT_LIMIT, mmio);
  296. imx_phy_reg_write(read_sum, mmio);
  297. imx_phy_reg_read(&read_sum, mmio);
  298. if ((read_sum & 0xffff) != 0)
  299. dev_err(dev, "Read/Write REG error, 0x%x!\n", read_sum);
  300. imx_phy_reg_write(0x5A5A, mmio);
  301. imx_phy_reg_read(&read_sum, mmio);
  302. if ((read_sum & 0xffff) != 0x5A5A)
  303. dev_err(dev, "Read/Write REG error, 0x%x!\n", read_sum);
  304. imx_phy_reg_write(0x1234, mmio);
  305. imx_phy_reg_read(&read_sum, mmio);
  306. if ((read_sum & 0xffff) != 0x1234)
  307. dev_err(dev, "Read/Write REG error, 0x%x!\n", read_sum);
  308. /* start temperature test */
  309. imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_MPLL_TST, mmio);
  310. imx_phy_reg_read(&mpll_test_reg, mmio);
  311. imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_RTUNE_CTL, mmio);
  312. imx_phy_reg_read(&rtune_ctl_reg, mmio);
  313. imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_DAC_CTL, mmio);
  314. imx_phy_reg_read(&dac_ctl_reg, mmio);
  315. /* mpll_tst.meas_iv ([12:2]) */
  316. str1 = (mpll_test_reg >> 2) & 0x7FF;
  317. /* rtune_ctl.mode ([1:0]) */
  318. str2 = (rtune_ctl_reg) & 0x3;
  319. /* dac_ctl.dac_mode ([14:12]) */
  320. str3 = (dac_ctl_reg >> 12) & 0x7;
  321. /* rtune_ctl.sel_atbp ([4]) */
  322. str4 = (rtune_ctl_reg >> 4);
  323. /* Calculate the m1 */
  324. /* mpll_tst.meas_iv */
  325. mpll_test_reg = (mpll_test_reg & 0xE03) | (512) << 2;
  326. /* rtune_ctl.mode */
  327. rtune_ctl_reg = (rtune_ctl_reg & 0xFFC) | (1);
  328. /* dac_ctl.dac_mode */
  329. dac_ctl_reg = (dac_ctl_reg & 0x8FF) | (4) << 12;
  330. /* rtune_ctl.sel_atbp */
  331. rtune_ctl_reg = (rtune_ctl_reg & 0xFEF) | (0) << 4;
  332. imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_MPLL_TST, mmio);
  333. imx_phy_reg_write(mpll_test_reg, mmio);
  334. imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_DAC_CTL, mmio);
  335. imx_phy_reg_write(dac_ctl_reg, mmio);
  336. m1 = read_adc_sum(dev, rtune_ctl_reg, mmio);
  337. /* Calculate the m2 */
  338. /* rtune_ctl.sel_atbp */
  339. rtune_ctl_reg = (rtune_ctl_reg & 0xFEF) | (1) << 4;
  340. m2 = read_adc_sum(dev, rtune_ctl_reg, mmio);
  341. /* restore the status */
  342. /* mpll_tst.meas_iv */
  343. mpll_test_reg = (mpll_test_reg & 0xE03) | (str1) << 2;
  344. /* rtune_ctl.mode */
  345. rtune_ctl_reg = (rtune_ctl_reg & 0xFFC) | (str2);
  346. /* dac_ctl.dac_mode */
  347. dac_ctl_reg = (dac_ctl_reg & 0x8FF) | (str3) << 12;
  348. /* rtune_ctl.sel_atbp */
  349. rtune_ctl_reg = (rtune_ctl_reg & 0xFEF) | (str4) << 4;
  350. imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_MPLL_TST, mmio);
  351. imx_phy_reg_write(mpll_test_reg, mmio);
  352. imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_DAC_CTL, mmio);
  353. imx_phy_reg_write(dac_ctl_reg, mmio);
  354. imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_RTUNE_CTL, mmio);
  355. imx_phy_reg_write(rtune_ctl_reg, mmio);
  356. /* Compute temperature */
  357. if (!(m2 / 1000))
  358. m2 = 1000;
  359. a = (m2 - m1) / (m2/1000);
  360. *temp = ((-559) * a * a) / 1000 + (1379) * a + (-458000);
  361. return 0;
  362. }
  363. static ssize_t sata_ahci_show_temp(struct device *dev,
  364. struct device_attribute *da,
  365. char *buf)
  366. {
  367. unsigned int temp = 0;
  368. int err;
  369. err = sata_ahci_read_temperature(dev, &temp);
  370. if (err < 0)
  371. return err;
  372. return sprintf(buf, "%u\n", temp);
  373. }
  374. static const struct thermal_zone_of_device_ops fsl_sata_ahci_of_thermal_ops = {
  375. .get_temp = sata_ahci_read_temperature,
  376. };
  377. static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, sata_ahci_show_temp, NULL, 0);
  378. static struct attribute *fsl_sata_ahci_attrs[] = {
  379. &sensor_dev_attr_temp1_input.dev_attr.attr,
  380. NULL
  381. };
  382. ATTRIBUTE_GROUPS(fsl_sata_ahci);
  383. static int imx8_sata_enable(struct ahci_host_priv *hpriv)
  384. {
  385. u32 val, reg;
  386. int i, ret;
  387. struct imx_ahci_priv *imxpriv = hpriv->plat_data;
  388. struct device *dev = &imxpriv->ahci_pdev->dev;
  389. /* configure the hsio for sata */
  390. ret = clk_prepare_enable(imxpriv->phy_pclk0);
  391. if (ret < 0) {
  392. dev_err(dev, "can't enable phy_pclk0.\n");
  393. return ret;
  394. }
  395. ret = clk_prepare_enable(imxpriv->phy_pclk1);
  396. if (ret < 0) {
  397. dev_err(dev, "can't enable phy_pclk1.\n");
  398. goto disable_phy_pclk0;
  399. }
  400. ret = clk_prepare_enable(imxpriv->epcs_tx_clk);
  401. if (ret < 0) {
  402. dev_err(dev, "can't enable epcs_tx_clk.\n");
  403. goto disable_phy_pclk1;
  404. }
  405. ret = clk_prepare_enable(imxpriv->epcs_rx_clk);
  406. if (ret < 0) {
  407. dev_err(dev, "can't enable epcs_rx_clk.\n");
  408. goto disable_epcs_tx_clk;
  409. }
  410. ret = clk_prepare_enable(imxpriv->phy_apbclk);
  411. if (ret < 0) {
  412. dev_err(dev, "can't enable phy_apbclk.\n");
  413. goto disable_epcs_rx_clk;
  414. }
  415. /* Configure PHYx2 PIPE_RSTN */
  416. regmap_read(imxpriv->gpr, IMX8QM_CSR_PCIEA_OFFSET +
  417. IMX8QM_CSR_PCIE_CTRL2_OFFSET, &val);
  418. if ((val & IMX8QM_CTRL_LTSSM_ENABLE) == 0) {
  419. /* The link of the PCIEA of HSIO is down */
  420. regmap_update_bits(imxpriv->gpr,
  421. IMX8QM_CSR_PHYX2_OFFSET,
  422. IMX8QM_PHY_PIPE_RSTN_0 |
  423. IMX8QM_PHY_PIPE_RSTN_OVERRIDE_0,
  424. IMX8QM_PHY_PIPE_RSTN_0 |
  425. IMX8QM_PHY_PIPE_RSTN_OVERRIDE_0);
  426. }
  427. regmap_read(imxpriv->gpr, IMX8QM_CSR_PCIEB_OFFSET +
  428. IMX8QM_CSR_PCIE_CTRL2_OFFSET, &reg);
  429. if ((reg & IMX8QM_CTRL_LTSSM_ENABLE) == 0) {
  430. /* The link of the PCIEB of HSIO is down */
  431. regmap_update_bits(imxpriv->gpr,
  432. IMX8QM_CSR_PHYX2_OFFSET,
  433. IMX8QM_PHY_PIPE_RSTN_1 |
  434. IMX8QM_PHY_PIPE_RSTN_OVERRIDE_1,
  435. IMX8QM_PHY_PIPE_RSTN_1 |
  436. IMX8QM_PHY_PIPE_RSTN_OVERRIDE_1);
  437. }
  438. if (((reg | val) & IMX8QM_CTRL_LTSSM_ENABLE) == 0) {
  439. /* The links of both PCIA and PCIEB of HSIO are down */
  440. regmap_update_bits(imxpriv->gpr,
  441. IMX8QM_LPCG_PHYX2_OFFSET,
  442. IMX8QM_LPCG_PHYX2_PCLK0_MASK |
  443. IMX8QM_LPCG_PHYX2_PCLK1_MASK,
  444. 0);
  445. }
  446. /* set PWR_RST and BT_RST of csr_pciea */
  447. val = IMX8QM_CSR_PCIEA_OFFSET + IMX8QM_CSR_PCIE_CTRL2_OFFSET;
  448. regmap_update_bits(imxpriv->gpr,
  449. val,
  450. IMX8QM_CTRL_BUTTON_RST_N,
  451. IMX8QM_CTRL_BUTTON_RST_N);
  452. regmap_update_bits(imxpriv->gpr,
  453. val,
  454. IMX8QM_CTRL_POWER_UP_RST_N,
  455. IMX8QM_CTRL_POWER_UP_RST_N);
  456. /* PHYX1_MODE to SATA */
  457. regmap_update_bits(imxpriv->gpr,
  458. IMX8QM_CSR_PHYX1_OFFSET,
  459. IMX8QM_PHY_MODE_MASK,
  460. IMX8QM_PHY_MODE_SATA);
  461. /*
  462. * BIT0 RXENA 1, BIT1 TXENA 0
  463. * BIT12 PHY_X1_EPCS_SEL 1.
  464. */
  465. regmap_update_bits(imxpriv->gpr,
  466. IMX8QM_CSR_MISC_OFFSET,
  467. IMX8QM_MISC_IOB_RXENA,
  468. IMX8QM_MISC_IOB_RXENA);
  469. regmap_update_bits(imxpriv->gpr,
  470. IMX8QM_CSR_MISC_OFFSET,
  471. IMX8QM_MISC_IOB_TXENA,
  472. 0);
  473. regmap_update_bits(imxpriv->gpr,
  474. IMX8QM_CSR_MISC_OFFSET,
  475. IMX8QM_MISC_PHYX1_EPCS_SEL,
  476. IMX8QM_MISC_PHYX1_EPCS_SEL);
  477. /*
  478. * It is possible, for PCIe and SATA are sharing
  479. * the same clock source, HPLL or external oscillator.
  480. * When PCIe is in low power modes (L1.X or L2 etc),
  481. * the clock source can be turned off. In this case,
  482. * if this clock source is required to be toggling by
  483. * SATA, then SATA functions will be abnormal.
  484. * Set the override here to avoid it.
  485. */
  486. regmap_update_bits(imxpriv->gpr,
  487. IMX8QM_CSR_MISC_OFFSET,
  488. IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_1 |
  489. IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_0 |
  490. IMX8QM_MISC_CLKREQN_IN_OVERRIDE_1 |
  491. IMX8QM_MISC_CLKREQN_IN_OVERRIDE_0,
  492. IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_1 |
  493. IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_0 |
  494. IMX8QM_MISC_CLKREQN_IN_OVERRIDE_1 |
  495. IMX8QM_MISC_CLKREQN_IN_OVERRIDE_0);
  496. /* clear PHY RST, then set it */
  497. regmap_update_bits(imxpriv->gpr,
  498. IMX8QM_CSR_SATA_OFFSET,
  499. IMX8QM_SATA_CTRL_EPCS_PHYRESET_N,
  500. 0);
  501. regmap_update_bits(imxpriv->gpr,
  502. IMX8QM_CSR_SATA_OFFSET,
  503. IMX8QM_SATA_CTRL_EPCS_PHYRESET_N,
  504. IMX8QM_SATA_CTRL_EPCS_PHYRESET_N);
  505. /* CTRL RST: SET -> delay 1 us -> CLEAR -> SET */
  506. regmap_update_bits(imxpriv->gpr,
  507. IMX8QM_CSR_SATA_OFFSET,
  508. IMX8QM_SATA_CTRL_RESET_N,
  509. IMX8QM_SATA_CTRL_RESET_N);
  510. udelay(1);
  511. regmap_update_bits(imxpriv->gpr,
  512. IMX8QM_CSR_SATA_OFFSET,
  513. IMX8QM_SATA_CTRL_RESET_N,
  514. 0);
  515. regmap_update_bits(imxpriv->gpr,
  516. IMX8QM_CSR_SATA_OFFSET,
  517. IMX8QM_SATA_CTRL_RESET_N,
  518. IMX8QM_SATA_CTRL_RESET_N);
  519. /* APB reset */
  520. regmap_update_bits(imxpriv->gpr,
  521. IMX8QM_CSR_PHYX1_OFFSET,
  522. IMX8QM_PHY_APB_RSTN_0,
  523. IMX8QM_PHY_APB_RSTN_0);
  524. for (i = 0; i < 100; i++) {
  525. reg = IMX8QM_CSR_PHYX1_OFFSET +
  526. IMX8QM_CSR_PHYX_STTS0_OFFSET;
  527. regmap_read(imxpriv->gpr, reg, &val);
  528. val &= IMX8QM_STTS0_LANE0_TX_PLL_LOCK;
  529. if (val == IMX8QM_STTS0_LANE0_TX_PLL_LOCK)
  530. break;
  531. udelay(1);
  532. }
  533. if (val != IMX8QM_STTS0_LANE0_TX_PLL_LOCK) {
  534. dev_err(dev, "TX PLL of the PHY is not locked\n");
  535. ret = -ENODEV;
  536. } else {
  537. writeb(imxpriv->imped_ratio, imxpriv->phy_base +
  538. IMX8QM_SATA_PHY_RX_IMPED_RATIO_OFFSET);
  539. writeb(imxpriv->imped_ratio, imxpriv->phy_base +
  540. IMX8QM_SATA_PHY_TX_IMPED_RATIO_OFFSET);
  541. reg = readb(imxpriv->phy_base +
  542. IMX8QM_SATA_PHY_RX_IMPED_RATIO_OFFSET);
  543. if (unlikely(reg != imxpriv->imped_ratio))
  544. dev_info(dev, "Can't set PHY RX impedance ratio.\n");
  545. reg = readb(imxpriv->phy_base +
  546. IMX8QM_SATA_PHY_TX_IMPED_RATIO_OFFSET);
  547. if (unlikely(reg != imxpriv->imped_ratio))
  548. dev_info(dev, "Can't set PHY TX impedance ratio.\n");
  549. usleep_range(50, 100);
  550. /*
  551. * To reduce the power consumption, gate off
  552. * the PHY clks
  553. */
  554. clk_disable_unprepare(imxpriv->phy_apbclk);
  555. clk_disable_unprepare(imxpriv->phy_pclk1);
  556. clk_disable_unprepare(imxpriv->phy_pclk0);
  557. return ret;
  558. }
  559. clk_disable_unprepare(imxpriv->phy_apbclk);
  560. disable_epcs_rx_clk:
  561. clk_disable_unprepare(imxpriv->epcs_rx_clk);
  562. disable_epcs_tx_clk:
  563. clk_disable_unprepare(imxpriv->epcs_tx_clk);
  564. disable_phy_pclk1:
  565. clk_disable_unprepare(imxpriv->phy_pclk1);
  566. disable_phy_pclk0:
  567. clk_disable_unprepare(imxpriv->phy_pclk0);
  568. return ret;
  569. }
  570. static int imx_sata_enable(struct ahci_host_priv *hpriv)
  571. {
  572. struct imx_ahci_priv *imxpriv = hpriv->plat_data;
  573. struct device *dev = &imxpriv->ahci_pdev->dev;
  574. int ret;
  575. if (imxpriv->no_device)
  576. return 0;
  577. ret = ahci_platform_enable_regulators(hpriv);
  578. if (ret)
  579. return ret;
  580. ret = clk_prepare_enable(imxpriv->sata_ref_clk);
  581. if (ret < 0)
  582. goto disable_regulator;
  583. if (imxpriv->type == AHCI_IMX6Q || imxpriv->type == AHCI_IMX6QP) {
  584. /*
  585. * set PHY Paremeters, two steps to configure the GPR13,
  586. * one write for rest of parameters, mask of first write
  587. * is 0x07ffffff, and the other one write for setting
  588. * the mpll_clk_en.
  589. */
  590. regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
  591. IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK |
  592. IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK |
  593. IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK |
  594. IMX6Q_GPR13_SATA_SPD_MODE_MASK |
  595. IMX6Q_GPR13_SATA_MPLL_SS_EN |
  596. IMX6Q_GPR13_SATA_TX_ATTEN_MASK |
  597. IMX6Q_GPR13_SATA_TX_BOOST_MASK |
  598. IMX6Q_GPR13_SATA_TX_LVL_MASK |
  599. IMX6Q_GPR13_SATA_MPLL_CLK_EN |
  600. IMX6Q_GPR13_SATA_TX_EDGE_RATE,
  601. imxpriv->phy_params);
  602. regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
  603. IMX6Q_GPR13_SATA_MPLL_CLK_EN,
  604. IMX6Q_GPR13_SATA_MPLL_CLK_EN);
  605. usleep_range(100, 200);
  606. ret = imx_sata_phy_reset(hpriv);
  607. if (ret) {
  608. dev_err(dev, "failed to reset phy: %d\n", ret);
  609. goto disable_clk;
  610. }
  611. } else if (imxpriv->type == AHCI_IMX8QM) {
  612. ret = imx8_sata_enable(hpriv);
  613. }
  614. usleep_range(1000, 2000);
  615. return 0;
  616. disable_clk:
  617. clk_disable_unprepare(imxpriv->sata_ref_clk);
  618. disable_regulator:
  619. ahci_platform_disable_regulators(hpriv);
  620. return ret;
  621. }
  622. static void imx_sata_disable(struct ahci_host_priv *hpriv)
  623. {
  624. struct imx_ahci_priv *imxpriv = hpriv->plat_data;
  625. if (imxpriv->no_device)
  626. return;
  627. switch (imxpriv->type) {
  628. case AHCI_IMX6QP:
  629. regmap_update_bits(imxpriv->gpr, IOMUXC_GPR5,
  630. IMX6Q_GPR5_SATA_SW_PD,
  631. IMX6Q_GPR5_SATA_SW_PD);
  632. regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
  633. IMX6Q_GPR13_SATA_MPLL_CLK_EN,
  634. !IMX6Q_GPR13_SATA_MPLL_CLK_EN);
  635. break;
  636. case AHCI_IMX6Q:
  637. regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
  638. IMX6Q_GPR13_SATA_MPLL_CLK_EN,
  639. !IMX6Q_GPR13_SATA_MPLL_CLK_EN);
  640. break;
  641. case AHCI_IMX8QM:
  642. clk_disable_unprepare(imxpriv->epcs_rx_clk);
  643. clk_disable_unprepare(imxpriv->epcs_tx_clk);
  644. break;
  645. default:
  646. break;
  647. }
  648. clk_disable_unprepare(imxpriv->sata_ref_clk);
  649. ahci_platform_disable_regulators(hpriv);
  650. }
  651. static void ahci_imx_error_handler(struct ata_port *ap)
  652. {
  653. u32 reg_val;
  654. struct ata_device *dev;
  655. struct ata_host *host = dev_get_drvdata(ap->dev);
  656. struct ahci_host_priv *hpriv = host->private_data;
  657. void __iomem *mmio = hpriv->mmio;
  658. struct imx_ahci_priv *imxpriv = hpriv->plat_data;
  659. ahci_error_handler(ap);
  660. if (!(imxpriv->first_time) || ahci_imx_hotplug)
  661. return;
  662. imxpriv->first_time = false;
  663. ata_for_each_dev(dev, &ap->link, ENABLED)
  664. return;
  665. /*
  666. * Disable link to save power. An imx ahci port can't be recovered
  667. * without full reset once the pddq mode is enabled making it
  668. * impossible to use as part of libata LPM.
  669. */
  670. reg_val = readl(mmio + IMX_P0PHYCR);
  671. writel(reg_val | IMX_P0PHYCR_TEST_PDDQ, mmio + IMX_P0PHYCR);
  672. imx_sata_disable(hpriv);
  673. imxpriv->no_device = true;
  674. dev_info(ap->dev, "no device found, disabling link.\n");
  675. dev_info(ap->dev, "pass " MODULE_PARAM_PREFIX ".hotplug=1 to enable hotplug\n");
  676. }
  677. static int ahci_imx_softreset(struct ata_link *link, unsigned int *class,
  678. unsigned long deadline)
  679. {
  680. struct ata_port *ap = link->ap;
  681. struct ata_host *host = dev_get_drvdata(ap->dev);
  682. struct ahci_host_priv *hpriv = host->private_data;
  683. struct imx_ahci_priv *imxpriv = hpriv->plat_data;
  684. int ret;
  685. if (imxpriv->type == AHCI_IMX53)
  686. ret = ahci_pmp_retry_srst_ops.softreset(link, class, deadline);
  687. else
  688. ret = ahci_ops.softreset(link, class, deadline);
  689. return ret;
  690. }
  691. static struct ata_port_operations ahci_imx_ops = {
  692. .inherits = &ahci_ops,
  693. .host_stop = ahci_imx_host_stop,
  694. .error_handler = ahci_imx_error_handler,
  695. .softreset = ahci_imx_softreset,
  696. };
  697. static const struct ata_port_info ahci_imx_port_info = {
  698. .flags = AHCI_FLAG_COMMON,
  699. .pio_mask = ATA_PIO4,
  700. .udma_mask = ATA_UDMA6,
  701. .port_ops = &ahci_imx_ops,
  702. };
  703. static const struct of_device_id imx_ahci_of_match[] = {
  704. { .compatible = "fsl,imx53-ahci", .data = (void *)AHCI_IMX53 },
  705. { .compatible = "fsl,imx6q-ahci", .data = (void *)AHCI_IMX6Q },
  706. { .compatible = "fsl,imx6qp-ahci", .data = (void *)AHCI_IMX6QP },
  707. { .compatible = "fsl,imx8qm-ahci", .data = (void *)AHCI_IMX8QM },
  708. {},
  709. };
  710. MODULE_DEVICE_TABLE(of, imx_ahci_of_match);
  711. struct reg_value {
  712. u32 of_value;
  713. u32 reg_value;
  714. };
  715. struct reg_property {
  716. const char *name;
  717. const struct reg_value *values;
  718. size_t num_values;
  719. u32 def_value;
  720. u32 set_value;
  721. };
  722. static const struct reg_value gpr13_tx_level[] = {
  723. { 937, IMX6Q_GPR13_SATA_TX_LVL_0_937_V },
  724. { 947, IMX6Q_GPR13_SATA_TX_LVL_0_947_V },
  725. { 957, IMX6Q_GPR13_SATA_TX_LVL_0_957_V },
  726. { 966, IMX6Q_GPR13_SATA_TX_LVL_0_966_V },
  727. { 976, IMX6Q_GPR13_SATA_TX_LVL_0_976_V },
  728. { 986, IMX6Q_GPR13_SATA_TX_LVL_0_986_V },
  729. { 996, IMX6Q_GPR13_SATA_TX_LVL_0_996_V },
  730. { 1005, IMX6Q_GPR13_SATA_TX_LVL_1_005_V },
  731. { 1015, IMX6Q_GPR13_SATA_TX_LVL_1_015_V },
  732. { 1025, IMX6Q_GPR13_SATA_TX_LVL_1_025_V },
  733. { 1035, IMX6Q_GPR13_SATA_TX_LVL_1_035_V },
  734. { 1045, IMX6Q_GPR13_SATA_TX_LVL_1_045_V },
  735. { 1054, IMX6Q_GPR13_SATA_TX_LVL_1_054_V },
  736. { 1064, IMX6Q_GPR13_SATA_TX_LVL_1_064_V },
  737. { 1074, IMX6Q_GPR13_SATA_TX_LVL_1_074_V },
  738. { 1084, IMX6Q_GPR13_SATA_TX_LVL_1_084_V },
  739. { 1094, IMX6Q_GPR13_SATA_TX_LVL_1_094_V },
  740. { 1104, IMX6Q_GPR13_SATA_TX_LVL_1_104_V },
  741. { 1113, IMX6Q_GPR13_SATA_TX_LVL_1_113_V },
  742. { 1123, IMX6Q_GPR13_SATA_TX_LVL_1_123_V },
  743. { 1133, IMX6Q_GPR13_SATA_TX_LVL_1_133_V },
  744. { 1143, IMX6Q_GPR13_SATA_TX_LVL_1_143_V },
  745. { 1152, IMX6Q_GPR13_SATA_TX_LVL_1_152_V },
  746. { 1162, IMX6Q_GPR13_SATA_TX_LVL_1_162_V },
  747. { 1172, IMX6Q_GPR13_SATA_TX_LVL_1_172_V },
  748. { 1182, IMX6Q_GPR13_SATA_TX_LVL_1_182_V },
  749. { 1191, IMX6Q_GPR13_SATA_TX_LVL_1_191_V },
  750. { 1201, IMX6Q_GPR13_SATA_TX_LVL_1_201_V },
  751. { 1211, IMX6Q_GPR13_SATA_TX_LVL_1_211_V },
  752. { 1221, IMX6Q_GPR13_SATA_TX_LVL_1_221_V },
  753. { 1230, IMX6Q_GPR13_SATA_TX_LVL_1_230_V },
  754. { 1240, IMX6Q_GPR13_SATA_TX_LVL_1_240_V }
  755. };
  756. static const struct reg_value gpr13_tx_boost[] = {
  757. { 0, IMX6Q_GPR13_SATA_TX_BOOST_0_00_DB },
  758. { 370, IMX6Q_GPR13_SATA_TX_BOOST_0_37_DB },
  759. { 740, IMX6Q_GPR13_SATA_TX_BOOST_0_74_DB },
  760. { 1110, IMX6Q_GPR13_SATA_TX_BOOST_1_11_DB },
  761. { 1480, IMX6Q_GPR13_SATA_TX_BOOST_1_48_DB },
  762. { 1850, IMX6Q_GPR13_SATA_TX_BOOST_1_85_DB },
  763. { 2220, IMX6Q_GPR13_SATA_TX_BOOST_2_22_DB },
  764. { 2590, IMX6Q_GPR13_SATA_TX_BOOST_2_59_DB },
  765. { 2960, IMX6Q_GPR13_SATA_TX_BOOST_2_96_DB },
  766. { 3330, IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB },
  767. { 3700, IMX6Q_GPR13_SATA_TX_BOOST_3_70_DB },
  768. { 4070, IMX6Q_GPR13_SATA_TX_BOOST_4_07_DB },
  769. { 4440, IMX6Q_GPR13_SATA_TX_BOOST_4_44_DB },
  770. { 4810, IMX6Q_GPR13_SATA_TX_BOOST_4_81_DB },
  771. { 5280, IMX6Q_GPR13_SATA_TX_BOOST_5_28_DB },
  772. { 5750, IMX6Q_GPR13_SATA_TX_BOOST_5_75_DB }
  773. };
  774. static const struct reg_value gpr13_tx_atten[] = {
  775. { 8, IMX6Q_GPR13_SATA_TX_ATTEN_8_16 },
  776. { 9, IMX6Q_GPR13_SATA_TX_ATTEN_9_16 },
  777. { 10, IMX6Q_GPR13_SATA_TX_ATTEN_10_16 },
  778. { 12, IMX6Q_GPR13_SATA_TX_ATTEN_12_16 },
  779. { 14, IMX6Q_GPR13_SATA_TX_ATTEN_14_16 },
  780. { 16, IMX6Q_GPR13_SATA_TX_ATTEN_16_16 },
  781. };
  782. static const struct reg_value gpr13_rx_eq[] = {
  783. { 500, IMX6Q_GPR13_SATA_RX_EQ_VAL_0_5_DB },
  784. { 1000, IMX6Q_GPR13_SATA_RX_EQ_VAL_1_0_DB },
  785. { 1500, IMX6Q_GPR13_SATA_RX_EQ_VAL_1_5_DB },
  786. { 2000, IMX6Q_GPR13_SATA_RX_EQ_VAL_2_0_DB },
  787. { 2500, IMX6Q_GPR13_SATA_RX_EQ_VAL_2_5_DB },
  788. { 3000, IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB },
  789. { 3500, IMX6Q_GPR13_SATA_RX_EQ_VAL_3_5_DB },
  790. { 4000, IMX6Q_GPR13_SATA_RX_EQ_VAL_4_0_DB },
  791. };
  792. static const struct reg_property gpr13_props[] = {
  793. {
  794. .name = "fsl,transmit-level-mV",
  795. .values = gpr13_tx_level,
  796. .num_values = ARRAY_SIZE(gpr13_tx_level),
  797. .def_value = IMX6Q_GPR13_SATA_TX_LVL_1_025_V,
  798. }, {
  799. .name = "fsl,transmit-boost-mdB",
  800. .values = gpr13_tx_boost,
  801. .num_values = ARRAY_SIZE(gpr13_tx_boost),
  802. .def_value = IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB,
  803. }, {
  804. .name = "fsl,transmit-atten-16ths",
  805. .values = gpr13_tx_atten,
  806. .num_values = ARRAY_SIZE(gpr13_tx_atten),
  807. .def_value = IMX6Q_GPR13_SATA_TX_ATTEN_9_16,
  808. }, {
  809. .name = "fsl,receive-eq-mdB",
  810. .values = gpr13_rx_eq,
  811. .num_values = ARRAY_SIZE(gpr13_rx_eq),
  812. .def_value = IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB,
  813. }, {
  814. .name = "fsl,no-spread-spectrum",
  815. .def_value = IMX6Q_GPR13_SATA_MPLL_SS_EN,
  816. .set_value = 0,
  817. },
  818. };
  819. static u32 imx_ahci_parse_props(struct device *dev,
  820. const struct reg_property *prop, size_t num)
  821. {
  822. struct device_node *np = dev->of_node;
  823. u32 reg_value = 0;
  824. int i, j;
  825. for (i = 0; i < num; i++, prop++) {
  826. u32 of_val;
  827. if (prop->num_values == 0) {
  828. if (of_property_read_bool(np, prop->name))
  829. reg_value |= prop->set_value;
  830. else
  831. reg_value |= prop->def_value;
  832. continue;
  833. }
  834. if (of_property_read_u32(np, prop->name, &of_val)) {
  835. dev_info(dev, "%s not specified, using %08x\n",
  836. prop->name, prop->def_value);
  837. reg_value |= prop->def_value;
  838. continue;
  839. }
  840. for (j = 0; j < prop->num_values; j++) {
  841. if (prop->values[j].of_value == of_val) {
  842. dev_info(dev, "%s value %u, using %08x\n",
  843. prop->name, of_val, prop->values[j].reg_value);
  844. reg_value |= prop->values[j].reg_value;
  845. break;
  846. }
  847. }
  848. if (j == prop->num_values) {
  849. dev_err(dev, "DT property %s is not a valid value\n",
  850. prop->name);
  851. reg_value |= prop->def_value;
  852. }
  853. }
  854. return reg_value;
  855. }
  856. static struct scsi_host_template ahci_platform_sht = {
  857. AHCI_SHT(DRV_NAME),
  858. };
  859. static int imx8_sata_probe(struct device *dev, struct imx_ahci_priv *imxpriv)
  860. {
  861. struct resource *phy_res;
  862. struct platform_device *pdev = imxpriv->ahci_pdev;
  863. struct device_node *np = dev->of_node;
  864. if (of_property_read_u32(np, "fsl,phy-imp", &imxpriv->imped_ratio))
  865. imxpriv->imped_ratio = IMX8QM_SATA_PHY_IMPED_RATIO_85OHM;
  866. phy_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
  867. if (phy_res) {
  868. imxpriv->phy_base = devm_ioremap(dev, phy_res->start,
  869. resource_size(phy_res));
  870. if (!imxpriv->phy_base) {
  871. dev_err(dev, "error with ioremap\n");
  872. return -ENOMEM;
  873. }
  874. } else {
  875. dev_err(dev, "missing *phy* reg region.\n");
  876. return -ENOMEM;
  877. }
  878. imxpriv->gpr =
  879. syscon_regmap_lookup_by_phandle(np, "hsio");
  880. if (IS_ERR(imxpriv->gpr)) {
  881. dev_err(dev, "unable to find gpr registers\n");
  882. return PTR_ERR(imxpriv->gpr);
  883. }
  884. imxpriv->epcs_tx_clk = devm_clk_get(dev, "epcs_tx");
  885. if (IS_ERR(imxpriv->epcs_tx_clk)) {
  886. dev_err(dev, "can't get epcs_tx_clk clock.\n");
  887. return PTR_ERR(imxpriv->epcs_tx_clk);
  888. }
  889. imxpriv->epcs_rx_clk = devm_clk_get(dev, "epcs_rx");
  890. if (IS_ERR(imxpriv->epcs_rx_clk)) {
  891. dev_err(dev, "can't get epcs_rx_clk clock.\n");
  892. return PTR_ERR(imxpriv->epcs_rx_clk);
  893. }
  894. imxpriv->phy_pclk0 = devm_clk_get(dev, "phy_pclk0");
  895. if (IS_ERR(imxpriv->phy_pclk0)) {
  896. dev_err(dev, "can't get phy_pclk0 clock.\n");
  897. return PTR_ERR(imxpriv->phy_pclk0);
  898. }
  899. imxpriv->phy_pclk1 = devm_clk_get(dev, "phy_pclk1");
  900. if (IS_ERR(imxpriv->phy_pclk1)) {
  901. dev_err(dev, "can't get phy_pclk1 clock.\n");
  902. return PTR_ERR(imxpriv->phy_pclk1);
  903. }
  904. imxpriv->phy_apbclk = devm_clk_get(dev, "phy_apbclk");
  905. if (IS_ERR(imxpriv->phy_apbclk)) {
  906. dev_err(dev, "can't get phy_apbclk clock.\n");
  907. return PTR_ERR(imxpriv->phy_apbclk);
  908. }
  909. /* Fetch GPIO, then enable the external OSC */
  910. imxpriv->clkreq_gpiod = devm_gpiod_get_optional(dev, "clkreq",
  911. GPIOD_OUT_LOW | GPIOD_FLAGS_BIT_NONEXCLUSIVE);
  912. if (IS_ERR(imxpriv->clkreq_gpiod))
  913. return PTR_ERR(imxpriv->clkreq_gpiod);
  914. if (imxpriv->clkreq_gpiod)
  915. gpiod_set_consumer_name(imxpriv->clkreq_gpiod, "SATA CLKREQ");
  916. return 0;
  917. }
  918. static int imx_ahci_probe(struct platform_device *pdev)
  919. {
  920. struct device *dev = &pdev->dev;
  921. const struct of_device_id *of_id;
  922. struct ahci_host_priv *hpriv;
  923. struct imx_ahci_priv *imxpriv;
  924. unsigned int reg_val;
  925. int ret;
  926. of_id = of_match_device(imx_ahci_of_match, dev);
  927. if (!of_id)
  928. return -EINVAL;
  929. imxpriv = devm_kzalloc(dev, sizeof(*imxpriv), GFP_KERNEL);
  930. if (!imxpriv)
  931. return -ENOMEM;
  932. imxpriv->ahci_pdev = pdev;
  933. imxpriv->no_device = false;
  934. imxpriv->first_time = true;
  935. imxpriv->type = (enum ahci_imx_type)of_id->data;
  936. imxpriv->sata_clk = devm_clk_get(dev, "sata");
  937. if (IS_ERR(imxpriv->sata_clk)) {
  938. dev_err(dev, "can't get sata clock.\n");
  939. return PTR_ERR(imxpriv->sata_clk);
  940. }
  941. imxpriv->sata_ref_clk = devm_clk_get(dev, "sata_ref");
  942. if (IS_ERR(imxpriv->sata_ref_clk)) {
  943. dev_err(dev, "can't get sata_ref clock.\n");
  944. return PTR_ERR(imxpriv->sata_ref_clk);
  945. }
  946. imxpriv->ahb_clk = devm_clk_get(dev, "ahb");
  947. if (IS_ERR(imxpriv->ahb_clk)) {
  948. dev_err(dev, "can't get ahb clock.\n");
  949. return PTR_ERR(imxpriv->ahb_clk);
  950. }
  951. if (imxpriv->type == AHCI_IMX6Q || imxpriv->type == AHCI_IMX6QP) {
  952. u32 reg_value;
  953. imxpriv->gpr = syscon_regmap_lookup_by_compatible(
  954. "fsl,imx6q-iomuxc-gpr");
  955. if (IS_ERR(imxpriv->gpr)) {
  956. dev_err(dev,
  957. "failed to find fsl,imx6q-iomux-gpr regmap\n");
  958. return PTR_ERR(imxpriv->gpr);
  959. }
  960. reg_value = imx_ahci_parse_props(dev, gpr13_props,
  961. ARRAY_SIZE(gpr13_props));
  962. imxpriv->phy_params =
  963. IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M |
  964. IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F |
  965. IMX6Q_GPR13_SATA_SPD_MODE_3P0G |
  966. reg_value;
  967. } else if (imxpriv->type == AHCI_IMX8QM) {
  968. ret = imx8_sata_probe(dev, imxpriv);
  969. if (ret)
  970. return ret;
  971. }
  972. hpriv = ahci_platform_get_resources(pdev, 0);
  973. if (IS_ERR(hpriv))
  974. return PTR_ERR(hpriv);
  975. hpriv->plat_data = imxpriv;
  976. ret = clk_prepare_enable(imxpriv->sata_clk);
  977. if (ret)
  978. return ret;
  979. if (imxpriv->type == AHCI_IMX53 &&
  980. IS_ENABLED(CONFIG_HWMON)) {
  981. /* Add the temperature monitor */
  982. struct device *hwmon_dev;
  983. hwmon_dev =
  984. devm_hwmon_device_register_with_groups(dev,
  985. "sata_ahci",
  986. hpriv,
  987. fsl_sata_ahci_groups);
  988. if (IS_ERR(hwmon_dev)) {
  989. ret = PTR_ERR(hwmon_dev);
  990. goto disable_clk;
  991. }
  992. devm_thermal_zone_of_sensor_register(hwmon_dev, 0, hwmon_dev,
  993. &fsl_sata_ahci_of_thermal_ops);
  994. dev_info(dev, "%s: sensor 'sata_ahci'\n", dev_name(hwmon_dev));
  995. }
  996. ret = imx_sata_enable(hpriv);
  997. if (ret)
  998. goto disable_clk;
  999. /*
  1000. * Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL,
  1001. * and IP vendor specific register IMX_TIMER1MS.
  1002. * Configure CAP_SSS (support stagered spin up).
  1003. * Implement the port0.
  1004. * Get the ahb clock rate, and configure the TIMER1MS register.
  1005. */
  1006. reg_val = readl(hpriv->mmio + HOST_CAP);
  1007. if (!(reg_val & HOST_CAP_SSS)) {
  1008. reg_val |= HOST_CAP_SSS;
  1009. writel(reg_val, hpriv->mmio + HOST_CAP);
  1010. }
  1011. reg_val = readl(hpriv->mmio + HOST_PORTS_IMPL);
  1012. if (!(reg_val & 0x1)) {
  1013. reg_val |= 0x1;
  1014. writel(reg_val, hpriv->mmio + HOST_PORTS_IMPL);
  1015. }
  1016. reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000;
  1017. writel(reg_val, hpriv->mmio + IMX_TIMER1MS);
  1018. ret = ahci_platform_init_host(pdev, hpriv, &ahci_imx_port_info,
  1019. &ahci_platform_sht);
  1020. if (ret)
  1021. goto disable_sata;
  1022. return 0;
  1023. disable_sata:
  1024. imx_sata_disable(hpriv);
  1025. disable_clk:
  1026. clk_disable_unprepare(imxpriv->sata_clk);
  1027. return ret;
  1028. }
  1029. static void ahci_imx_host_stop(struct ata_host *host)
  1030. {
  1031. struct ahci_host_priv *hpriv = host->private_data;
  1032. struct imx_ahci_priv *imxpriv = hpriv->plat_data;
  1033. imx_sata_disable(hpriv);
  1034. clk_disable_unprepare(imxpriv->sata_clk);
  1035. }
  1036. #ifdef CONFIG_PM_SLEEP
  1037. static int imx_ahci_suspend(struct device *dev)
  1038. {
  1039. struct ata_host *host = dev_get_drvdata(dev);
  1040. struct ahci_host_priv *hpriv = host->private_data;
  1041. int ret;
  1042. ret = ahci_platform_suspend_host(dev);
  1043. if (ret)
  1044. return ret;
  1045. imx_sata_disable(hpriv);
  1046. return 0;
  1047. }
  1048. static int imx_ahci_resume(struct device *dev)
  1049. {
  1050. struct ata_host *host = dev_get_drvdata(dev);
  1051. struct ahci_host_priv *hpriv = host->private_data;
  1052. int ret;
  1053. ret = imx_sata_enable(hpriv);
  1054. if (ret)
  1055. return ret;
  1056. return ahci_platform_resume_host(dev);
  1057. }
  1058. #endif
  1059. static SIMPLE_DEV_PM_OPS(ahci_imx_pm_ops, imx_ahci_suspend, imx_ahci_resume);
  1060. static struct platform_driver imx_ahci_driver = {
  1061. .probe = imx_ahci_probe,
  1062. .remove = ata_platform_remove_one,
  1063. .driver = {
  1064. .name = DRV_NAME,
  1065. .of_match_table = imx_ahci_of_match,
  1066. .pm = &ahci_imx_pm_ops,
  1067. },
  1068. };
  1069. module_platform_driver(imx_ahci_driver);
  1070. MODULE_DESCRIPTION("Freescale i.MX AHCI SATA platform driver");
  1071. MODULE_AUTHOR("Richard Zhu <Hong-Xing.Zhu@freescale.com>");
  1072. MODULE_LICENSE("GPL");
  1073. MODULE_ALIAS("ahci:imx");