ahci_ceva.c 9.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2015 Xilinx, Inc.
  4. * CEVA AHCI SATA platform driver
  5. *
  6. * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
  7. */
  8. #include <linux/ahci_platform.h>
  9. #include <linux/kernel.h>
  10. #include <linux/libata.h>
  11. #include <linux/module.h>
  12. #include <linux/of_device.h>
  13. #include <linux/platform_device.h>
  14. #include "ahci.h"
  15. /* Vendor Specific Register Offsets */
  16. #define AHCI_VEND_PCFG 0xA4
  17. #define AHCI_VEND_PPCFG 0xA8
  18. #define AHCI_VEND_PP2C 0xAC
  19. #define AHCI_VEND_PP3C 0xB0
  20. #define AHCI_VEND_PP4C 0xB4
  21. #define AHCI_VEND_PP5C 0xB8
  22. #define AHCI_VEND_AXICC 0xBC
  23. #define AHCI_VEND_PAXIC 0xC0
  24. #define AHCI_VEND_PTC 0xC8
  25. /* Vendor Specific Register bit definitions */
  26. #define PAXIC_ADBW_BW64 0x1
  27. #define PAXIC_MAWID(i) (((i) * 2) << 4)
  28. #define PAXIC_MARID(i) (((i) * 2) << 12)
  29. #define PAXIC_MARIDD(i) ((((i) * 2) + 1) << 16)
  30. #define PAXIC_MAWIDD(i) ((((i) * 2) + 1) << 8)
  31. #define PAXIC_OTL (0x4 << 20)
  32. /* Register bit definitions for cache control */
  33. #define AXICC_ARCA_VAL (0xF << 0)
  34. #define AXICC_ARCF_VAL (0xF << 4)
  35. #define AXICC_ARCH_VAL (0xF << 8)
  36. #define AXICC_ARCP_VAL (0xF << 12)
  37. #define AXICC_AWCFD_VAL (0xF << 16)
  38. #define AXICC_AWCD_VAL (0xF << 20)
  39. #define AXICC_AWCF_VAL (0xF << 24)
  40. #define PCFG_TPSS_VAL (0x32 << 16)
  41. #define PCFG_TPRS_VAL (0x2 << 12)
  42. #define PCFG_PAD_VAL 0x2
  43. #define PPCFG_TTA 0x1FFFE
  44. #define PPCFG_PSSO_EN (1 << 28)
  45. #define PPCFG_PSS_EN (1 << 29)
  46. #define PPCFG_ESDF_EN (1 << 31)
  47. #define PP5C_RIT 0x60216
  48. #define PP5C_RCT (0x7f0 << 20)
  49. #define PTC_RX_WM_VAL 0x40
  50. #define PTC_RSVD (1 << 27)
  51. #define PORT0_BASE 0x100
  52. #define PORT1_BASE 0x180
  53. /* Port Control Register Bit Definitions */
  54. #define PORT_SCTL_SPD_GEN3 (0x3 << 4)
  55. #define PORT_SCTL_SPD_GEN2 (0x2 << 4)
  56. #define PORT_SCTL_SPD_GEN1 (0x1 << 4)
  57. #define PORT_SCTL_IPM (0x3 << 8)
  58. #define PORT_BASE 0x100
  59. #define PORT_OFFSET 0x80
  60. #define NR_PORTS 2
  61. #define DRV_NAME "ahci-ceva"
  62. #define CEVA_FLAG_BROKEN_GEN2 1
  63. static unsigned int rx_watermark = PTC_RX_WM_VAL;
  64. module_param(rx_watermark, uint, 0644);
  65. MODULE_PARM_DESC(rx_watermark, "RxWaterMark value (0 - 0x80)");
  66. struct ceva_ahci_priv {
  67. struct platform_device *ahci_pdev;
  68. /* Port Phy2Cfg Register */
  69. u32 pp2c[NR_PORTS];
  70. u32 pp3c[NR_PORTS];
  71. u32 pp4c[NR_PORTS];
  72. u32 pp5c[NR_PORTS];
  73. /* Axi Cache Control Register */
  74. u32 axicc;
  75. bool is_cci_enabled;
  76. int flags;
  77. };
  78. static unsigned int ceva_ahci_read_id(struct ata_device *dev,
  79. struct ata_taskfile *tf, u16 *id)
  80. {
  81. u32 err_mask;
  82. err_mask = ata_do_dev_read_id(dev, tf, id);
  83. if (err_mask)
  84. return err_mask;
  85. /*
  86. * Since CEVA controller does not support device sleep feature, we
  87. * need to clear DEVSLP (bit 8) in word78 of the IDENTIFY DEVICE data.
  88. */
  89. id[ATA_ID_FEATURE_SUPP] &= cpu_to_le16(~(1 << 8));
  90. return 0;
  91. }
  92. static struct ata_port_operations ahci_ceva_ops = {
  93. .inherits = &ahci_platform_ops,
  94. .read_id = ceva_ahci_read_id,
  95. };
  96. static const struct ata_port_info ahci_ceva_port_info = {
  97. .flags = AHCI_FLAG_COMMON,
  98. .pio_mask = ATA_PIO4,
  99. .udma_mask = ATA_UDMA6,
  100. .port_ops = &ahci_ceva_ops,
  101. };
  102. static void ahci_ceva_setup(struct ahci_host_priv *hpriv)
  103. {
  104. void __iomem *mmio = hpriv->mmio;
  105. struct ceva_ahci_priv *cevapriv = hpriv->plat_data;
  106. u32 tmp;
  107. int i;
  108. /* Set AHCI Enable */
  109. tmp = readl(mmio + HOST_CTL);
  110. tmp |= HOST_AHCI_EN;
  111. writel(tmp, mmio + HOST_CTL);
  112. for (i = 0; i < NR_PORTS; i++) {
  113. /* TPSS TPRS scalars, CISE and Port Addr */
  114. tmp = PCFG_TPSS_VAL | PCFG_TPRS_VAL | (PCFG_PAD_VAL + i);
  115. writel(tmp, mmio + AHCI_VEND_PCFG);
  116. /*
  117. * AXI Data bus width to 64
  118. * Set Mem Addr Read, Write ID for data transfers
  119. * Set Mem Addr Read ID, Write ID for non-data transfers
  120. * Transfer limit to 72 DWord
  121. */
  122. tmp = PAXIC_ADBW_BW64 | PAXIC_MAWIDD(i) | PAXIC_MARIDD(i) |
  123. PAXIC_MAWID(i) | PAXIC_MARID(i) | PAXIC_OTL;
  124. writel(tmp, mmio + AHCI_VEND_PAXIC);
  125. /* Set AXI cache control register if CCi is enabled */
  126. if (cevapriv->is_cci_enabled) {
  127. tmp = readl(mmio + AHCI_VEND_AXICC);
  128. tmp |= AXICC_ARCA_VAL | AXICC_ARCF_VAL |
  129. AXICC_ARCH_VAL | AXICC_ARCP_VAL |
  130. AXICC_AWCFD_VAL | AXICC_AWCD_VAL |
  131. AXICC_AWCF_VAL;
  132. writel(tmp, mmio + AHCI_VEND_AXICC);
  133. }
  134. /* Port Phy Cfg register enables */
  135. tmp = PPCFG_TTA | PPCFG_PSS_EN | PPCFG_ESDF_EN;
  136. writel(tmp, mmio + AHCI_VEND_PPCFG);
  137. /* Phy Control OOB timing parameters COMINIT */
  138. writel(cevapriv->pp2c[i], mmio + AHCI_VEND_PP2C);
  139. /* Phy Control OOB timing parameters COMWAKE */
  140. writel(cevapriv->pp3c[i], mmio + AHCI_VEND_PP3C);
  141. /* Phy Control Burst timing setting */
  142. writel(cevapriv->pp4c[i], mmio + AHCI_VEND_PP4C);
  143. /* Rate Change Timer and Retry Interval Timer setting */
  144. writel(cevapriv->pp5c[i], mmio + AHCI_VEND_PP5C);
  145. /* Rx Watermark setting */
  146. tmp = rx_watermark | PTC_RSVD;
  147. writel(tmp, mmio + AHCI_VEND_PTC);
  148. /* Default to Gen 3 Speed and Gen 1 if Gen2 is broken */
  149. tmp = PORT_SCTL_SPD_GEN3 | PORT_SCTL_IPM;
  150. if (cevapriv->flags & CEVA_FLAG_BROKEN_GEN2)
  151. tmp = PORT_SCTL_SPD_GEN1 | PORT_SCTL_IPM;
  152. writel(tmp, mmio + PORT_SCR_CTL + PORT_BASE + PORT_OFFSET * i);
  153. }
  154. }
  155. static struct scsi_host_template ahci_platform_sht = {
  156. AHCI_SHT(DRV_NAME),
  157. };
  158. static int ceva_ahci_probe(struct platform_device *pdev)
  159. {
  160. struct device_node *np = pdev->dev.of_node;
  161. struct device *dev = &pdev->dev;
  162. struct ahci_host_priv *hpriv;
  163. struct ceva_ahci_priv *cevapriv;
  164. enum dev_dma_attr attr;
  165. int rc;
  166. cevapriv = devm_kzalloc(dev, sizeof(*cevapriv), GFP_KERNEL);
  167. if (!cevapriv)
  168. return -ENOMEM;
  169. cevapriv->ahci_pdev = pdev;
  170. hpriv = ahci_platform_get_resources(pdev, 0);
  171. if (IS_ERR(hpriv))
  172. return PTR_ERR(hpriv);
  173. rc = ahci_platform_enable_resources(hpriv);
  174. if (rc)
  175. return rc;
  176. if (of_property_read_bool(np, "ceva,broken-gen2"))
  177. cevapriv->flags = CEVA_FLAG_BROKEN_GEN2;
  178. /* Read OOB timing value for COMINIT from device-tree */
  179. if (of_property_read_u8_array(np, "ceva,p0-cominit-params",
  180. (u8 *)&cevapriv->pp2c[0], 4) < 0) {
  181. dev_warn(dev, "ceva,p0-cominit-params property not defined\n");
  182. return -EINVAL;
  183. }
  184. if (of_property_read_u8_array(np, "ceva,p1-cominit-params",
  185. (u8 *)&cevapriv->pp2c[1], 4) < 0) {
  186. dev_warn(dev, "ceva,p1-cominit-params property not defined\n");
  187. return -EINVAL;
  188. }
  189. /* Read OOB timing value for COMWAKE from device-tree*/
  190. if (of_property_read_u8_array(np, "ceva,p0-comwake-params",
  191. (u8 *)&cevapriv->pp3c[0], 4) < 0) {
  192. dev_warn(dev, "ceva,p0-comwake-params property not defined\n");
  193. return -EINVAL;
  194. }
  195. if (of_property_read_u8_array(np, "ceva,p1-comwake-params",
  196. (u8 *)&cevapriv->pp3c[1], 4) < 0) {
  197. dev_warn(dev, "ceva,p1-comwake-params property not defined\n");
  198. return -EINVAL;
  199. }
  200. /* Read phy BURST timing value from device-tree */
  201. if (of_property_read_u8_array(np, "ceva,p0-burst-params",
  202. (u8 *)&cevapriv->pp4c[0], 4) < 0) {
  203. dev_warn(dev, "ceva,p0-burst-params property not defined\n");
  204. return -EINVAL;
  205. }
  206. if (of_property_read_u8_array(np, "ceva,p1-burst-params",
  207. (u8 *)&cevapriv->pp4c[1], 4) < 0) {
  208. dev_warn(dev, "ceva,p1-burst-params property not defined\n");
  209. return -EINVAL;
  210. }
  211. /* Read phy RETRY interval timing value from device-tree */
  212. if (of_property_read_u16_array(np, "ceva,p0-retry-params",
  213. (u16 *)&cevapriv->pp5c[0], 2) < 0) {
  214. dev_warn(dev, "ceva,p0-retry-params property not defined\n");
  215. return -EINVAL;
  216. }
  217. if (of_property_read_u16_array(np, "ceva,p1-retry-params",
  218. (u16 *)&cevapriv->pp5c[1], 2) < 0) {
  219. dev_warn(dev, "ceva,p1-retry-params property not defined\n");
  220. return -EINVAL;
  221. }
  222. /*
  223. * Check if CCI is enabled for SATA. The DEV_DMA_COHERENT is returned
  224. * if CCI is enabled, so check for DEV_DMA_COHERENT.
  225. */
  226. attr = device_get_dma_attr(dev);
  227. cevapriv->is_cci_enabled = (attr == DEV_DMA_COHERENT);
  228. hpriv->plat_data = cevapriv;
  229. /* CEVA specific initialization */
  230. ahci_ceva_setup(hpriv);
  231. rc = ahci_platform_init_host(pdev, hpriv, &ahci_ceva_port_info,
  232. &ahci_platform_sht);
  233. if (rc)
  234. goto disable_resources;
  235. return 0;
  236. disable_resources:
  237. ahci_platform_disable_resources(hpriv);
  238. return rc;
  239. }
  240. static int __maybe_unused ceva_ahci_suspend(struct device *dev)
  241. {
  242. return ahci_platform_suspend(dev);
  243. }
  244. static int __maybe_unused ceva_ahci_resume(struct device *dev)
  245. {
  246. struct ata_host *host = dev_get_drvdata(dev);
  247. struct ahci_host_priv *hpriv = host->private_data;
  248. int rc;
  249. rc = ahci_platform_enable_resources(hpriv);
  250. if (rc)
  251. return rc;
  252. /* Configure CEVA specific config before resuming HBA */
  253. ahci_ceva_setup(hpriv);
  254. rc = ahci_platform_resume_host(dev);
  255. if (rc)
  256. goto disable_resources;
  257. /* We resumed so update PM runtime state */
  258. pm_runtime_disable(dev);
  259. pm_runtime_set_active(dev);
  260. pm_runtime_enable(dev);
  261. return 0;
  262. disable_resources:
  263. ahci_platform_disable_resources(hpriv);
  264. return rc;
  265. }
  266. static SIMPLE_DEV_PM_OPS(ahci_ceva_pm_ops, ceva_ahci_suspend, ceva_ahci_resume);
  267. static const struct of_device_id ceva_ahci_of_match[] = {
  268. { .compatible = "ceva,ahci-1v84" },
  269. {},
  270. };
  271. MODULE_DEVICE_TABLE(of, ceva_ahci_of_match);
  272. static struct platform_driver ceva_ahci_driver = {
  273. .probe = ceva_ahci_probe,
  274. .remove = ata_platform_remove_one,
  275. .driver = {
  276. .name = DRV_NAME,
  277. .of_match_table = ceva_ahci_of_match,
  278. .pm = &ahci_ceva_pm_ops,
  279. },
  280. };
  281. module_platform_driver(ceva_ahci_driver);
  282. MODULE_DESCRIPTION("CEVA AHCI SATA platform driver");
  283. MODULE_AUTHOR("Xilinx Inc.");
  284. MODULE_LICENSE("GPL v2");