ahci.h 17 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * ahci.h - Common AHCI SATA definitions and declarations
  4. *
  5. * Maintained by: Tejun Heo <tj@kernel.org>
  6. * Please ALWAYS copy linux-ide@vger.kernel.org
  7. * on emails.
  8. *
  9. * Copyright 2004-2005 Red Hat, Inc.
  10. *
  11. * libata documentation is available via 'make {ps|pdf}docs',
  12. * as Documentation/driver-api/libata.rst
  13. *
  14. * AHCI hardware documentation:
  15. * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
  16. * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
  17. */
  18. #ifndef _AHCI_H
  19. #define _AHCI_H
  20. #include <linux/pci.h>
  21. #include <linux/clk.h>
  22. #include <linux/libata.h>
  23. #include <linux/phy/phy.h>
  24. #include <linux/regulator/consumer.h>
  25. /* Enclosure Management Control */
  26. #define EM_CTRL_MSG_TYPE 0x000f0000
  27. /* Enclosure Management LED Message Type */
  28. #define EM_MSG_LED_HBA_PORT 0x0000000f
  29. #define EM_MSG_LED_PMP_SLOT 0x0000ff00
  30. #define EM_MSG_LED_VALUE 0xffff0000
  31. #define EM_MSG_LED_VALUE_ACTIVITY 0x00070000
  32. #define EM_MSG_LED_VALUE_OFF 0xfff80000
  33. #define EM_MSG_LED_VALUE_ON 0x00010000
  34. enum {
  35. AHCI_MAX_PORTS = 32,
  36. AHCI_MAX_CLKS = 5,
  37. AHCI_MAX_SG = 168, /* hardware max is 64K */
  38. AHCI_DMA_BOUNDARY = 0xffffffff,
  39. AHCI_MAX_CMDS = 32,
  40. AHCI_CMD_SZ = 32,
  41. AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
  42. AHCI_RX_FIS_SZ = 256,
  43. AHCI_CMD_TBL_CDB = 0x40,
  44. AHCI_CMD_TBL_HDR_SZ = 0x80,
  45. AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
  46. AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
  47. AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
  48. AHCI_RX_FIS_SZ,
  49. AHCI_PORT_PRIV_FBS_DMA_SZ = AHCI_CMD_SLOT_SZ +
  50. AHCI_CMD_TBL_AR_SZ +
  51. (AHCI_RX_FIS_SZ * 16),
  52. AHCI_IRQ_ON_SG = (1 << 31),
  53. AHCI_CMD_ATAPI = (1 << 5),
  54. AHCI_CMD_WRITE = (1 << 6),
  55. AHCI_CMD_PREFETCH = (1 << 7),
  56. AHCI_CMD_RESET = (1 << 8),
  57. AHCI_CMD_CLR_BUSY = (1 << 10),
  58. RX_FIS_PIO_SETUP = 0x20, /* offset of PIO Setup FIS data */
  59. RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
  60. RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
  61. RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
  62. /* global controller registers */
  63. HOST_CAP = 0x00, /* host capabilities */
  64. HOST_CTL = 0x04, /* global host control */
  65. HOST_IRQ_STAT = 0x08, /* interrupt status */
  66. HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
  67. HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
  68. HOST_EM_LOC = 0x1c, /* Enclosure Management location */
  69. HOST_EM_CTL = 0x20, /* Enclosure Management Control */
  70. HOST_CAP2 = 0x24, /* host capabilities, extended */
  71. /* HOST_CTL bits */
  72. HOST_RESET = (1 << 0), /* reset controller; self-clear */
  73. HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
  74. HOST_MRSM = (1 << 2), /* MSI Revert to Single Message */
  75. HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
  76. /* HOST_CAP bits */
  77. HOST_CAP_SXS = (1 << 5), /* Supports External SATA */
  78. HOST_CAP_EMS = (1 << 6), /* Enclosure Management support */
  79. HOST_CAP_CCC = (1 << 7), /* Command Completion Coalescing */
  80. HOST_CAP_PART = (1 << 13), /* Partial state capable */
  81. HOST_CAP_SSC = (1 << 14), /* Slumber state capable */
  82. HOST_CAP_PIO_MULTI = (1 << 15), /* PIO multiple DRQ support */
  83. HOST_CAP_FBS = (1 << 16), /* FIS-based switching support */
  84. HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
  85. HOST_CAP_ONLY = (1 << 18), /* Supports AHCI mode only */
  86. HOST_CAP_CLO = (1 << 24), /* Command List Override support */
  87. HOST_CAP_LED = (1 << 25), /* Supports activity LED */
  88. HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */
  89. HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
  90. HOST_CAP_MPS = (1 << 28), /* Mechanical presence switch */
  91. HOST_CAP_SNTF = (1 << 29), /* SNotification register */
  92. HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
  93. HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
  94. /* HOST_CAP2 bits */
  95. HOST_CAP2_BOH = (1 << 0), /* BIOS/OS handoff supported */
  96. HOST_CAP2_NVMHCI = (1 << 1), /* NVMHCI supported */
  97. HOST_CAP2_APST = (1 << 2), /* Automatic partial to slumber */
  98. HOST_CAP2_SDS = (1 << 3), /* Support device sleep */
  99. HOST_CAP2_SADM = (1 << 4), /* Support aggressive DevSlp */
  100. HOST_CAP2_DESO = (1 << 5), /* DevSlp from slumber only */
  101. /* registers for each SATA port */
  102. PORT_LST_ADDR = 0x00, /* command list DMA addr */
  103. PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
  104. PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
  105. PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
  106. PORT_IRQ_STAT = 0x10, /* interrupt status */
  107. PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
  108. PORT_CMD = 0x18, /* port command */
  109. PORT_TFDATA = 0x20, /* taskfile data */
  110. PORT_SIG = 0x24, /* device TF signature */
  111. PORT_CMD_ISSUE = 0x38, /* command issue */
  112. PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
  113. PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
  114. PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
  115. PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
  116. PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
  117. PORT_FBS = 0x40, /* FIS-based Switching */
  118. PORT_DEVSLP = 0x44, /* device sleep */
  119. /* PORT_IRQ_{STAT,MASK} bits */
  120. PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
  121. PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
  122. PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
  123. PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
  124. PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
  125. PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
  126. PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
  127. PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
  128. PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
  129. PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
  130. PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
  131. PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
  132. PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
  133. PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
  134. PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
  135. PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
  136. PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
  137. PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
  138. PORT_IRQ_IF_ERR |
  139. PORT_IRQ_CONNECT |
  140. PORT_IRQ_PHYRDY |
  141. PORT_IRQ_UNK_FIS |
  142. PORT_IRQ_BAD_PMP,
  143. PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
  144. PORT_IRQ_TF_ERR |
  145. PORT_IRQ_HBUS_DATA_ERR,
  146. DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
  147. PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
  148. PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
  149. /* PORT_CMD bits */
  150. PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */
  151. PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */
  152. PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
  153. PORT_CMD_FBSCP = (1 << 22), /* FBS Capable Port */
  154. PORT_CMD_ESP = (1 << 21), /* External Sata Port */
  155. PORT_CMD_HPCP = (1 << 18), /* HotPlug Capable Port */
  156. PORT_CMD_PMP = (1 << 17), /* PMP attached */
  157. PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
  158. PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
  159. PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
  160. PORT_CMD_CLO = (1 << 3), /* Command list override */
  161. PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
  162. PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
  163. PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
  164. PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
  165. PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
  166. PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
  167. PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
  168. /* PORT_FBS bits */
  169. PORT_FBS_DWE_OFFSET = 16, /* FBS device with error offset */
  170. PORT_FBS_ADO_OFFSET = 12, /* FBS active dev optimization offset */
  171. PORT_FBS_DEV_OFFSET = 8, /* FBS device to issue offset */
  172. PORT_FBS_DEV_MASK = (0xf << PORT_FBS_DEV_OFFSET), /* FBS.DEV */
  173. PORT_FBS_SDE = (1 << 2), /* FBS single device error */
  174. PORT_FBS_DEC = (1 << 1), /* FBS device error clear */
  175. PORT_FBS_EN = (1 << 0), /* Enable FBS */
  176. /* PORT_DEVSLP bits */
  177. PORT_DEVSLP_DM_OFFSET = 25, /* DITO multiplier offset */
  178. PORT_DEVSLP_DM_MASK = (0xf << 25), /* DITO multiplier mask */
  179. PORT_DEVSLP_DITO_OFFSET = 15, /* DITO offset */
  180. PORT_DEVSLP_MDAT_OFFSET = 10, /* Minimum assertion time */
  181. PORT_DEVSLP_DETO_OFFSET = 2, /* DevSlp exit timeout */
  182. PORT_DEVSLP_DSP = (1 << 1), /* DevSlp present */
  183. PORT_DEVSLP_ADSE = (1 << 0), /* Aggressive DevSlp enable */
  184. /* hpriv->flags bits */
  185. #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
  186. AHCI_HFLAG_NO_NCQ = (1 << 0),
  187. AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
  188. AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
  189. AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
  190. AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
  191. AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
  192. AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
  193. AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */
  194. AHCI_HFLAG_YES_NCQ = (1 << 9), /* force NCQ cap on */
  195. AHCI_HFLAG_NO_SUSPEND = (1 << 10), /* don't suspend */
  196. AHCI_HFLAG_SRST_TOUT_IS_OFFLINE = (1 << 11), /* treat SRST timeout as
  197. link offline */
  198. AHCI_HFLAG_NO_SNTF = (1 << 12), /* no sntf */
  199. AHCI_HFLAG_NO_FPDMA_AA = (1 << 13), /* no FPDMA AA */
  200. AHCI_HFLAG_YES_FBS = (1 << 14), /* force FBS cap on */
  201. AHCI_HFLAG_DELAY_ENGINE = (1 << 15), /* do not start engine on
  202. port start (wait until
  203. error-handling stage) */
  204. AHCI_HFLAG_NO_DEVSLP = (1 << 17), /* no device sleep */
  205. AHCI_HFLAG_NO_FBS = (1 << 18), /* no FBS */
  206. #ifdef CONFIG_PCI_MSI
  207. AHCI_HFLAG_MULTI_MSI = (1 << 20), /* per-port MSI(-X) */
  208. #else
  209. /* compile out MSI infrastructure */
  210. AHCI_HFLAG_MULTI_MSI = 0,
  211. #endif
  212. AHCI_HFLAG_WAKE_BEFORE_STOP = (1 << 22), /* wake before DMA stop */
  213. AHCI_HFLAG_YES_ALPM = (1 << 23), /* force ALPM cap on */
  214. AHCI_HFLAG_NO_WRITE_TO_RO = (1 << 24), /* don't write to read
  215. only registers */
  216. AHCI_HFLAG_IS_MOBILE = (1 << 25), /* mobile chipset, use
  217. SATA_MOBILE_LPM_POLICY
  218. as default lpm_policy */
  219. AHCI_HFLAG_SUSPEND_PHYS = (1 << 26), /* handle PHYs during
  220. suspend/resume */
  221. AHCI_HFLAG_IGN_NOTSUPP_POWER_ON = (1 << 27), /* ignore -EOPNOTSUPP
  222. from phy_power_on() */
  223. AHCI_HFLAG_NO_SXS = (1 << 28), /* SXS not supported */
  224. /* ap->flags bits */
  225. AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA |
  226. ATA_FLAG_ACPI_SATA | ATA_FLAG_AN,
  227. ICH_MAP = 0x90, /* ICH MAP register */
  228. PCS_6 = 0x92, /* 6 port PCS */
  229. PCS_7 = 0x94, /* 7+ port PCS (Denverton) */
  230. /* em constants */
  231. EM_MAX_SLOTS = 8,
  232. EM_MAX_RETRY = 5,
  233. /* em_ctl bits */
  234. EM_CTL_RST = (1 << 9), /* Reset */
  235. EM_CTL_TM = (1 << 8), /* Transmit Message */
  236. EM_CTL_MR = (1 << 0), /* Message Received */
  237. EM_CTL_ALHD = (1 << 26), /* Activity LED */
  238. EM_CTL_XMT = (1 << 25), /* Transmit Only */
  239. EM_CTL_SMB = (1 << 24), /* Single Message Buffer */
  240. EM_CTL_SGPIO = (1 << 19), /* SGPIO messages supported */
  241. EM_CTL_SES = (1 << 18), /* SES-2 messages supported */
  242. EM_CTL_SAFTE = (1 << 17), /* SAF-TE messages supported */
  243. EM_CTL_LED = (1 << 16), /* LED messages supported */
  244. /* em message type */
  245. EM_MSG_TYPE_LED = (1 << 0), /* LED */
  246. EM_MSG_TYPE_SAFTE = (1 << 1), /* SAF-TE */
  247. EM_MSG_TYPE_SES2 = (1 << 2), /* SES-2 */
  248. EM_MSG_TYPE_SGPIO = (1 << 3), /* SGPIO */
  249. };
  250. struct ahci_cmd_hdr {
  251. __le32 opts;
  252. __le32 status;
  253. __le32 tbl_addr;
  254. __le32 tbl_addr_hi;
  255. __le32 reserved[4];
  256. };
  257. struct ahci_sg {
  258. __le32 addr;
  259. __le32 addr_hi;
  260. __le32 reserved;
  261. __le32 flags_size;
  262. };
  263. struct ahci_em_priv {
  264. enum sw_activity blink_policy;
  265. struct timer_list timer;
  266. unsigned long saved_activity;
  267. unsigned long activity;
  268. unsigned long led_state;
  269. struct ata_link *link;
  270. };
  271. struct ahci_port_priv {
  272. struct ata_link *active_link;
  273. struct ahci_cmd_hdr *cmd_slot;
  274. dma_addr_t cmd_slot_dma;
  275. void *cmd_tbl;
  276. dma_addr_t cmd_tbl_dma;
  277. void *rx_fis;
  278. dma_addr_t rx_fis_dma;
  279. /* for NCQ spurious interrupt analysis */
  280. unsigned int ncq_saw_d2h:1;
  281. unsigned int ncq_saw_dmas:1;
  282. unsigned int ncq_saw_sdb:1;
  283. spinlock_t lock; /* protects parent ata_port */
  284. u32 intr_mask; /* interrupts to enable */
  285. bool fbs_supported; /* set iff FBS is supported */
  286. bool fbs_enabled; /* set iff FBS is enabled */
  287. int fbs_last_dev; /* save FBS.DEV of last FIS */
  288. /* enclosure management info per PM slot */
  289. struct ahci_em_priv em_priv[EM_MAX_SLOTS];
  290. char *irq_desc; /* desc in /proc/interrupts */
  291. };
  292. struct ahci_host_priv {
  293. /* Input fields */
  294. unsigned int flags; /* AHCI_HFLAG_* */
  295. u32 force_port_map; /* force port map */
  296. u32 mask_port_map; /* mask out particular bits */
  297. void __iomem * mmio; /* bus-independent mem map */
  298. u32 cap; /* cap to use */
  299. u32 cap2; /* cap2 to use */
  300. u32 version; /* cached version */
  301. u32 port_map; /* port map to use */
  302. u32 saved_cap; /* saved initial cap */
  303. u32 saved_cap2; /* saved initial cap2 */
  304. u32 saved_port_map; /* saved initial port_map */
  305. u32 em_loc; /* enclosure management location */
  306. u32 em_buf_sz; /* EM buffer size in byte */
  307. u32 em_msg_type; /* EM message type */
  308. u32 remapped_nvme; /* NVMe remapped device count */
  309. bool got_runtime_pm; /* Did we do pm_runtime_get? */
  310. struct clk *clks[AHCI_MAX_CLKS]; /* Optional */
  311. struct reset_control *rsts; /* Optional */
  312. struct regulator **target_pwrs; /* Optional */
  313. struct regulator *ahci_regulator;/* Optional */
  314. struct regulator *phy_regulator;/* Optional */
  315. /*
  316. * If platform uses PHYs. There is a 1:1 relation between the port number and
  317. * the PHY position in this array.
  318. */
  319. struct phy **phys;
  320. unsigned nports; /* Number of ports */
  321. void *plat_data; /* Other platform data */
  322. unsigned int irq; /* interrupt line */
  323. /*
  324. * Optional ahci_start_engine override, if not set this gets set to the
  325. * default ahci_start_engine during ahci_save_initial_config, this can
  326. * be overridden anytime before the host is activated.
  327. */
  328. void (*start_engine)(struct ata_port *ap);
  329. /*
  330. * Optional ahci_stop_engine override, if not set this gets set to the
  331. * default ahci_stop_engine during ahci_save_initial_config, this can
  332. * be overridden anytime before the host is activated.
  333. */
  334. int (*stop_engine)(struct ata_port *ap);
  335. irqreturn_t (*irq_handler)(int irq, void *dev_instance);
  336. /* only required for per-port MSI(-X) support */
  337. int (*get_irq_vector)(struct ata_host *host,
  338. int port);
  339. };
  340. extern int ahci_ignore_sss;
  341. extern struct device_attribute *ahci_shost_attrs[];
  342. extern struct device_attribute *ahci_sdev_attrs[];
  343. /*
  344. * This must be instantiated by the edge drivers. Read the comments
  345. * for ATA_BASE_SHT
  346. */
  347. #define AHCI_SHT(drv_name) \
  348. ATA_NCQ_SHT(drv_name), \
  349. .can_queue = AHCI_MAX_CMDS, \
  350. .sg_tablesize = AHCI_MAX_SG, \
  351. .dma_boundary = AHCI_DMA_BOUNDARY, \
  352. .shost_attrs = ahci_shost_attrs, \
  353. .sdev_attrs = ahci_sdev_attrs
  354. extern struct ata_port_operations ahci_ops;
  355. extern struct ata_port_operations ahci_platform_ops;
  356. extern struct ata_port_operations ahci_pmp_retry_srst_ops;
  357. unsigned int ahci_dev_classify(struct ata_port *ap);
  358. void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
  359. u32 opts);
  360. void ahci_save_initial_config(struct device *dev,
  361. struct ahci_host_priv *hpriv);
  362. void ahci_init_controller(struct ata_host *host);
  363. int ahci_reset_controller(struct ata_host *host);
  364. int ahci_do_softreset(struct ata_link *link, unsigned int *class,
  365. int pmp, unsigned long deadline,
  366. int (*check_ready)(struct ata_link *link));
  367. int ahci_do_hardreset(struct ata_link *link, unsigned int *class,
  368. unsigned long deadline, bool *online);
  369. unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
  370. int ahci_stop_engine(struct ata_port *ap);
  371. void ahci_start_fis_rx(struct ata_port *ap);
  372. void ahci_start_engine(struct ata_port *ap);
  373. int ahci_check_ready(struct ata_link *link);
  374. int ahci_kick_engine(struct ata_port *ap);
  375. int ahci_port_resume(struct ata_port *ap);
  376. void ahci_set_em_messages(struct ahci_host_priv *hpriv,
  377. struct ata_port_info *pi);
  378. int ahci_reset_em(struct ata_host *host);
  379. void ahci_print_info(struct ata_host *host, const char *scc_s);
  380. int ahci_host_activate(struct ata_host *host, struct scsi_host_template *sht);
  381. void ahci_error_handler(struct ata_port *ap);
  382. u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked);
  383. static inline void __iomem *__ahci_port_base(struct ata_host *host,
  384. unsigned int port_no)
  385. {
  386. struct ahci_host_priv *hpriv = host->private_data;
  387. void __iomem *mmio = hpriv->mmio;
  388. return mmio + 0x100 + (port_no * 0x80);
  389. }
  390. static inline void __iomem *ahci_port_base(struct ata_port *ap)
  391. {
  392. return __ahci_port_base(ap->host, ap->port_no);
  393. }
  394. static inline int ahci_nr_ports(u32 cap)
  395. {
  396. return (cap & 0x1f) + 1;
  397. }
  398. #endif /* _AHCI_H */