ahci.c 63 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * ahci.c - AHCI SATA support
  4. *
  5. * Maintained by: Tejun Heo <tj@kernel.org>
  6. * Please ALWAYS copy linux-ide@vger.kernel.org
  7. * on emails.
  8. *
  9. * Copyright 2004-2005 Red Hat, Inc.
  10. *
  11. * libata documentation is available via 'make {ps|pdf}docs',
  12. * as Documentation/driver-api/libata.rst
  13. *
  14. * AHCI hardware documentation:
  15. * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
  16. * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
  17. */
  18. #include <linux/kernel.h>
  19. #include <linux/module.h>
  20. #include <linux/pci.h>
  21. #include <linux/blkdev.h>
  22. #include <linux/delay.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/dma-mapping.h>
  25. #include <linux/device.h>
  26. #include <linux/dmi.h>
  27. #include <linux/gfp.h>
  28. #include <linux/msi.h>
  29. #include <scsi/scsi_host.h>
  30. #include <scsi/scsi_cmnd.h>
  31. #include <linux/libata.h>
  32. #include <linux/ahci-remap.h>
  33. #include <linux/io-64-nonatomic-lo-hi.h>
  34. #include "ahci.h"
  35. #define DRV_NAME "ahci"
  36. #define DRV_VERSION "3.0"
  37. enum {
  38. AHCI_PCI_BAR_STA2X11 = 0,
  39. AHCI_PCI_BAR_CAVIUM = 0,
  40. AHCI_PCI_BAR_LOONGSON = 0,
  41. AHCI_PCI_BAR_ENMOTUS = 2,
  42. AHCI_PCI_BAR_CAVIUM_GEN5 = 4,
  43. AHCI_PCI_BAR_STANDARD = 5,
  44. };
  45. enum board_ids {
  46. /* board IDs by feature in alphabetical order */
  47. board_ahci,
  48. board_ahci_ign_iferr,
  49. board_ahci_mobile,
  50. board_ahci_nomsi,
  51. board_ahci_noncq,
  52. board_ahci_nosntf,
  53. board_ahci_yes_fbs,
  54. /* board IDs for specific chipsets in alphabetical order */
  55. board_ahci_al,
  56. board_ahci_avn,
  57. board_ahci_mcp65,
  58. board_ahci_mcp77,
  59. board_ahci_mcp89,
  60. board_ahci_mv,
  61. board_ahci_sb600,
  62. board_ahci_sb700, /* for SB700 and SB800 */
  63. board_ahci_vt8251,
  64. /*
  65. * board IDs for Intel chipsets that support more than 6 ports
  66. * *and* end up needing the PCS quirk.
  67. */
  68. board_ahci_pcs7,
  69. /* aliases */
  70. board_ahci_mcp_linux = board_ahci_mcp65,
  71. board_ahci_mcp67 = board_ahci_mcp65,
  72. board_ahci_mcp73 = board_ahci_mcp65,
  73. board_ahci_mcp79 = board_ahci_mcp77,
  74. };
  75. static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
  76. static void ahci_remove_one(struct pci_dev *dev);
  77. static void ahci_shutdown_one(struct pci_dev *dev);
  78. static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
  79. unsigned long deadline);
  80. static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
  81. unsigned long deadline);
  82. static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
  83. static bool is_mcp89_apple(struct pci_dev *pdev);
  84. static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
  85. unsigned long deadline);
  86. #ifdef CONFIG_PM
  87. static int ahci_pci_device_runtime_suspend(struct device *dev);
  88. static int ahci_pci_device_runtime_resume(struct device *dev);
  89. #ifdef CONFIG_PM_SLEEP
  90. static int ahci_pci_device_suspend(struct device *dev);
  91. static int ahci_pci_device_resume(struct device *dev);
  92. #endif
  93. #endif /* CONFIG_PM */
  94. static struct scsi_host_template ahci_sht = {
  95. AHCI_SHT("ahci"),
  96. };
  97. static struct ata_port_operations ahci_vt8251_ops = {
  98. .inherits = &ahci_ops,
  99. .hardreset = ahci_vt8251_hardreset,
  100. };
  101. static struct ata_port_operations ahci_p5wdh_ops = {
  102. .inherits = &ahci_ops,
  103. .hardreset = ahci_p5wdh_hardreset,
  104. };
  105. static struct ata_port_operations ahci_avn_ops = {
  106. .inherits = &ahci_ops,
  107. .hardreset = ahci_avn_hardreset,
  108. };
  109. static const struct ata_port_info ahci_port_info[] = {
  110. /* by features */
  111. [board_ahci] = {
  112. .flags = AHCI_FLAG_COMMON,
  113. .pio_mask = ATA_PIO4,
  114. .udma_mask = ATA_UDMA6,
  115. .port_ops = &ahci_ops,
  116. },
  117. [board_ahci_ign_iferr] = {
  118. AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
  119. .flags = AHCI_FLAG_COMMON,
  120. .pio_mask = ATA_PIO4,
  121. .udma_mask = ATA_UDMA6,
  122. .port_ops = &ahci_ops,
  123. },
  124. [board_ahci_mobile] = {
  125. AHCI_HFLAGS (AHCI_HFLAG_IS_MOBILE),
  126. .flags = AHCI_FLAG_COMMON,
  127. .pio_mask = ATA_PIO4,
  128. .udma_mask = ATA_UDMA6,
  129. .port_ops = &ahci_ops,
  130. },
  131. [board_ahci_nomsi] = {
  132. AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
  133. .flags = AHCI_FLAG_COMMON,
  134. .pio_mask = ATA_PIO4,
  135. .udma_mask = ATA_UDMA6,
  136. .port_ops = &ahci_ops,
  137. },
  138. [board_ahci_noncq] = {
  139. AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
  140. .flags = AHCI_FLAG_COMMON,
  141. .pio_mask = ATA_PIO4,
  142. .udma_mask = ATA_UDMA6,
  143. .port_ops = &ahci_ops,
  144. },
  145. [board_ahci_nosntf] = {
  146. AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
  147. .flags = AHCI_FLAG_COMMON,
  148. .pio_mask = ATA_PIO4,
  149. .udma_mask = ATA_UDMA6,
  150. .port_ops = &ahci_ops,
  151. },
  152. [board_ahci_yes_fbs] = {
  153. AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
  154. .flags = AHCI_FLAG_COMMON,
  155. .pio_mask = ATA_PIO4,
  156. .udma_mask = ATA_UDMA6,
  157. .port_ops = &ahci_ops,
  158. },
  159. /* by chipsets */
  160. [board_ahci_al] = {
  161. AHCI_HFLAGS (AHCI_HFLAG_NO_PMP | AHCI_HFLAG_NO_MSI),
  162. .flags = AHCI_FLAG_COMMON,
  163. .pio_mask = ATA_PIO4,
  164. .udma_mask = ATA_UDMA6,
  165. .port_ops = &ahci_ops,
  166. },
  167. [board_ahci_avn] = {
  168. .flags = AHCI_FLAG_COMMON,
  169. .pio_mask = ATA_PIO4,
  170. .udma_mask = ATA_UDMA6,
  171. .port_ops = &ahci_avn_ops,
  172. },
  173. [board_ahci_mcp65] = {
  174. AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
  175. AHCI_HFLAG_YES_NCQ),
  176. .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
  177. .pio_mask = ATA_PIO4,
  178. .udma_mask = ATA_UDMA6,
  179. .port_ops = &ahci_ops,
  180. },
  181. [board_ahci_mcp77] = {
  182. AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
  183. .flags = AHCI_FLAG_COMMON,
  184. .pio_mask = ATA_PIO4,
  185. .udma_mask = ATA_UDMA6,
  186. .port_ops = &ahci_ops,
  187. },
  188. [board_ahci_mcp89] = {
  189. AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
  190. .flags = AHCI_FLAG_COMMON,
  191. .pio_mask = ATA_PIO4,
  192. .udma_mask = ATA_UDMA6,
  193. .port_ops = &ahci_ops,
  194. },
  195. [board_ahci_mv] = {
  196. AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
  197. AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
  198. .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
  199. .pio_mask = ATA_PIO4,
  200. .udma_mask = ATA_UDMA6,
  201. .port_ops = &ahci_ops,
  202. },
  203. [board_ahci_sb600] = {
  204. AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
  205. AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
  206. AHCI_HFLAG_32BIT_ONLY),
  207. .flags = AHCI_FLAG_COMMON,
  208. .pio_mask = ATA_PIO4,
  209. .udma_mask = ATA_UDMA6,
  210. .port_ops = &ahci_pmp_retry_srst_ops,
  211. },
  212. [board_ahci_sb700] = { /* for SB700 and SB800 */
  213. AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
  214. .flags = AHCI_FLAG_COMMON,
  215. .pio_mask = ATA_PIO4,
  216. .udma_mask = ATA_UDMA6,
  217. .port_ops = &ahci_pmp_retry_srst_ops,
  218. },
  219. [board_ahci_vt8251] = {
  220. AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
  221. .flags = AHCI_FLAG_COMMON,
  222. .pio_mask = ATA_PIO4,
  223. .udma_mask = ATA_UDMA6,
  224. .port_ops = &ahci_vt8251_ops,
  225. },
  226. [board_ahci_pcs7] = {
  227. .flags = AHCI_FLAG_COMMON,
  228. .pio_mask = ATA_PIO4,
  229. .udma_mask = ATA_UDMA6,
  230. .port_ops = &ahci_ops,
  231. },
  232. };
  233. static const struct pci_device_id ahci_pci_tbl[] = {
  234. /* Intel */
  235. { PCI_VDEVICE(INTEL, 0x06d6), board_ahci }, /* Comet Lake PCH-H RAID */
  236. { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
  237. { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
  238. { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
  239. { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
  240. { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
  241. { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
  242. { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
  243. { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
  244. { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
  245. { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
  246. { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
  247. { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
  248. { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
  249. { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
  250. { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
  251. { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
  252. { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
  253. { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
  254. { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
  255. { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
  256. { PCI_VDEVICE(INTEL, 0x2929), board_ahci_mobile }, /* ICH9M */
  257. { PCI_VDEVICE(INTEL, 0x292a), board_ahci_mobile }, /* ICH9M */
  258. { PCI_VDEVICE(INTEL, 0x292b), board_ahci_mobile }, /* ICH9M */
  259. { PCI_VDEVICE(INTEL, 0x292c), board_ahci_mobile }, /* ICH9M */
  260. { PCI_VDEVICE(INTEL, 0x292f), board_ahci_mobile }, /* ICH9M */
  261. { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
  262. { PCI_VDEVICE(INTEL, 0x294e), board_ahci_mobile }, /* ICH9M */
  263. { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
  264. { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
  265. { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
  266. { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
  267. { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
  268. { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
  269. { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
  270. { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
  271. { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
  272. { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_mobile }, /* PCH M AHCI */
  273. { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
  274. { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_mobile }, /* PCH M RAID */
  275. { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
  276. { PCI_VDEVICE(INTEL, 0x19b0), board_ahci_pcs7 }, /* DNV AHCI */
  277. { PCI_VDEVICE(INTEL, 0x19b1), board_ahci_pcs7 }, /* DNV AHCI */
  278. { PCI_VDEVICE(INTEL, 0x19b2), board_ahci_pcs7 }, /* DNV AHCI */
  279. { PCI_VDEVICE(INTEL, 0x19b3), board_ahci_pcs7 }, /* DNV AHCI */
  280. { PCI_VDEVICE(INTEL, 0x19b4), board_ahci_pcs7 }, /* DNV AHCI */
  281. { PCI_VDEVICE(INTEL, 0x19b5), board_ahci_pcs7 }, /* DNV AHCI */
  282. { PCI_VDEVICE(INTEL, 0x19b6), board_ahci_pcs7 }, /* DNV AHCI */
  283. { PCI_VDEVICE(INTEL, 0x19b7), board_ahci_pcs7 }, /* DNV AHCI */
  284. { PCI_VDEVICE(INTEL, 0x19bE), board_ahci_pcs7 }, /* DNV AHCI */
  285. { PCI_VDEVICE(INTEL, 0x19bF), board_ahci_pcs7 }, /* DNV AHCI */
  286. { PCI_VDEVICE(INTEL, 0x19c0), board_ahci_pcs7 }, /* DNV AHCI */
  287. { PCI_VDEVICE(INTEL, 0x19c1), board_ahci_pcs7 }, /* DNV AHCI */
  288. { PCI_VDEVICE(INTEL, 0x19c2), board_ahci_pcs7 }, /* DNV AHCI */
  289. { PCI_VDEVICE(INTEL, 0x19c3), board_ahci_pcs7 }, /* DNV AHCI */
  290. { PCI_VDEVICE(INTEL, 0x19c4), board_ahci_pcs7 }, /* DNV AHCI */
  291. { PCI_VDEVICE(INTEL, 0x19c5), board_ahci_pcs7 }, /* DNV AHCI */
  292. { PCI_VDEVICE(INTEL, 0x19c6), board_ahci_pcs7 }, /* DNV AHCI */
  293. { PCI_VDEVICE(INTEL, 0x19c7), board_ahci_pcs7 }, /* DNV AHCI */
  294. { PCI_VDEVICE(INTEL, 0x19cE), board_ahci_pcs7 }, /* DNV AHCI */
  295. { PCI_VDEVICE(INTEL, 0x19cF), board_ahci_pcs7 }, /* DNV AHCI */
  296. { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
  297. { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_mobile }, /* CPT M AHCI */
  298. { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
  299. { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_mobile }, /* CPT M RAID */
  300. { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
  301. { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
  302. { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
  303. { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
  304. { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
  305. { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
  306. { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
  307. { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
  308. { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_mobile }, /* Panther M AHCI */
  309. { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
  310. { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
  311. { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
  312. { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_mobile }, /* Panther M RAID */
  313. { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
  314. { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
  315. { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_mobile }, /* Lynx M AHCI */
  316. { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
  317. { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_mobile }, /* Lynx M RAID */
  318. { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
  319. { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_mobile }, /* Lynx M RAID */
  320. { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
  321. { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_mobile }, /* Lynx M RAID */
  322. { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_mobile }, /* Lynx LP AHCI */
  323. { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_mobile }, /* Lynx LP AHCI */
  324. { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_mobile }, /* Lynx LP RAID */
  325. { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_mobile }, /* Lynx LP RAID */
  326. { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_mobile }, /* Lynx LP RAID */
  327. { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_mobile }, /* Lynx LP RAID */
  328. { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_mobile }, /* Lynx LP RAID */
  329. { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_mobile }, /* Lynx LP RAID */
  330. { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_mobile }, /* Cannon Lake PCH-LP AHCI */
  331. { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
  332. { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
  333. { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
  334. { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
  335. { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
  336. { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
  337. { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
  338. { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
  339. { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
  340. { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
  341. { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
  342. { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
  343. { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
  344. { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
  345. { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
  346. { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
  347. { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
  348. { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
  349. { PCI_VDEVICE(INTEL, 0x43d4), board_ahci }, /* Rocket Lake PCH-H RAID */
  350. { PCI_VDEVICE(INTEL, 0x43d5), board_ahci }, /* Rocket Lake PCH-H RAID */
  351. { PCI_VDEVICE(INTEL, 0x43d6), board_ahci }, /* Rocket Lake PCH-H RAID */
  352. { PCI_VDEVICE(INTEL, 0x43d7), board_ahci }, /* Rocket Lake PCH-H RAID */
  353. { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
  354. { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
  355. { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
  356. { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
  357. { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
  358. { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
  359. { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
  360. { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
  361. { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
  362. { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_mobile }, /* Wildcat LP AHCI */
  363. { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_mobile }, /* Wildcat LP RAID */
  364. { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_mobile }, /* Wildcat LP RAID */
  365. { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_mobile }, /* Wildcat LP RAID */
  366. { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
  367. { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_mobile }, /* 9 Series M AHCI */
  368. { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
  369. { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_mobile }, /* 9 Series M RAID */
  370. { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
  371. { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_mobile }, /* 9 Series M RAID */
  372. { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
  373. { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_mobile }, /* 9 Series M RAID */
  374. { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_mobile }, /* Sunrise LP AHCI */
  375. { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_mobile }, /* Sunrise LP RAID */
  376. { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_mobile }, /* Sunrise LP RAID */
  377. { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
  378. { PCI_VDEVICE(INTEL, 0xa103), board_ahci_mobile }, /* Sunrise M AHCI */
  379. { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
  380. { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
  381. { PCI_VDEVICE(INTEL, 0xa107), board_ahci_mobile }, /* Sunrise M RAID */
  382. { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
  383. { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/
  384. { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/
  385. { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/
  386. { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Lewisburg RAID*/
  387. { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
  388. { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
  389. { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/
  390. { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/
  391. { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
  392. { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
  393. { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/
  394. { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
  395. { PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */
  396. { PCI_VDEVICE(INTEL, 0x06d7), board_ahci }, /* Comet Lake-H RAID */
  397. { PCI_VDEVICE(INTEL, 0xa386), board_ahci }, /* Comet Lake PCH-V RAID */
  398. { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_mobile }, /* Bay Trail AHCI */
  399. { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_mobile }, /* Bay Trail AHCI */
  400. { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_mobile }, /* Cherry Tr. AHCI */
  401. { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_mobile }, /* ApolloLake AHCI */
  402. { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_mobile }, /* Ice Lake LP AHCI */
  403. { PCI_VDEVICE(INTEL, 0x02d3), board_ahci_mobile }, /* Comet Lake PCH-U AHCI */
  404. { PCI_VDEVICE(INTEL, 0x02d7), board_ahci_mobile }, /* Comet Lake PCH RAID */
  405. /* JMicron 360/1/3/5/6, match class to avoid IDE function */
  406. { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
  407. PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
  408. /* JMicron 362B and 362C have an AHCI function with IDE class code */
  409. { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
  410. { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
  411. /* May need to update quirk_jmicron_async_suspend() for additions */
  412. /* ATI */
  413. { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
  414. { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
  415. { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
  416. { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
  417. { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
  418. { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
  419. { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
  420. /* Amazon's Annapurna Labs support */
  421. { PCI_DEVICE(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031),
  422. .class = PCI_CLASS_STORAGE_SATA_AHCI,
  423. .class_mask = 0xffffff,
  424. board_ahci_al },
  425. /* AMD */
  426. { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
  427. { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
  428. { PCI_VDEVICE(AMD, 0x7901), board_ahci_mobile }, /* AMD Green Sardine */
  429. /* AMD is using RAID class only for ahci controllers */
  430. { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
  431. PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
  432. /* VIA */
  433. { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
  434. { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
  435. /* NVIDIA */
  436. { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
  437. { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
  438. { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
  439. { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
  440. { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
  441. { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
  442. { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
  443. { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
  444. { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
  445. { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
  446. { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
  447. { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
  448. { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
  449. { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
  450. { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
  451. { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
  452. { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
  453. { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
  454. { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
  455. { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
  456. { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
  457. { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
  458. { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
  459. { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
  460. { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
  461. { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
  462. { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
  463. { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
  464. { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
  465. { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
  466. { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
  467. { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
  468. { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
  469. { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
  470. { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
  471. { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
  472. { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
  473. { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
  474. { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
  475. { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
  476. { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
  477. { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
  478. { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
  479. { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
  480. { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
  481. { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
  482. { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
  483. { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
  484. { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
  485. { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
  486. { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
  487. { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
  488. { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
  489. { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
  490. { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
  491. { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
  492. { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
  493. { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
  494. { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
  495. { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
  496. { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
  497. { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
  498. { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
  499. { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
  500. { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
  501. { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
  502. { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
  503. { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
  504. { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
  505. { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
  506. { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
  507. { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
  508. { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
  509. { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
  510. { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
  511. { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
  512. { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
  513. { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
  514. { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
  515. { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
  516. { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
  517. { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
  518. { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
  519. { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
  520. /* SiS */
  521. { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
  522. { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
  523. { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
  524. /* ST Microelectronics */
  525. { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
  526. /* Marvell */
  527. { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
  528. { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
  529. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
  530. .class = PCI_CLASS_STORAGE_SATA_AHCI,
  531. .class_mask = 0xffffff,
  532. .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
  533. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
  534. .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
  535. { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
  536. PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
  537. .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
  538. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
  539. .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
  540. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
  541. .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
  542. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
  543. .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
  544. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
  545. .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
  546. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
  547. .driver_data = board_ahci_yes_fbs },
  548. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */
  549. .driver_data = board_ahci_yes_fbs },
  550. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
  551. .driver_data = board_ahci_yes_fbs },
  552. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
  553. .driver_data = board_ahci_yes_fbs },
  554. { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */
  555. .driver_data = board_ahci_yes_fbs },
  556. { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */
  557. .driver_data = board_ahci_yes_fbs },
  558. /* Promise */
  559. { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
  560. { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
  561. /* Asmedia */
  562. { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
  563. { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
  564. { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
  565. { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
  566. { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci }, /* ASM1061R */
  567. { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci }, /* ASM1062R */
  568. /*
  569. * Samsung SSDs found on some macbooks. NCQ times out if MSI is
  570. * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
  571. */
  572. { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
  573. { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
  574. /* Enmotus */
  575. { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
  576. /* Loongson */
  577. { PCI_VDEVICE(LOONGSON, 0x7a08), board_ahci },
  578. /* Generic, PCI class code for AHCI */
  579. { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
  580. PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
  581. { } /* terminate list */
  582. };
  583. static const struct dev_pm_ops ahci_pci_pm_ops = {
  584. SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume)
  585. SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend,
  586. ahci_pci_device_runtime_resume, NULL)
  587. };
  588. static struct pci_driver ahci_pci_driver = {
  589. .name = DRV_NAME,
  590. .id_table = ahci_pci_tbl,
  591. .probe = ahci_init_one,
  592. .remove = ahci_remove_one,
  593. .shutdown = ahci_shutdown_one,
  594. .driver = {
  595. .pm = &ahci_pci_pm_ops,
  596. },
  597. };
  598. #if IS_ENABLED(CONFIG_PATA_MARVELL)
  599. static int marvell_enable;
  600. #else
  601. static int marvell_enable = 1;
  602. #endif
  603. module_param(marvell_enable, int, 0644);
  604. MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
  605. static int mobile_lpm_policy = -1;
  606. module_param(mobile_lpm_policy, int, 0644);
  607. MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets");
  608. static void ahci_pci_save_initial_config(struct pci_dev *pdev,
  609. struct ahci_host_priv *hpriv)
  610. {
  611. if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
  612. dev_info(&pdev->dev, "JMB361 has only one port\n");
  613. hpriv->force_port_map = 1;
  614. }
  615. /*
  616. * Temporary Marvell 6145 hack: PATA port presence
  617. * is asserted through the standard AHCI port
  618. * presence register, as bit 4 (counting from 0)
  619. */
  620. if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
  621. if (pdev->device == 0x6121)
  622. hpriv->mask_port_map = 0x3;
  623. else
  624. hpriv->mask_port_map = 0xf;
  625. dev_info(&pdev->dev,
  626. "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
  627. }
  628. ahci_save_initial_config(&pdev->dev, hpriv);
  629. }
  630. static void ahci_pci_init_controller(struct ata_host *host)
  631. {
  632. struct ahci_host_priv *hpriv = host->private_data;
  633. struct pci_dev *pdev = to_pci_dev(host->dev);
  634. void __iomem *port_mmio;
  635. u32 tmp;
  636. int mv;
  637. if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
  638. if (pdev->device == 0x6121)
  639. mv = 2;
  640. else
  641. mv = 4;
  642. port_mmio = __ahci_port_base(host, mv);
  643. writel(0, port_mmio + PORT_IRQ_MASK);
  644. /* clear port IRQ */
  645. tmp = readl(port_mmio + PORT_IRQ_STAT);
  646. VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
  647. if (tmp)
  648. writel(tmp, port_mmio + PORT_IRQ_STAT);
  649. }
  650. ahci_init_controller(host);
  651. }
  652. static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
  653. unsigned long deadline)
  654. {
  655. struct ata_port *ap = link->ap;
  656. struct ahci_host_priv *hpriv = ap->host->private_data;
  657. bool online;
  658. int rc;
  659. DPRINTK("ENTER\n");
  660. hpriv->stop_engine(ap);
  661. rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
  662. deadline, &online, NULL);
  663. hpriv->start_engine(ap);
  664. DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
  665. /* vt8251 doesn't clear BSY on signature FIS reception,
  666. * request follow-up softreset.
  667. */
  668. return online ? -EAGAIN : rc;
  669. }
  670. static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
  671. unsigned long deadline)
  672. {
  673. struct ata_port *ap = link->ap;
  674. struct ahci_port_priv *pp = ap->private_data;
  675. struct ahci_host_priv *hpriv = ap->host->private_data;
  676. u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
  677. struct ata_taskfile tf;
  678. bool online;
  679. int rc;
  680. hpriv->stop_engine(ap);
  681. /* clear D2H reception area to properly wait for D2H FIS */
  682. ata_tf_init(link->device, &tf);
  683. tf.command = ATA_BUSY;
  684. ata_tf_to_fis(&tf, 0, 0, d2h_fis);
  685. rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
  686. deadline, &online, NULL);
  687. hpriv->start_engine(ap);
  688. /* The pseudo configuration device on SIMG4726 attached to
  689. * ASUS P5W-DH Deluxe doesn't send signature FIS after
  690. * hardreset if no device is attached to the first downstream
  691. * port && the pseudo device locks up on SRST w/ PMP==0. To
  692. * work around this, wait for !BSY only briefly. If BSY isn't
  693. * cleared, perform CLO and proceed to IDENTIFY (achieved by
  694. * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
  695. *
  696. * Wait for two seconds. Devices attached to downstream port
  697. * which can't process the following IDENTIFY after this will
  698. * have to be reset again. For most cases, this should
  699. * suffice while making probing snappish enough.
  700. */
  701. if (online) {
  702. rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
  703. ahci_check_ready);
  704. if (rc)
  705. ahci_kick_engine(ap);
  706. }
  707. return rc;
  708. }
  709. /*
  710. * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
  711. *
  712. * It has been observed with some SSDs that the timing of events in the
  713. * link synchronization phase can leave the port in a state that can not
  714. * be recovered by a SATA-hard-reset alone. The failing signature is
  715. * SStatus.DET stuck at 1 ("Device presence detected but Phy
  716. * communication not established"). It was found that unloading and
  717. * reloading the driver when this problem occurs allows the drive
  718. * connection to be recovered (DET advanced to 0x3). The critical
  719. * component of reloading the driver is that the port state machines are
  720. * reset by bouncing "port enable" in the AHCI PCS configuration
  721. * register. So, reproduce that effect by bouncing a port whenever we
  722. * see DET==1 after a reset.
  723. */
  724. static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
  725. unsigned long deadline)
  726. {
  727. const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
  728. struct ata_port *ap = link->ap;
  729. struct ahci_port_priv *pp = ap->private_data;
  730. struct ahci_host_priv *hpriv = ap->host->private_data;
  731. u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
  732. unsigned long tmo = deadline - jiffies;
  733. struct ata_taskfile tf;
  734. bool online;
  735. int rc, i;
  736. DPRINTK("ENTER\n");
  737. hpriv->stop_engine(ap);
  738. for (i = 0; i < 2; i++) {
  739. u16 val;
  740. u32 sstatus;
  741. int port = ap->port_no;
  742. struct ata_host *host = ap->host;
  743. struct pci_dev *pdev = to_pci_dev(host->dev);
  744. /* clear D2H reception area to properly wait for D2H FIS */
  745. ata_tf_init(link->device, &tf);
  746. tf.command = ATA_BUSY;
  747. ata_tf_to_fis(&tf, 0, 0, d2h_fis);
  748. rc = sata_link_hardreset(link, timing, deadline, &online,
  749. ahci_check_ready);
  750. if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
  751. (sstatus & 0xf) != 1)
  752. break;
  753. ata_link_info(link, "avn bounce port%d\n", port);
  754. pci_read_config_word(pdev, 0x92, &val);
  755. val &= ~(1 << port);
  756. pci_write_config_word(pdev, 0x92, val);
  757. ata_msleep(ap, 1000);
  758. val |= 1 << port;
  759. pci_write_config_word(pdev, 0x92, val);
  760. deadline += tmo;
  761. }
  762. hpriv->start_engine(ap);
  763. if (online)
  764. *class = ahci_dev_classify(ap);
  765. DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
  766. return rc;
  767. }
  768. #ifdef CONFIG_PM
  769. static void ahci_pci_disable_interrupts(struct ata_host *host)
  770. {
  771. struct ahci_host_priv *hpriv = host->private_data;
  772. void __iomem *mmio = hpriv->mmio;
  773. u32 ctl;
  774. /* AHCI spec rev1.1 section 8.3.3:
  775. * Software must disable interrupts prior to requesting a
  776. * transition of the HBA to D3 state.
  777. */
  778. ctl = readl(mmio + HOST_CTL);
  779. ctl &= ~HOST_IRQ_EN;
  780. writel(ctl, mmio + HOST_CTL);
  781. readl(mmio + HOST_CTL); /* flush */
  782. }
  783. static int ahci_pci_device_runtime_suspend(struct device *dev)
  784. {
  785. struct pci_dev *pdev = to_pci_dev(dev);
  786. struct ata_host *host = pci_get_drvdata(pdev);
  787. ahci_pci_disable_interrupts(host);
  788. return 0;
  789. }
  790. static int ahci_pci_device_runtime_resume(struct device *dev)
  791. {
  792. struct pci_dev *pdev = to_pci_dev(dev);
  793. struct ata_host *host = pci_get_drvdata(pdev);
  794. int rc;
  795. rc = ahci_reset_controller(host);
  796. if (rc)
  797. return rc;
  798. ahci_pci_init_controller(host);
  799. return 0;
  800. }
  801. #ifdef CONFIG_PM_SLEEP
  802. static int ahci_pci_device_suspend(struct device *dev)
  803. {
  804. struct pci_dev *pdev = to_pci_dev(dev);
  805. struct ata_host *host = pci_get_drvdata(pdev);
  806. struct ahci_host_priv *hpriv = host->private_data;
  807. if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
  808. dev_err(&pdev->dev,
  809. "BIOS update required for suspend/resume\n");
  810. return -EIO;
  811. }
  812. ahci_pci_disable_interrupts(host);
  813. return ata_host_suspend(host, PMSG_SUSPEND);
  814. }
  815. static int ahci_pci_device_resume(struct device *dev)
  816. {
  817. struct pci_dev *pdev = to_pci_dev(dev);
  818. struct ata_host *host = pci_get_drvdata(pdev);
  819. int rc;
  820. /* Apple BIOS helpfully mangles the registers on resume */
  821. if (is_mcp89_apple(pdev))
  822. ahci_mcp89_apple_enable(pdev);
  823. if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
  824. rc = ahci_reset_controller(host);
  825. if (rc)
  826. return rc;
  827. ahci_pci_init_controller(host);
  828. }
  829. ata_host_resume(host);
  830. return 0;
  831. }
  832. #endif
  833. #endif /* CONFIG_PM */
  834. static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
  835. {
  836. const int dma_bits = using_dac ? 64 : 32;
  837. int rc;
  838. /*
  839. * If the device fixup already set the dma_mask to some non-standard
  840. * value, don't extend it here. This happens on STA2X11, for example.
  841. *
  842. * XXX: manipulating the DMA mask from platform code is completely
  843. * bogus, platform code should use dev->bus_dma_limit instead..
  844. */
  845. if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
  846. return 0;
  847. rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits));
  848. if (rc)
  849. dev_err(&pdev->dev, "DMA enable failed\n");
  850. return rc;
  851. }
  852. static void ahci_pci_print_info(struct ata_host *host)
  853. {
  854. struct pci_dev *pdev = to_pci_dev(host->dev);
  855. u16 cc;
  856. const char *scc_s;
  857. pci_read_config_word(pdev, 0x0a, &cc);
  858. if (cc == PCI_CLASS_STORAGE_IDE)
  859. scc_s = "IDE";
  860. else if (cc == PCI_CLASS_STORAGE_SATA)
  861. scc_s = "SATA";
  862. else if (cc == PCI_CLASS_STORAGE_RAID)
  863. scc_s = "RAID";
  864. else
  865. scc_s = "unknown";
  866. ahci_print_info(host, scc_s);
  867. }
  868. /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
  869. * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
  870. * support PMP and the 4726 either directly exports the device
  871. * attached to the first downstream port or acts as a hardware storage
  872. * controller and emulate a single ATA device (can be RAID 0/1 or some
  873. * other configuration).
  874. *
  875. * When there's no device attached to the first downstream port of the
  876. * 4726, "Config Disk" appears, which is a pseudo ATA device to
  877. * configure the 4726. However, ATA emulation of the device is very
  878. * lame. It doesn't send signature D2H Reg FIS after the initial
  879. * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
  880. *
  881. * The following function works around the problem by always using
  882. * hardreset on the port and not depending on receiving signature FIS
  883. * afterward. If signature FIS isn't received soon, ATA class is
  884. * assumed without follow-up softreset.
  885. */
  886. static void ahci_p5wdh_workaround(struct ata_host *host)
  887. {
  888. static const struct dmi_system_id sysids[] = {
  889. {
  890. .ident = "P5W DH Deluxe",
  891. .matches = {
  892. DMI_MATCH(DMI_SYS_VENDOR,
  893. "ASUSTEK COMPUTER INC"),
  894. DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
  895. },
  896. },
  897. { }
  898. };
  899. struct pci_dev *pdev = to_pci_dev(host->dev);
  900. if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
  901. dmi_check_system(sysids)) {
  902. struct ata_port *ap = host->ports[1];
  903. dev_info(&pdev->dev,
  904. "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
  905. ap->ops = &ahci_p5wdh_ops;
  906. ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
  907. }
  908. }
  909. /*
  910. * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
  911. * booting in BIOS compatibility mode. We restore the registers but not ID.
  912. */
  913. static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
  914. {
  915. u32 val;
  916. printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
  917. pci_read_config_dword(pdev, 0xf8, &val);
  918. val |= 1 << 0x1b;
  919. /* the following changes the device ID, but appears not to affect function */
  920. /* val = (val & ~0xf0000000) | 0x80000000; */
  921. pci_write_config_dword(pdev, 0xf8, val);
  922. pci_read_config_dword(pdev, 0x54c, &val);
  923. val |= 1 << 0xc;
  924. pci_write_config_dword(pdev, 0x54c, val);
  925. pci_read_config_dword(pdev, 0x4a4, &val);
  926. val &= 0xff;
  927. val |= 0x01060100;
  928. pci_write_config_dword(pdev, 0x4a4, val);
  929. pci_read_config_dword(pdev, 0x54c, &val);
  930. val &= ~(1 << 0xc);
  931. pci_write_config_dword(pdev, 0x54c, val);
  932. pci_read_config_dword(pdev, 0xf8, &val);
  933. val &= ~(1 << 0x1b);
  934. pci_write_config_dword(pdev, 0xf8, val);
  935. }
  936. static bool is_mcp89_apple(struct pci_dev *pdev)
  937. {
  938. return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
  939. pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
  940. pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
  941. pdev->subsystem_device == 0xcb89;
  942. }
  943. /* only some SB600 ahci controllers can do 64bit DMA */
  944. static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
  945. {
  946. static const struct dmi_system_id sysids[] = {
  947. /*
  948. * The oldest version known to be broken is 0901 and
  949. * working is 1501 which was released on 2007-10-26.
  950. * Enable 64bit DMA on 1501 and anything newer.
  951. *
  952. * Please read bko#9412 for more info.
  953. */
  954. {
  955. .ident = "ASUS M2A-VM",
  956. .matches = {
  957. DMI_MATCH(DMI_BOARD_VENDOR,
  958. "ASUSTeK Computer INC."),
  959. DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
  960. },
  961. .driver_data = "20071026", /* yyyymmdd */
  962. },
  963. /*
  964. * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
  965. * support 64bit DMA.
  966. *
  967. * BIOS versions earlier than 1.5 had the Manufacturer DMI
  968. * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
  969. * This spelling mistake was fixed in BIOS version 1.5, so
  970. * 1.5 and later have the Manufacturer as
  971. * "MICRO-STAR INTERNATIONAL CO.,LTD".
  972. * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
  973. *
  974. * BIOS versions earlier than 1.9 had a Board Product Name
  975. * DMI field of "MS-7376". This was changed to be
  976. * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
  977. * match on DMI_BOARD_NAME of "MS-7376".
  978. */
  979. {
  980. .ident = "MSI K9A2 Platinum",
  981. .matches = {
  982. DMI_MATCH(DMI_BOARD_VENDOR,
  983. "MICRO-STAR INTER"),
  984. DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
  985. },
  986. },
  987. /*
  988. * All BIOS versions for the MSI K9AGM2 (MS-7327) support
  989. * 64bit DMA.
  990. *
  991. * This board also had the typo mentioned above in the
  992. * Manufacturer DMI field (fixed in BIOS version 1.5), so
  993. * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
  994. */
  995. {
  996. .ident = "MSI K9AGM2",
  997. .matches = {
  998. DMI_MATCH(DMI_BOARD_VENDOR,
  999. "MICRO-STAR INTER"),
  1000. DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
  1001. },
  1002. },
  1003. /*
  1004. * All BIOS versions for the Asus M3A support 64bit DMA.
  1005. * (all release versions from 0301 to 1206 were tested)
  1006. */
  1007. {
  1008. .ident = "ASUS M3A",
  1009. .matches = {
  1010. DMI_MATCH(DMI_BOARD_VENDOR,
  1011. "ASUSTeK Computer INC."),
  1012. DMI_MATCH(DMI_BOARD_NAME, "M3A"),
  1013. },
  1014. },
  1015. { }
  1016. };
  1017. const struct dmi_system_id *match;
  1018. int year, month, date;
  1019. char buf[9];
  1020. match = dmi_first_match(sysids);
  1021. if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
  1022. !match)
  1023. return false;
  1024. if (!match->driver_data)
  1025. goto enable_64bit;
  1026. dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
  1027. snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
  1028. if (strcmp(buf, match->driver_data) >= 0)
  1029. goto enable_64bit;
  1030. else {
  1031. dev_warn(&pdev->dev,
  1032. "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
  1033. match->ident);
  1034. return false;
  1035. }
  1036. enable_64bit:
  1037. dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
  1038. return true;
  1039. }
  1040. static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
  1041. {
  1042. static const struct dmi_system_id broken_systems[] = {
  1043. {
  1044. .ident = "HP Compaq nx6310",
  1045. .matches = {
  1046. DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
  1047. DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
  1048. },
  1049. /* PCI slot number of the controller */
  1050. .driver_data = (void *)0x1FUL,
  1051. },
  1052. {
  1053. .ident = "HP Compaq 6720s",
  1054. .matches = {
  1055. DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
  1056. DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
  1057. },
  1058. /* PCI slot number of the controller */
  1059. .driver_data = (void *)0x1FUL,
  1060. },
  1061. { } /* terminate list */
  1062. };
  1063. const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
  1064. if (dmi) {
  1065. unsigned long slot = (unsigned long)dmi->driver_data;
  1066. /* apply the quirk only to on-board controllers */
  1067. return slot == PCI_SLOT(pdev->devfn);
  1068. }
  1069. return false;
  1070. }
  1071. static bool ahci_broken_suspend(struct pci_dev *pdev)
  1072. {
  1073. static const struct dmi_system_id sysids[] = {
  1074. /*
  1075. * On HP dv[4-6] and HDX18 with earlier BIOSen, link
  1076. * to the harddisk doesn't become online after
  1077. * resuming from STR. Warn and fail suspend.
  1078. *
  1079. * http://bugzilla.kernel.org/show_bug.cgi?id=12276
  1080. *
  1081. * Use dates instead of versions to match as HP is
  1082. * apparently recycling both product and version
  1083. * strings.
  1084. *
  1085. * http://bugzilla.kernel.org/show_bug.cgi?id=15462
  1086. */
  1087. {
  1088. .ident = "dv4",
  1089. .matches = {
  1090. DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
  1091. DMI_MATCH(DMI_PRODUCT_NAME,
  1092. "HP Pavilion dv4 Notebook PC"),
  1093. },
  1094. .driver_data = "20090105", /* F.30 */
  1095. },
  1096. {
  1097. .ident = "dv5",
  1098. .matches = {
  1099. DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
  1100. DMI_MATCH(DMI_PRODUCT_NAME,
  1101. "HP Pavilion dv5 Notebook PC"),
  1102. },
  1103. .driver_data = "20090506", /* F.16 */
  1104. },
  1105. {
  1106. .ident = "dv6",
  1107. .matches = {
  1108. DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
  1109. DMI_MATCH(DMI_PRODUCT_NAME,
  1110. "HP Pavilion dv6 Notebook PC"),
  1111. },
  1112. .driver_data = "20090423", /* F.21 */
  1113. },
  1114. {
  1115. .ident = "HDX18",
  1116. .matches = {
  1117. DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
  1118. DMI_MATCH(DMI_PRODUCT_NAME,
  1119. "HP HDX18 Notebook PC"),
  1120. },
  1121. .driver_data = "20090430", /* F.23 */
  1122. },
  1123. /*
  1124. * Acer eMachines G725 has the same problem. BIOS
  1125. * V1.03 is known to be broken. V3.04 is known to
  1126. * work. Between, there are V1.06, V2.06 and V3.03
  1127. * that we don't have much idea about. For now,
  1128. * blacklist anything older than V3.04.
  1129. *
  1130. * http://bugzilla.kernel.org/show_bug.cgi?id=15104
  1131. */
  1132. {
  1133. .ident = "G725",
  1134. .matches = {
  1135. DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
  1136. DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
  1137. },
  1138. .driver_data = "20091216", /* V3.04 */
  1139. },
  1140. { } /* terminate list */
  1141. };
  1142. const struct dmi_system_id *dmi = dmi_first_match(sysids);
  1143. int year, month, date;
  1144. char buf[9];
  1145. if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
  1146. return false;
  1147. dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
  1148. snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
  1149. return strcmp(buf, dmi->driver_data) < 0;
  1150. }
  1151. static bool ahci_broken_lpm(struct pci_dev *pdev)
  1152. {
  1153. static const struct dmi_system_id sysids[] = {
  1154. /* Various Lenovo 50 series have LPM issues with older BIOSen */
  1155. {
  1156. .matches = {
  1157. DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
  1158. DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"),
  1159. },
  1160. .driver_data = "20180406", /* 1.31 */
  1161. },
  1162. {
  1163. .matches = {
  1164. DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
  1165. DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"),
  1166. },
  1167. .driver_data = "20180420", /* 1.28 */
  1168. },
  1169. {
  1170. .matches = {
  1171. DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
  1172. DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"),
  1173. },
  1174. .driver_data = "20180315", /* 1.33 */
  1175. },
  1176. {
  1177. .matches = {
  1178. DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
  1179. DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"),
  1180. },
  1181. /*
  1182. * Note date based on release notes, 2.35 has been
  1183. * reported to be good, but I've been unable to get
  1184. * a hold of the reporter to get the DMI BIOS date.
  1185. * TODO: fix this.
  1186. */
  1187. .driver_data = "20180310", /* 2.35 */
  1188. },
  1189. { } /* terminate list */
  1190. };
  1191. const struct dmi_system_id *dmi = dmi_first_match(sysids);
  1192. int year, month, date;
  1193. char buf[9];
  1194. if (!dmi)
  1195. return false;
  1196. dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
  1197. snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
  1198. return strcmp(buf, dmi->driver_data) < 0;
  1199. }
  1200. static bool ahci_broken_online(struct pci_dev *pdev)
  1201. {
  1202. #define ENCODE_BUSDEVFN(bus, slot, func) \
  1203. (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
  1204. static const struct dmi_system_id sysids[] = {
  1205. /*
  1206. * There are several gigabyte boards which use
  1207. * SIMG5723s configured as hardware RAID. Certain
  1208. * 5723 firmware revisions shipped there keep the link
  1209. * online but fail to answer properly to SRST or
  1210. * IDENTIFY when no device is attached downstream
  1211. * causing libata to retry quite a few times leading
  1212. * to excessive detection delay.
  1213. *
  1214. * As these firmwares respond to the second reset try
  1215. * with invalid device signature, considering unknown
  1216. * sig as offline works around the problem acceptably.
  1217. */
  1218. {
  1219. .ident = "EP45-DQ6",
  1220. .matches = {
  1221. DMI_MATCH(DMI_BOARD_VENDOR,
  1222. "Gigabyte Technology Co., Ltd."),
  1223. DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
  1224. },
  1225. .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
  1226. },
  1227. {
  1228. .ident = "EP45-DS5",
  1229. .matches = {
  1230. DMI_MATCH(DMI_BOARD_VENDOR,
  1231. "Gigabyte Technology Co., Ltd."),
  1232. DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
  1233. },
  1234. .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
  1235. },
  1236. { } /* terminate list */
  1237. };
  1238. #undef ENCODE_BUSDEVFN
  1239. const struct dmi_system_id *dmi = dmi_first_match(sysids);
  1240. unsigned int val;
  1241. if (!dmi)
  1242. return false;
  1243. val = (unsigned long)dmi->driver_data;
  1244. return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
  1245. }
  1246. static bool ahci_broken_devslp(struct pci_dev *pdev)
  1247. {
  1248. /* device with broken DEVSLP but still showing SDS capability */
  1249. static const struct pci_device_id ids[] = {
  1250. { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
  1251. {}
  1252. };
  1253. return pci_match_id(ids, pdev);
  1254. }
  1255. #ifdef CONFIG_ATA_ACPI
  1256. static void ahci_gtf_filter_workaround(struct ata_host *host)
  1257. {
  1258. static const struct dmi_system_id sysids[] = {
  1259. /*
  1260. * Aspire 3810T issues a bunch of SATA enable commands
  1261. * via _GTF including an invalid one and one which is
  1262. * rejected by the device. Among the successful ones
  1263. * is FPDMA non-zero offset enable which when enabled
  1264. * only on the drive side leads to NCQ command
  1265. * failures. Filter it out.
  1266. */
  1267. {
  1268. .ident = "Aspire 3810T",
  1269. .matches = {
  1270. DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
  1271. DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
  1272. },
  1273. .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
  1274. },
  1275. { }
  1276. };
  1277. const struct dmi_system_id *dmi = dmi_first_match(sysids);
  1278. unsigned int filter;
  1279. int i;
  1280. if (!dmi)
  1281. return;
  1282. filter = (unsigned long)dmi->driver_data;
  1283. dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
  1284. filter, dmi->ident);
  1285. for (i = 0; i < host->n_ports; i++) {
  1286. struct ata_port *ap = host->ports[i];
  1287. struct ata_link *link;
  1288. struct ata_device *dev;
  1289. ata_for_each_link(link, ap, EDGE)
  1290. ata_for_each_dev(dev, link, ALL)
  1291. dev->gtf_filter |= filter;
  1292. }
  1293. }
  1294. #else
  1295. static inline void ahci_gtf_filter_workaround(struct ata_host *host)
  1296. {}
  1297. #endif
  1298. /*
  1299. * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected
  1300. * as DUMMY, or detected but eventually get a "link down" and never get up
  1301. * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the
  1302. * port_map may hold a value of 0x00.
  1303. *
  1304. * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports
  1305. * and can significantly reduce the occurrence of the problem.
  1306. *
  1307. * https://bugzilla.kernel.org/show_bug.cgi?id=189471
  1308. */
  1309. static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv,
  1310. struct pci_dev *pdev)
  1311. {
  1312. static const struct dmi_system_id sysids[] = {
  1313. {
  1314. .ident = "Acer Switch Alpha 12",
  1315. .matches = {
  1316. DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
  1317. DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271")
  1318. },
  1319. },
  1320. { }
  1321. };
  1322. if (dmi_check_system(sysids)) {
  1323. dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n");
  1324. if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) {
  1325. hpriv->port_map = 0x7;
  1326. hpriv->cap = 0xC734FF02;
  1327. }
  1328. }
  1329. }
  1330. #ifdef CONFIG_ARM64
  1331. /*
  1332. * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently.
  1333. * Workaround is to make sure all pending IRQs are served before leaving
  1334. * handler.
  1335. */
  1336. static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
  1337. {
  1338. struct ata_host *host = dev_instance;
  1339. struct ahci_host_priv *hpriv;
  1340. unsigned int rc = 0;
  1341. void __iomem *mmio;
  1342. u32 irq_stat, irq_masked;
  1343. unsigned int handled = 1;
  1344. VPRINTK("ENTER\n");
  1345. hpriv = host->private_data;
  1346. mmio = hpriv->mmio;
  1347. irq_stat = readl(mmio + HOST_IRQ_STAT);
  1348. if (!irq_stat)
  1349. return IRQ_NONE;
  1350. do {
  1351. irq_masked = irq_stat & hpriv->port_map;
  1352. spin_lock(&host->lock);
  1353. rc = ahci_handle_port_intr(host, irq_masked);
  1354. if (!rc)
  1355. handled = 0;
  1356. writel(irq_stat, mmio + HOST_IRQ_STAT);
  1357. irq_stat = readl(mmio + HOST_IRQ_STAT);
  1358. spin_unlock(&host->lock);
  1359. } while (irq_stat);
  1360. VPRINTK("EXIT\n");
  1361. return IRQ_RETVAL(handled);
  1362. }
  1363. #endif
  1364. static void ahci_remap_check(struct pci_dev *pdev, int bar,
  1365. struct ahci_host_priv *hpriv)
  1366. {
  1367. int i;
  1368. u32 cap;
  1369. /*
  1370. * Check if this device might have remapped nvme devices.
  1371. */
  1372. if (pdev->vendor != PCI_VENDOR_ID_INTEL ||
  1373. pci_resource_len(pdev, bar) < SZ_512K ||
  1374. bar != AHCI_PCI_BAR_STANDARD ||
  1375. !(readl(hpriv->mmio + AHCI_VSCAP) & 1))
  1376. return;
  1377. cap = readq(hpriv->mmio + AHCI_REMAP_CAP);
  1378. for (i = 0; i < AHCI_MAX_REMAP; i++) {
  1379. if ((cap & (1 << i)) == 0)
  1380. continue;
  1381. if (readl(hpriv->mmio + ahci_remap_dcc(i))
  1382. != PCI_CLASS_STORAGE_EXPRESS)
  1383. continue;
  1384. /* We've found a remapped device */
  1385. hpriv->remapped_nvme++;
  1386. }
  1387. if (!hpriv->remapped_nvme)
  1388. return;
  1389. dev_warn(&pdev->dev, "Found %u remapped NVMe devices.\n",
  1390. hpriv->remapped_nvme);
  1391. dev_warn(&pdev->dev,
  1392. "Switch your BIOS from RAID to AHCI mode to use them.\n");
  1393. /*
  1394. * Don't rely on the msi-x capability in the remap case,
  1395. * share the legacy interrupt across ahci and remapped devices.
  1396. */
  1397. hpriv->flags |= AHCI_HFLAG_NO_MSI;
  1398. }
  1399. static int ahci_get_irq_vector(struct ata_host *host, int port)
  1400. {
  1401. return pci_irq_vector(to_pci_dev(host->dev), port);
  1402. }
  1403. static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
  1404. struct ahci_host_priv *hpriv)
  1405. {
  1406. int nvec;
  1407. if (hpriv->flags & AHCI_HFLAG_NO_MSI)
  1408. return -ENODEV;
  1409. /*
  1410. * If number of MSIs is less than number of ports then Sharing Last
  1411. * Message mode could be enforced. In this case assume that advantage
  1412. * of multipe MSIs is negated and use single MSI mode instead.
  1413. */
  1414. if (n_ports > 1) {
  1415. nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX,
  1416. PCI_IRQ_MSIX | PCI_IRQ_MSI);
  1417. if (nvec > 0) {
  1418. if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) {
  1419. hpriv->get_irq_vector = ahci_get_irq_vector;
  1420. hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
  1421. return nvec;
  1422. }
  1423. /*
  1424. * Fallback to single MSI mode if the controller
  1425. * enforced MRSM mode.
  1426. */
  1427. printk(KERN_INFO
  1428. "ahci: MRSM is on, fallback to single MSI\n");
  1429. pci_free_irq_vectors(pdev);
  1430. }
  1431. }
  1432. /*
  1433. * If the host is not capable of supporting per-port vectors, fall
  1434. * back to single MSI before finally attempting single MSI-X.
  1435. */
  1436. nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
  1437. if (nvec == 1)
  1438. return nvec;
  1439. return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX);
  1440. }
  1441. static void ahci_update_initial_lpm_policy(struct ata_port *ap,
  1442. struct ahci_host_priv *hpriv)
  1443. {
  1444. int policy = CONFIG_SATA_MOBILE_LPM_POLICY;
  1445. /* Ignore processing for non mobile platforms */
  1446. if (!(hpriv->flags & AHCI_HFLAG_IS_MOBILE))
  1447. return;
  1448. /* user modified policy via module param */
  1449. if (mobile_lpm_policy != -1) {
  1450. policy = mobile_lpm_policy;
  1451. goto update_policy;
  1452. }
  1453. #ifdef CONFIG_ACPI
  1454. if (policy > ATA_LPM_MED_POWER &&
  1455. (acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0)) {
  1456. if (hpriv->cap & HOST_CAP_PART)
  1457. policy = ATA_LPM_MIN_POWER_WITH_PARTIAL;
  1458. else if (hpriv->cap & HOST_CAP_SSC)
  1459. policy = ATA_LPM_MIN_POWER;
  1460. }
  1461. #endif
  1462. update_policy:
  1463. if (policy >= ATA_LPM_UNKNOWN && policy <= ATA_LPM_MIN_POWER)
  1464. ap->target_lpm_policy = policy;
  1465. }
  1466. static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
  1467. {
  1468. const struct pci_device_id *id = pci_match_id(ahci_pci_tbl, pdev);
  1469. u16 tmp16;
  1470. /*
  1471. * Only apply the 6-port PCS quirk for known legacy platforms.
  1472. */
  1473. if (!id || id->vendor != PCI_VENDOR_ID_INTEL)
  1474. return;
  1475. /* Skip applying the quirk on Denverton and beyond */
  1476. if (((enum board_ids) id->driver_data) >= board_ahci_pcs7)
  1477. return;
  1478. /*
  1479. * port_map is determined from PORTS_IMPL PCI register which is
  1480. * implemented as write or write-once register. If the register
  1481. * isn't programmed, ahci automatically generates it from number
  1482. * of ports, which is good enough for PCS programming. It is
  1483. * otherwise expected that platform firmware enables the ports
  1484. * before the OS boots.
  1485. */
  1486. pci_read_config_word(pdev, PCS_6, &tmp16);
  1487. if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
  1488. tmp16 |= hpriv->port_map;
  1489. pci_write_config_word(pdev, PCS_6, tmp16);
  1490. }
  1491. }
  1492. static ssize_t remapped_nvme_show(struct device *dev,
  1493. struct device_attribute *attr,
  1494. char *buf)
  1495. {
  1496. struct ata_host *host = dev_get_drvdata(dev);
  1497. struct ahci_host_priv *hpriv = host->private_data;
  1498. return sprintf(buf, "%u\n", hpriv->remapped_nvme);
  1499. }
  1500. static DEVICE_ATTR_RO(remapped_nvme);
  1501. static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
  1502. {
  1503. unsigned int board_id = ent->driver_data;
  1504. struct ata_port_info pi = ahci_port_info[board_id];
  1505. const struct ata_port_info *ppi[] = { &pi, NULL };
  1506. struct device *dev = &pdev->dev;
  1507. struct ahci_host_priv *hpriv;
  1508. struct ata_host *host;
  1509. int n_ports, i, rc;
  1510. int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
  1511. VPRINTK("ENTER\n");
  1512. WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
  1513. ata_print_version_once(&pdev->dev, DRV_VERSION);
  1514. /* The AHCI driver can only drive the SATA ports, the PATA driver
  1515. can drive them all so if both drivers are selected make sure
  1516. AHCI stays out of the way */
  1517. if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
  1518. return -ENODEV;
  1519. /* Apple BIOS on MCP89 prevents us using AHCI */
  1520. if (is_mcp89_apple(pdev))
  1521. ahci_mcp89_apple_enable(pdev);
  1522. /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
  1523. * At the moment, we can only use the AHCI mode. Let the users know
  1524. * that for SAS drives they're out of luck.
  1525. */
  1526. if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
  1527. dev_info(&pdev->dev,
  1528. "PDC42819 can only drive SATA devices with this driver\n");
  1529. /* Some devices use non-standard BARs */
  1530. if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
  1531. ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
  1532. else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
  1533. ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
  1534. else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) {
  1535. if (pdev->device == 0xa01c)
  1536. ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
  1537. if (pdev->device == 0xa084)
  1538. ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5;
  1539. } else if (pdev->vendor == PCI_VENDOR_ID_LOONGSON) {
  1540. if (pdev->device == 0x7a08)
  1541. ahci_pci_bar = AHCI_PCI_BAR_LOONGSON;
  1542. }
  1543. /* acquire resources */
  1544. rc = pcim_enable_device(pdev);
  1545. if (rc)
  1546. return rc;
  1547. if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
  1548. (pdev->device == 0x2652 || pdev->device == 0x2653)) {
  1549. u8 map;
  1550. /* ICH6s share the same PCI ID for both piix and ahci
  1551. * modes. Enabling ahci mode while MAP indicates
  1552. * combined mode is a bad idea. Yield to ata_piix.
  1553. */
  1554. pci_read_config_byte(pdev, ICH_MAP, &map);
  1555. if (map & 0x3) {
  1556. dev_info(&pdev->dev,
  1557. "controller is in combined mode, can't enable AHCI mode\n");
  1558. return -ENODEV;
  1559. }
  1560. }
  1561. /* AHCI controllers often implement SFF compatible interface.
  1562. * Grab all PCI BARs just in case.
  1563. */
  1564. rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
  1565. if (rc == -EBUSY)
  1566. pcim_pin_device(pdev);
  1567. if (rc)
  1568. return rc;
  1569. hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
  1570. if (!hpriv)
  1571. return -ENOMEM;
  1572. hpriv->flags |= (unsigned long)pi.private_data;
  1573. /* MCP65 revision A1 and A2 can't do MSI */
  1574. if (board_id == board_ahci_mcp65 &&
  1575. (pdev->revision == 0xa1 || pdev->revision == 0xa2))
  1576. hpriv->flags |= AHCI_HFLAG_NO_MSI;
  1577. /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
  1578. if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
  1579. hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
  1580. /* only some SB600s can do 64bit DMA */
  1581. if (ahci_sb600_enable_64bit(pdev))
  1582. hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
  1583. hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
  1584. /* detect remapped nvme devices */
  1585. ahci_remap_check(pdev, ahci_pci_bar, hpriv);
  1586. sysfs_add_file_to_group(&pdev->dev.kobj,
  1587. &dev_attr_remapped_nvme.attr,
  1588. NULL);
  1589. /* must set flag prior to save config in order to take effect */
  1590. if (ahci_broken_devslp(pdev))
  1591. hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
  1592. #ifdef CONFIG_ARM64
  1593. if (pdev->vendor == PCI_VENDOR_ID_HUAWEI &&
  1594. pdev->device == 0xa235 &&
  1595. pdev->revision < 0x30)
  1596. hpriv->flags |= AHCI_HFLAG_NO_SXS;
  1597. if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
  1598. hpriv->irq_handler = ahci_thunderx_irq_handler;
  1599. #endif
  1600. /* save initial config */
  1601. ahci_pci_save_initial_config(pdev, hpriv);
  1602. /*
  1603. * If platform firmware failed to enable ports, try to enable
  1604. * them here.
  1605. */
  1606. ahci_intel_pcs_quirk(pdev, hpriv);
  1607. /* prepare host */
  1608. if (hpriv->cap & HOST_CAP_NCQ) {
  1609. pi.flags |= ATA_FLAG_NCQ;
  1610. /*
  1611. * Auto-activate optimization is supposed to be
  1612. * supported on all AHCI controllers indicating NCQ
  1613. * capability, but it seems to be broken on some
  1614. * chipsets including NVIDIAs.
  1615. */
  1616. if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
  1617. pi.flags |= ATA_FLAG_FPDMA_AA;
  1618. /*
  1619. * All AHCI controllers should be forward-compatible
  1620. * with the new auxiliary field. This code should be
  1621. * conditionalized if any buggy AHCI controllers are
  1622. * encountered.
  1623. */
  1624. pi.flags |= ATA_FLAG_FPDMA_AUX;
  1625. }
  1626. if (hpriv->cap & HOST_CAP_PMP)
  1627. pi.flags |= ATA_FLAG_PMP;
  1628. ahci_set_em_messages(hpriv, &pi);
  1629. if (ahci_broken_system_poweroff(pdev)) {
  1630. pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
  1631. dev_info(&pdev->dev,
  1632. "quirky BIOS, skipping spindown on poweroff\n");
  1633. }
  1634. if (ahci_broken_lpm(pdev)) {
  1635. pi.flags |= ATA_FLAG_NO_LPM;
  1636. dev_warn(&pdev->dev,
  1637. "BIOS update required for Link Power Management support\n");
  1638. }
  1639. if (ahci_broken_suspend(pdev)) {
  1640. hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
  1641. dev_warn(&pdev->dev,
  1642. "BIOS update required for suspend/resume\n");
  1643. }
  1644. if (ahci_broken_online(pdev)) {
  1645. hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
  1646. dev_info(&pdev->dev,
  1647. "online status unreliable, applying workaround\n");
  1648. }
  1649. /* Acer SA5-271 workaround modifies private_data */
  1650. acer_sa5_271_workaround(hpriv, pdev);
  1651. /* CAP.NP sometimes indicate the index of the last enabled
  1652. * port, at other times, that of the last possible port, so
  1653. * determining the maximum port number requires looking at
  1654. * both CAP.NP and port_map.
  1655. */
  1656. n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
  1657. host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
  1658. if (!host)
  1659. return -ENOMEM;
  1660. host->private_data = hpriv;
  1661. if (ahci_init_msi(pdev, n_ports, hpriv) < 0) {
  1662. /* legacy intx interrupts */
  1663. pci_intx(pdev, 1);
  1664. }
  1665. hpriv->irq = pci_irq_vector(pdev, 0);
  1666. if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
  1667. host->flags |= ATA_HOST_PARALLEL_SCAN;
  1668. else
  1669. dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
  1670. if (pi.flags & ATA_FLAG_EM)
  1671. ahci_reset_em(host);
  1672. for (i = 0; i < host->n_ports; i++) {
  1673. struct ata_port *ap = host->ports[i];
  1674. ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
  1675. ata_port_pbar_desc(ap, ahci_pci_bar,
  1676. 0x100 + ap->port_no * 0x80, "port");
  1677. /* set enclosure management message type */
  1678. if (ap->flags & ATA_FLAG_EM)
  1679. ap->em_message_type = hpriv->em_msg_type;
  1680. ahci_update_initial_lpm_policy(ap, hpriv);
  1681. /* disabled/not-implemented port */
  1682. if (!(hpriv->port_map & (1 << i)))
  1683. ap->ops = &ata_dummy_port_ops;
  1684. }
  1685. /* apply workaround for ASUS P5W DH Deluxe mainboard */
  1686. ahci_p5wdh_workaround(host);
  1687. /* apply gtf filter quirk */
  1688. ahci_gtf_filter_workaround(host);
  1689. /* initialize adapter */
  1690. rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
  1691. if (rc)
  1692. return rc;
  1693. rc = ahci_reset_controller(host);
  1694. if (rc)
  1695. return rc;
  1696. ahci_pci_init_controller(host);
  1697. ahci_pci_print_info(host);
  1698. pci_set_master(pdev);
  1699. rc = ahci_host_activate(host, &ahci_sht);
  1700. if (rc)
  1701. return rc;
  1702. pm_runtime_put_noidle(&pdev->dev);
  1703. return 0;
  1704. }
  1705. static void ahci_shutdown_one(struct pci_dev *pdev)
  1706. {
  1707. ata_pci_shutdown_one(pdev);
  1708. }
  1709. static void ahci_remove_one(struct pci_dev *pdev)
  1710. {
  1711. sysfs_remove_file_from_group(&pdev->dev.kobj,
  1712. &dev_attr_remapped_nvme.attr,
  1713. NULL);
  1714. pm_runtime_get_noresume(&pdev->dev);
  1715. ata_pci_remove_one(pdev);
  1716. }
  1717. module_pci_driver(ahci_pci_driver);
  1718. MODULE_AUTHOR("Jeff Garzik");
  1719. MODULE_DESCRIPTION("AHCI SATA low-level driver");
  1720. MODULE_LICENSE("GPL");
  1721. MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
  1722. MODULE_VERSION(DRV_VERSION);