pci_root.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * pci_root.c - ACPI PCI Root Bridge Driver ($Revision: 40 $)
  4. *
  5. * Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com>
  6. * Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
  7. */
  8. #include <linux/kernel.h>
  9. #include <linux/module.h>
  10. #include <linux/init.h>
  11. #include <linux/types.h>
  12. #include <linux/mutex.h>
  13. #include <linux/pm.h>
  14. #include <linux/pm_runtime.h>
  15. #include <linux/pci.h>
  16. #include <linux/pci-acpi.h>
  17. #include <linux/dmar.h>
  18. #include <linux/acpi.h>
  19. #include <linux/slab.h>
  20. #include <linux/dmi.h>
  21. #include <linux/platform_data/x86/apple.h>
  22. #include <acpi/apei.h> /* for acpi_hest_init() */
  23. #include "internal.h"
  24. #define ACPI_PCI_ROOT_CLASS "pci_bridge"
  25. #define ACPI_PCI_ROOT_DEVICE_NAME "PCI Root Bridge"
  26. static int acpi_pci_root_add(struct acpi_device *device,
  27. const struct acpi_device_id *not_used);
  28. static void acpi_pci_root_remove(struct acpi_device *device);
  29. static int acpi_pci_root_scan_dependent(struct acpi_device *adev)
  30. {
  31. acpiphp_check_host_bridge(adev);
  32. return 0;
  33. }
  34. #define ACPI_PCIE_REQ_SUPPORT (OSC_PCI_EXT_CONFIG_SUPPORT \
  35. | OSC_PCI_ASPM_SUPPORT \
  36. | OSC_PCI_CLOCK_PM_SUPPORT \
  37. | OSC_PCI_MSI_SUPPORT)
  38. static const struct acpi_device_id root_device_ids[] = {
  39. {"PNP0A03", 0},
  40. {"", 0},
  41. };
  42. static struct acpi_scan_handler pci_root_handler = {
  43. .ids = root_device_ids,
  44. .attach = acpi_pci_root_add,
  45. .detach = acpi_pci_root_remove,
  46. .hotplug = {
  47. .enabled = true,
  48. .scan_dependent = acpi_pci_root_scan_dependent,
  49. },
  50. };
  51. static DEFINE_MUTEX(osc_lock);
  52. /**
  53. * acpi_is_root_bridge - determine whether an ACPI CA node is a PCI root bridge
  54. * @handle: the ACPI CA node in question.
  55. *
  56. * Note: we could make this API take a struct acpi_device * instead, but
  57. * for now, it's more convenient to operate on an acpi_handle.
  58. */
  59. int acpi_is_root_bridge(acpi_handle handle)
  60. {
  61. int ret;
  62. struct acpi_device *device;
  63. ret = acpi_bus_get_device(handle, &device);
  64. if (ret)
  65. return 0;
  66. ret = acpi_match_device_ids(device, root_device_ids);
  67. if (ret)
  68. return 0;
  69. else
  70. return 1;
  71. }
  72. EXPORT_SYMBOL_GPL(acpi_is_root_bridge);
  73. static acpi_status
  74. get_root_bridge_busnr_callback(struct acpi_resource *resource, void *data)
  75. {
  76. struct resource *res = data;
  77. struct acpi_resource_address64 address;
  78. acpi_status status;
  79. status = acpi_resource_to_address64(resource, &address);
  80. if (ACPI_FAILURE(status))
  81. return AE_OK;
  82. if ((address.address.address_length > 0) &&
  83. (address.resource_type == ACPI_BUS_NUMBER_RANGE)) {
  84. res->start = address.address.minimum;
  85. res->end = address.address.minimum + address.address.address_length - 1;
  86. }
  87. return AE_OK;
  88. }
  89. static acpi_status try_get_root_bridge_busnr(acpi_handle handle,
  90. struct resource *res)
  91. {
  92. acpi_status status;
  93. res->start = -1;
  94. status =
  95. acpi_walk_resources(handle, METHOD_NAME__CRS,
  96. get_root_bridge_busnr_callback, res);
  97. if (ACPI_FAILURE(status))
  98. return status;
  99. if (res->start == -1)
  100. return AE_ERROR;
  101. return AE_OK;
  102. }
  103. struct pci_osc_bit_struct {
  104. u32 bit;
  105. char *desc;
  106. };
  107. static struct pci_osc_bit_struct pci_osc_support_bit[] = {
  108. { OSC_PCI_EXT_CONFIG_SUPPORT, "ExtendedConfig" },
  109. { OSC_PCI_ASPM_SUPPORT, "ASPM" },
  110. { OSC_PCI_CLOCK_PM_SUPPORT, "ClockPM" },
  111. { OSC_PCI_SEGMENT_GROUPS_SUPPORT, "Segments" },
  112. { OSC_PCI_MSI_SUPPORT, "MSI" },
  113. { OSC_PCI_EDR_SUPPORT, "EDR" },
  114. { OSC_PCI_HPX_TYPE_3_SUPPORT, "HPX-Type3" },
  115. };
  116. static struct pci_osc_bit_struct pci_osc_control_bit[] = {
  117. { OSC_PCI_EXPRESS_NATIVE_HP_CONTROL, "PCIeHotplug" },
  118. { OSC_PCI_SHPC_NATIVE_HP_CONTROL, "SHPCHotplug" },
  119. { OSC_PCI_EXPRESS_PME_CONTROL, "PME" },
  120. { OSC_PCI_EXPRESS_AER_CONTROL, "AER" },
  121. { OSC_PCI_EXPRESS_CAPABILITY_CONTROL, "PCIeCapability" },
  122. { OSC_PCI_EXPRESS_LTR_CONTROL, "LTR" },
  123. { OSC_PCI_EXPRESS_DPC_CONTROL, "DPC" },
  124. };
  125. static void decode_osc_bits(struct acpi_pci_root *root, char *msg, u32 word,
  126. struct pci_osc_bit_struct *table, int size)
  127. {
  128. char buf[80];
  129. int i, len = 0;
  130. struct pci_osc_bit_struct *entry;
  131. buf[0] = '\0';
  132. for (i = 0, entry = table; i < size; i++, entry++)
  133. if (word & entry->bit)
  134. len += scnprintf(buf + len, sizeof(buf) - len, "%s%s",
  135. len ? " " : "", entry->desc);
  136. dev_info(&root->device->dev, "_OSC: %s [%s]\n", msg, buf);
  137. }
  138. static void decode_osc_support(struct acpi_pci_root *root, char *msg, u32 word)
  139. {
  140. decode_osc_bits(root, msg, word, pci_osc_support_bit,
  141. ARRAY_SIZE(pci_osc_support_bit));
  142. }
  143. static void decode_osc_control(struct acpi_pci_root *root, char *msg, u32 word)
  144. {
  145. decode_osc_bits(root, msg, word, pci_osc_control_bit,
  146. ARRAY_SIZE(pci_osc_control_bit));
  147. }
  148. static u8 pci_osc_uuid_str[] = "33DB4D5B-1FF7-401C-9657-7441C03DD766";
  149. static acpi_status acpi_pci_run_osc(acpi_handle handle,
  150. const u32 *capbuf, u32 *retval)
  151. {
  152. struct acpi_osc_context context = {
  153. .uuid_str = pci_osc_uuid_str,
  154. .rev = 1,
  155. .cap.length = 12,
  156. .cap.pointer = (void *)capbuf,
  157. };
  158. acpi_status status;
  159. status = acpi_run_osc(handle, &context);
  160. if (ACPI_SUCCESS(status)) {
  161. *retval = *((u32 *)(context.ret.pointer + 8));
  162. kfree(context.ret.pointer);
  163. }
  164. return status;
  165. }
  166. static acpi_status acpi_pci_query_osc(struct acpi_pci_root *root,
  167. u32 support,
  168. u32 *control)
  169. {
  170. acpi_status status;
  171. u32 result, capbuf[3];
  172. support &= OSC_PCI_SUPPORT_MASKS;
  173. support |= root->osc_support_set;
  174. capbuf[OSC_QUERY_DWORD] = OSC_QUERY_ENABLE;
  175. capbuf[OSC_SUPPORT_DWORD] = support;
  176. if (control) {
  177. *control &= OSC_PCI_CONTROL_MASKS;
  178. capbuf[OSC_CONTROL_DWORD] = *control | root->osc_control_set;
  179. } else {
  180. /* Run _OSC query only with existing controls. */
  181. capbuf[OSC_CONTROL_DWORD] = root->osc_control_set;
  182. }
  183. status = acpi_pci_run_osc(root->device->handle, capbuf, &result);
  184. if (ACPI_SUCCESS(status)) {
  185. root->osc_support_set = support;
  186. if (control)
  187. *control = result;
  188. }
  189. return status;
  190. }
  191. static acpi_status acpi_pci_osc_support(struct acpi_pci_root *root, u32 flags)
  192. {
  193. acpi_status status;
  194. mutex_lock(&osc_lock);
  195. status = acpi_pci_query_osc(root, flags, NULL);
  196. mutex_unlock(&osc_lock);
  197. return status;
  198. }
  199. struct acpi_pci_root *acpi_pci_find_root(acpi_handle handle)
  200. {
  201. struct acpi_pci_root *root;
  202. struct acpi_device *device;
  203. if (acpi_bus_get_device(handle, &device) ||
  204. acpi_match_device_ids(device, root_device_ids))
  205. return NULL;
  206. root = acpi_driver_data(device);
  207. return root;
  208. }
  209. EXPORT_SYMBOL_GPL(acpi_pci_find_root);
  210. struct acpi_handle_node {
  211. struct list_head node;
  212. acpi_handle handle;
  213. };
  214. /**
  215. * acpi_get_pci_dev - convert ACPI CA handle to struct pci_dev
  216. * @handle: the handle in question
  217. *
  218. * Given an ACPI CA handle, the desired PCI device is located in the
  219. * list of PCI devices.
  220. *
  221. * If the device is found, its reference count is increased and this
  222. * function returns a pointer to its data structure. The caller must
  223. * decrement the reference count by calling pci_dev_put().
  224. * If no device is found, %NULL is returned.
  225. */
  226. struct pci_dev *acpi_get_pci_dev(acpi_handle handle)
  227. {
  228. int dev, fn;
  229. unsigned long long adr;
  230. acpi_status status;
  231. acpi_handle phandle;
  232. struct pci_bus *pbus;
  233. struct pci_dev *pdev = NULL;
  234. struct acpi_handle_node *node, *tmp;
  235. struct acpi_pci_root *root;
  236. LIST_HEAD(device_list);
  237. /*
  238. * Walk up the ACPI CA namespace until we reach a PCI root bridge.
  239. */
  240. phandle = handle;
  241. while (!acpi_is_root_bridge(phandle)) {
  242. node = kzalloc(sizeof(struct acpi_handle_node), GFP_KERNEL);
  243. if (!node)
  244. goto out;
  245. INIT_LIST_HEAD(&node->node);
  246. node->handle = phandle;
  247. list_add(&node->node, &device_list);
  248. status = acpi_get_parent(phandle, &phandle);
  249. if (ACPI_FAILURE(status))
  250. goto out;
  251. }
  252. root = acpi_pci_find_root(phandle);
  253. if (!root)
  254. goto out;
  255. pbus = root->bus;
  256. /*
  257. * Now, walk back down the PCI device tree until we return to our
  258. * original handle. Assumes that everything between the PCI root
  259. * bridge and the device we're looking for must be a P2P bridge.
  260. */
  261. list_for_each_entry(node, &device_list, node) {
  262. acpi_handle hnd = node->handle;
  263. status = acpi_evaluate_integer(hnd, "_ADR", NULL, &adr);
  264. if (ACPI_FAILURE(status))
  265. goto out;
  266. dev = (adr >> 16) & 0xffff;
  267. fn = adr & 0xffff;
  268. pdev = pci_get_slot(pbus, PCI_DEVFN(dev, fn));
  269. if (!pdev || hnd == handle)
  270. break;
  271. pbus = pdev->subordinate;
  272. pci_dev_put(pdev);
  273. /*
  274. * This function may be called for a non-PCI device that has a
  275. * PCI parent (eg. a disk under a PCI SATA controller). In that
  276. * case pdev->subordinate will be NULL for the parent.
  277. */
  278. if (!pbus) {
  279. dev_dbg(&pdev->dev, "Not a PCI-to-PCI bridge\n");
  280. pdev = NULL;
  281. break;
  282. }
  283. }
  284. out:
  285. list_for_each_entry_safe(node, tmp, &device_list, node)
  286. kfree(node);
  287. return pdev;
  288. }
  289. EXPORT_SYMBOL_GPL(acpi_get_pci_dev);
  290. /**
  291. * acpi_pci_osc_control_set - Request control of PCI root _OSC features.
  292. * @handle: ACPI handle of a PCI root bridge (or PCIe Root Complex).
  293. * @mask: Mask of _OSC bits to request control of, place to store control mask.
  294. * @req: Mask of _OSC bits the control of is essential to the caller.
  295. *
  296. * Run _OSC query for @mask and if that is successful, compare the returned
  297. * mask of control bits with @req. If all of the @req bits are set in the
  298. * returned mask, run _OSC request for it.
  299. *
  300. * The variable at the @mask address may be modified regardless of whether or
  301. * not the function returns success. On success it will contain the mask of
  302. * _OSC bits the BIOS has granted control of, but its contents are meaningless
  303. * on failure.
  304. **/
  305. acpi_status acpi_pci_osc_control_set(acpi_handle handle, u32 *mask, u32 req)
  306. {
  307. struct acpi_pci_root *root;
  308. acpi_status status = AE_OK;
  309. u32 ctrl, capbuf[3];
  310. if (!mask)
  311. return AE_BAD_PARAMETER;
  312. ctrl = *mask & OSC_PCI_CONTROL_MASKS;
  313. if ((ctrl & req) != req)
  314. return AE_TYPE;
  315. root = acpi_pci_find_root(handle);
  316. if (!root)
  317. return AE_NOT_EXIST;
  318. mutex_lock(&osc_lock);
  319. *mask = ctrl | root->osc_control_set;
  320. /* No need to evaluate _OSC if the control was already granted. */
  321. if ((root->osc_control_set & ctrl) == ctrl)
  322. goto out;
  323. /* Need to check the available controls bits before requesting them. */
  324. while (*mask) {
  325. status = acpi_pci_query_osc(root, root->osc_support_set, mask);
  326. if (ACPI_FAILURE(status))
  327. goto out;
  328. if (ctrl == *mask)
  329. break;
  330. decode_osc_control(root, "platform does not support",
  331. ctrl & ~(*mask));
  332. ctrl = *mask;
  333. }
  334. if ((ctrl & req) != req) {
  335. decode_osc_control(root, "not requesting control; platform does not support",
  336. req & ~(ctrl));
  337. status = AE_SUPPORT;
  338. goto out;
  339. }
  340. capbuf[OSC_QUERY_DWORD] = 0;
  341. capbuf[OSC_SUPPORT_DWORD] = root->osc_support_set;
  342. capbuf[OSC_CONTROL_DWORD] = ctrl;
  343. status = acpi_pci_run_osc(handle, capbuf, mask);
  344. if (ACPI_SUCCESS(status))
  345. root->osc_control_set = *mask;
  346. out:
  347. mutex_unlock(&osc_lock);
  348. return status;
  349. }
  350. EXPORT_SYMBOL(acpi_pci_osc_control_set);
  351. static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm,
  352. bool is_pcie)
  353. {
  354. u32 support, control, requested;
  355. acpi_status status;
  356. struct acpi_device *device = root->device;
  357. acpi_handle handle = device->handle;
  358. /*
  359. * Apple always return failure on _OSC calls when _OSI("Darwin") has
  360. * been called successfully. We know the feature set supported by the
  361. * platform, so avoid calling _OSC at all
  362. */
  363. if (x86_apple_machine) {
  364. root->osc_control_set = ~OSC_PCI_EXPRESS_PME_CONTROL;
  365. decode_osc_control(root, "OS assumes control of",
  366. root->osc_control_set);
  367. return;
  368. }
  369. /*
  370. * All supported architectures that use ACPI have support for
  371. * PCI domains, so we indicate this in _OSC support capabilities.
  372. */
  373. support = OSC_PCI_SEGMENT_GROUPS_SUPPORT;
  374. support |= OSC_PCI_HPX_TYPE_3_SUPPORT;
  375. if (pci_ext_cfg_avail())
  376. support |= OSC_PCI_EXT_CONFIG_SUPPORT;
  377. if (pcie_aspm_support_enabled())
  378. support |= OSC_PCI_ASPM_SUPPORT | OSC_PCI_CLOCK_PM_SUPPORT;
  379. if (pci_msi_enabled())
  380. support |= OSC_PCI_MSI_SUPPORT;
  381. if (IS_ENABLED(CONFIG_PCIE_EDR))
  382. support |= OSC_PCI_EDR_SUPPORT;
  383. decode_osc_support(root, "OS supports", support);
  384. status = acpi_pci_osc_support(root, support);
  385. if (ACPI_FAILURE(status)) {
  386. *no_aspm = 1;
  387. /* _OSC is optional for PCI host bridges */
  388. if ((status == AE_NOT_FOUND) && !is_pcie)
  389. return;
  390. dev_info(&device->dev, "_OSC failed (%s)%s\n",
  391. acpi_format_exception(status),
  392. pcie_aspm_support_enabled() ? "; disabling ASPM" : "");
  393. return;
  394. }
  395. if (pcie_ports_disabled) {
  396. dev_info(&device->dev, "PCIe port services disabled; not requesting _OSC control\n");
  397. return;
  398. }
  399. if ((support & ACPI_PCIE_REQ_SUPPORT) != ACPI_PCIE_REQ_SUPPORT) {
  400. decode_osc_support(root, "not requesting OS control; OS requires",
  401. ACPI_PCIE_REQ_SUPPORT);
  402. return;
  403. }
  404. control = OSC_PCI_EXPRESS_CAPABILITY_CONTROL
  405. | OSC_PCI_EXPRESS_PME_CONTROL;
  406. if (IS_ENABLED(CONFIG_PCIEASPM))
  407. control |= OSC_PCI_EXPRESS_LTR_CONTROL;
  408. if (IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE))
  409. control |= OSC_PCI_EXPRESS_NATIVE_HP_CONTROL;
  410. if (IS_ENABLED(CONFIG_HOTPLUG_PCI_SHPC))
  411. control |= OSC_PCI_SHPC_NATIVE_HP_CONTROL;
  412. if (pci_aer_available())
  413. control |= OSC_PCI_EXPRESS_AER_CONTROL;
  414. /*
  415. * Per the Downstream Port Containment Related Enhancements ECN to
  416. * the PCI Firmware Spec, r3.2, sec 4.5.1, table 4-5,
  417. * OSC_PCI_EXPRESS_DPC_CONTROL indicates the OS supports both DPC
  418. * and EDR.
  419. */
  420. if (IS_ENABLED(CONFIG_PCIE_DPC) && IS_ENABLED(CONFIG_PCIE_EDR))
  421. control |= OSC_PCI_EXPRESS_DPC_CONTROL;
  422. requested = control;
  423. status = acpi_pci_osc_control_set(handle, &control,
  424. OSC_PCI_EXPRESS_CAPABILITY_CONTROL);
  425. if (ACPI_SUCCESS(status)) {
  426. decode_osc_control(root, "OS now controls", control);
  427. if (acpi_gbl_FADT.boot_flags & ACPI_FADT_NO_ASPM) {
  428. /*
  429. * We have ASPM control, but the FADT indicates that
  430. * it's unsupported. Leave existing configuration
  431. * intact and prevent the OS from touching it.
  432. */
  433. dev_info(&device->dev, "FADT indicates ASPM is unsupported, using BIOS configuration\n");
  434. *no_aspm = 1;
  435. }
  436. } else {
  437. decode_osc_control(root, "OS requested", requested);
  438. decode_osc_control(root, "platform willing to grant", control);
  439. dev_info(&device->dev, "_OSC failed (%s); disabling ASPM\n",
  440. acpi_format_exception(status));
  441. /*
  442. * We want to disable ASPM here, but aspm_disabled
  443. * needs to remain in its state from boot so that we
  444. * properly handle PCIe 1.1 devices. So we set this
  445. * flag here, to defer the action until after the ACPI
  446. * root scan.
  447. */
  448. *no_aspm = 1;
  449. }
  450. }
  451. static int acpi_pci_root_add(struct acpi_device *device,
  452. const struct acpi_device_id *not_used)
  453. {
  454. unsigned long long segment, bus;
  455. acpi_status status;
  456. int result;
  457. struct acpi_pci_root *root;
  458. acpi_handle handle = device->handle;
  459. int no_aspm = 0;
  460. bool hotadd = system_state == SYSTEM_RUNNING;
  461. bool is_pcie;
  462. root = kzalloc(sizeof(struct acpi_pci_root), GFP_KERNEL);
  463. if (!root)
  464. return -ENOMEM;
  465. segment = 0;
  466. status = acpi_evaluate_integer(handle, METHOD_NAME__SEG, NULL,
  467. &segment);
  468. if (ACPI_FAILURE(status) && status != AE_NOT_FOUND) {
  469. dev_err(&device->dev, "can't evaluate _SEG\n");
  470. result = -ENODEV;
  471. goto end;
  472. }
  473. /* Check _CRS first, then _BBN. If no _BBN, default to zero. */
  474. root->secondary.flags = IORESOURCE_BUS;
  475. status = try_get_root_bridge_busnr(handle, &root->secondary);
  476. if (ACPI_FAILURE(status)) {
  477. /*
  478. * We need both the start and end of the downstream bus range
  479. * to interpret _CBA (MMCONFIG base address), so it really is
  480. * supposed to be in _CRS. If we don't find it there, all we
  481. * can do is assume [_BBN-0xFF] or [0-0xFF].
  482. */
  483. root->secondary.end = 0xFF;
  484. dev_warn(&device->dev,
  485. FW_BUG "no secondary bus range in _CRS\n");
  486. status = acpi_evaluate_integer(handle, METHOD_NAME__BBN,
  487. NULL, &bus);
  488. if (ACPI_SUCCESS(status))
  489. root->secondary.start = bus;
  490. else if (status == AE_NOT_FOUND)
  491. root->secondary.start = 0;
  492. else {
  493. dev_err(&device->dev, "can't evaluate _BBN\n");
  494. result = -ENODEV;
  495. goto end;
  496. }
  497. }
  498. root->device = device;
  499. root->segment = segment & 0xFFFF;
  500. strcpy(acpi_device_name(device), ACPI_PCI_ROOT_DEVICE_NAME);
  501. strcpy(acpi_device_class(device), ACPI_PCI_ROOT_CLASS);
  502. device->driver_data = root;
  503. if (hotadd && dmar_device_add(handle)) {
  504. result = -ENXIO;
  505. goto end;
  506. }
  507. pr_info(PREFIX "%s [%s] (domain %04x %pR)\n",
  508. acpi_device_name(device), acpi_device_bid(device),
  509. root->segment, &root->secondary);
  510. root->mcfg_addr = acpi_pci_root_get_mcfg_addr(handle);
  511. is_pcie = strcmp(acpi_device_hid(device), "PNP0A08") == 0;
  512. negotiate_os_control(root, &no_aspm, is_pcie);
  513. /*
  514. * TBD: Need PCI interface for enumeration/configuration of roots.
  515. */
  516. /*
  517. * Scan the Root Bridge
  518. * --------------------
  519. * Must do this prior to any attempt to bind the root device, as the
  520. * PCI namespace does not get created until this call is made (and
  521. * thus the root bridge's pci_dev does not exist).
  522. */
  523. root->bus = pci_acpi_scan_root(root);
  524. if (!root->bus) {
  525. dev_err(&device->dev,
  526. "Bus %04x:%02x not present in PCI namespace\n",
  527. root->segment, (unsigned int)root->secondary.start);
  528. device->driver_data = NULL;
  529. result = -ENODEV;
  530. goto remove_dmar;
  531. }
  532. if (no_aspm)
  533. pcie_no_aspm();
  534. pci_acpi_add_bus_pm_notifier(device);
  535. device_set_wakeup_capable(root->bus->bridge, device->wakeup.flags.valid);
  536. if (hotadd) {
  537. pcibios_resource_survey_bus(root->bus);
  538. pci_assign_unassigned_root_bus_resources(root->bus);
  539. /*
  540. * This is only called for the hotadd case. For the boot-time
  541. * case, we need to wait until after PCI initialization in
  542. * order to deal with IOAPICs mapped in on a PCI BAR.
  543. *
  544. * This is currently x86-specific, because acpi_ioapic_add()
  545. * is an empty function without CONFIG_ACPI_HOTPLUG_IOAPIC.
  546. * And CONFIG_ACPI_HOTPLUG_IOAPIC depends on CONFIG_X86_IO_APIC
  547. * (see drivers/acpi/Kconfig).
  548. */
  549. acpi_ioapic_add(root->device->handle);
  550. }
  551. pci_lock_rescan_remove();
  552. pci_bus_add_devices(root->bus);
  553. pci_unlock_rescan_remove();
  554. return 1;
  555. remove_dmar:
  556. if (hotadd)
  557. dmar_device_remove(handle);
  558. end:
  559. kfree(root);
  560. return result;
  561. }
  562. static void acpi_pci_root_remove(struct acpi_device *device)
  563. {
  564. struct acpi_pci_root *root = acpi_driver_data(device);
  565. pci_lock_rescan_remove();
  566. pci_stop_root_bus(root->bus);
  567. pci_ioapic_remove(root);
  568. device_set_wakeup_capable(root->bus->bridge, false);
  569. pci_acpi_remove_bus_pm_notifier(device);
  570. pci_remove_root_bus(root->bus);
  571. WARN_ON(acpi_ioapic_remove(root));
  572. dmar_device_remove(device->handle);
  573. pci_unlock_rescan_remove();
  574. kfree(root);
  575. }
  576. /*
  577. * Following code to support acpi_pci_root_create() is copied from
  578. * arch/x86/pci/acpi.c and modified so it could be reused by x86, IA64
  579. * and ARM64.
  580. */
  581. static void acpi_pci_root_validate_resources(struct device *dev,
  582. struct list_head *resources,
  583. unsigned long type)
  584. {
  585. LIST_HEAD(list);
  586. struct resource *res1, *res2, *root = NULL;
  587. struct resource_entry *tmp, *entry, *entry2;
  588. BUG_ON((type & (IORESOURCE_MEM | IORESOURCE_IO)) == 0);
  589. root = (type & IORESOURCE_MEM) ? &iomem_resource : &ioport_resource;
  590. list_splice_init(resources, &list);
  591. resource_list_for_each_entry_safe(entry, tmp, &list) {
  592. bool free = false;
  593. resource_size_t end;
  594. res1 = entry->res;
  595. if (!(res1->flags & type))
  596. goto next;
  597. /* Exclude non-addressable range or non-addressable portion */
  598. end = min(res1->end, root->end);
  599. if (end <= res1->start) {
  600. dev_info(dev, "host bridge window %pR (ignored, not CPU addressable)\n",
  601. res1);
  602. free = true;
  603. goto next;
  604. } else if (res1->end != end) {
  605. dev_info(dev, "host bridge window %pR ([%#llx-%#llx] ignored, not CPU addressable)\n",
  606. res1, (unsigned long long)end + 1,
  607. (unsigned long long)res1->end);
  608. res1->end = end;
  609. }
  610. resource_list_for_each_entry(entry2, resources) {
  611. res2 = entry2->res;
  612. if (!(res2->flags & type))
  613. continue;
  614. /*
  615. * I don't like throwing away windows because then
  616. * our resources no longer match the ACPI _CRS, but
  617. * the kernel resource tree doesn't allow overlaps.
  618. */
  619. if (resource_overlaps(res1, res2)) {
  620. res2->start = min(res1->start, res2->start);
  621. res2->end = max(res1->end, res2->end);
  622. dev_info(dev, "host bridge window expanded to %pR; %pR ignored\n",
  623. res2, res1);
  624. free = true;
  625. goto next;
  626. }
  627. }
  628. next:
  629. resource_list_del(entry);
  630. if (free)
  631. resource_list_free_entry(entry);
  632. else
  633. resource_list_add_tail(entry, resources);
  634. }
  635. }
  636. static void acpi_pci_root_remap_iospace(struct fwnode_handle *fwnode,
  637. struct resource_entry *entry)
  638. {
  639. #ifdef PCI_IOBASE
  640. struct resource *res = entry->res;
  641. resource_size_t cpu_addr = res->start;
  642. resource_size_t pci_addr = cpu_addr - entry->offset;
  643. resource_size_t length = resource_size(res);
  644. unsigned long port;
  645. if (pci_register_io_range(fwnode, cpu_addr, length))
  646. goto err;
  647. port = pci_address_to_pio(cpu_addr);
  648. if (port == (unsigned long)-1)
  649. goto err;
  650. res->start = port;
  651. res->end = port + length - 1;
  652. entry->offset = port - pci_addr;
  653. if (pci_remap_iospace(res, cpu_addr) < 0)
  654. goto err;
  655. pr_info("Remapped I/O %pa to %pR\n", &cpu_addr, res);
  656. return;
  657. err:
  658. res->flags |= IORESOURCE_DISABLED;
  659. #endif
  660. }
  661. int acpi_pci_probe_root_resources(struct acpi_pci_root_info *info)
  662. {
  663. int ret;
  664. struct list_head *list = &info->resources;
  665. struct acpi_device *device = info->bridge;
  666. struct resource_entry *entry, *tmp;
  667. unsigned long flags;
  668. flags = IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT;
  669. ret = acpi_dev_get_resources(device, list,
  670. acpi_dev_filter_resource_type_cb,
  671. (void *)flags);
  672. if (ret < 0)
  673. dev_warn(&device->dev,
  674. "failed to parse _CRS method, error code %d\n", ret);
  675. else if (ret == 0)
  676. dev_dbg(&device->dev,
  677. "no IO and memory resources present in _CRS\n");
  678. else {
  679. resource_list_for_each_entry_safe(entry, tmp, list) {
  680. if (entry->res->flags & IORESOURCE_IO)
  681. acpi_pci_root_remap_iospace(&device->fwnode,
  682. entry);
  683. if (entry->res->flags & IORESOURCE_DISABLED)
  684. resource_list_destroy_entry(entry);
  685. else
  686. entry->res->name = info->name;
  687. }
  688. acpi_pci_root_validate_resources(&device->dev, list,
  689. IORESOURCE_MEM);
  690. acpi_pci_root_validate_resources(&device->dev, list,
  691. IORESOURCE_IO);
  692. }
  693. return ret;
  694. }
  695. static void pci_acpi_root_add_resources(struct acpi_pci_root_info *info)
  696. {
  697. struct resource_entry *entry, *tmp;
  698. struct resource *res, *conflict, *root = NULL;
  699. resource_list_for_each_entry_safe(entry, tmp, &info->resources) {
  700. res = entry->res;
  701. if (res->flags & IORESOURCE_MEM)
  702. root = &iomem_resource;
  703. else if (res->flags & IORESOURCE_IO)
  704. root = &ioport_resource;
  705. else
  706. continue;
  707. /*
  708. * Some legacy x86 host bridge drivers use iomem_resource and
  709. * ioport_resource as default resource pool, skip it.
  710. */
  711. if (res == root)
  712. continue;
  713. conflict = insert_resource_conflict(root, res);
  714. if (conflict) {
  715. dev_info(&info->bridge->dev,
  716. "ignoring host bridge window %pR (conflicts with %s %pR)\n",
  717. res, conflict->name, conflict);
  718. resource_list_destroy_entry(entry);
  719. }
  720. }
  721. }
  722. static void __acpi_pci_root_release_info(struct acpi_pci_root_info *info)
  723. {
  724. struct resource *res;
  725. struct resource_entry *entry, *tmp;
  726. if (!info)
  727. return;
  728. resource_list_for_each_entry_safe(entry, tmp, &info->resources) {
  729. res = entry->res;
  730. if (res->parent &&
  731. (res->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
  732. release_resource(res);
  733. resource_list_destroy_entry(entry);
  734. }
  735. info->ops->release_info(info);
  736. }
  737. static void acpi_pci_root_release_info(struct pci_host_bridge *bridge)
  738. {
  739. struct resource *res;
  740. struct resource_entry *entry;
  741. resource_list_for_each_entry(entry, &bridge->windows) {
  742. res = entry->res;
  743. if (res->flags & IORESOURCE_IO)
  744. pci_unmap_iospace(res);
  745. if (res->parent &&
  746. (res->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
  747. release_resource(res);
  748. }
  749. __acpi_pci_root_release_info(bridge->release_data);
  750. }
  751. struct pci_bus *acpi_pci_root_create(struct acpi_pci_root *root,
  752. struct acpi_pci_root_ops *ops,
  753. struct acpi_pci_root_info *info,
  754. void *sysdata)
  755. {
  756. int ret, busnum = root->secondary.start;
  757. struct acpi_device *device = root->device;
  758. int node = acpi_get_node(device->handle);
  759. struct pci_bus *bus;
  760. struct pci_host_bridge *host_bridge;
  761. union acpi_object *obj;
  762. info->root = root;
  763. info->bridge = device;
  764. info->ops = ops;
  765. INIT_LIST_HEAD(&info->resources);
  766. snprintf(info->name, sizeof(info->name), "PCI Bus %04x:%02x",
  767. root->segment, busnum);
  768. if (ops->init_info && ops->init_info(info))
  769. goto out_release_info;
  770. if (ops->prepare_resources)
  771. ret = ops->prepare_resources(info);
  772. else
  773. ret = acpi_pci_probe_root_resources(info);
  774. if (ret < 0)
  775. goto out_release_info;
  776. pci_acpi_root_add_resources(info);
  777. pci_add_resource(&info->resources, &root->secondary);
  778. bus = pci_create_root_bus(NULL, busnum, ops->pci_ops,
  779. sysdata, &info->resources);
  780. if (!bus)
  781. goto out_release_info;
  782. host_bridge = to_pci_host_bridge(bus->bridge);
  783. if (!(root->osc_control_set & OSC_PCI_EXPRESS_NATIVE_HP_CONTROL))
  784. host_bridge->native_pcie_hotplug = 0;
  785. if (!(root->osc_control_set & OSC_PCI_SHPC_NATIVE_HP_CONTROL))
  786. host_bridge->native_shpc_hotplug = 0;
  787. if (!(root->osc_control_set & OSC_PCI_EXPRESS_AER_CONTROL))
  788. host_bridge->native_aer = 0;
  789. if (!(root->osc_control_set & OSC_PCI_EXPRESS_PME_CONTROL))
  790. host_bridge->native_pme = 0;
  791. if (!(root->osc_control_set & OSC_PCI_EXPRESS_LTR_CONTROL))
  792. host_bridge->native_ltr = 0;
  793. if (!(root->osc_control_set & OSC_PCI_EXPRESS_DPC_CONTROL))
  794. host_bridge->native_dpc = 0;
  795. /*
  796. * Evaluate the "PCI Boot Configuration" _DSM Function. If it
  797. * exists and returns 0, we must preserve any PCI resource
  798. * assignments made by firmware for this host bridge.
  799. */
  800. obj = acpi_evaluate_dsm(ACPI_HANDLE(bus->bridge), &pci_acpi_dsm_guid, 1,
  801. DSM_PCI_PRESERVE_BOOT_CONFIG, NULL);
  802. if (obj && obj->type == ACPI_TYPE_INTEGER && obj->integer.value == 0)
  803. host_bridge->preserve_config = 1;
  804. ACPI_FREE(obj);
  805. pci_scan_child_bus(bus);
  806. pci_set_host_bridge_release(host_bridge, acpi_pci_root_release_info,
  807. info);
  808. if (node != NUMA_NO_NODE)
  809. dev_printk(KERN_DEBUG, &bus->dev, "on NUMA node %d\n", node);
  810. return bus;
  811. out_release_info:
  812. __acpi_pci_root_release_info(info);
  813. return NULL;
  814. }
  815. void __init acpi_pci_root_init(void)
  816. {
  817. acpi_hest_init();
  818. if (acpi_pci_disabled)
  819. return;
  820. pci_acpi_crs_quirks();
  821. acpi_scan_add_handler_with_hotplug(&pci_root_handler, "pci_root");
  822. }