cppc_acpi.c 41 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * CPPC (Collaborative Processor Performance Control) methods used by CPUfreq drivers.
  4. *
  5. * (C) Copyright 2014, 2015 Linaro Ltd.
  6. * Author: Ashwin Chaugule <ashwin.chaugule@linaro.org>
  7. *
  8. * CPPC describes a few methods for controlling CPU performance using
  9. * information from a per CPU table called CPC. This table is described in
  10. * the ACPI v5.0+ specification. The table consists of a list of
  11. * registers which may be memory mapped or hardware registers and also may
  12. * include some static integer values.
  13. *
  14. * CPU performance is on an abstract continuous scale as against a discretized
  15. * P-state scale which is tied to CPU frequency only. In brief, the basic
  16. * operation involves:
  17. *
  18. * - OS makes a CPU performance request. (Can provide min and max bounds)
  19. *
  20. * - Platform (such as BMC) is free to optimize request within requested bounds
  21. * depending on power/thermal budgets etc.
  22. *
  23. * - Platform conveys its decision back to OS
  24. *
  25. * The communication between OS and platform occurs through another medium
  26. * called (PCC) Platform Communication Channel. This is a generic mailbox like
  27. * mechanism which includes doorbell semantics to indicate register updates.
  28. * See drivers/mailbox/pcc.c for details on PCC.
  29. *
  30. * Finer details about the PCC and CPPC spec are available in the ACPI v5.1 and
  31. * above specifications.
  32. */
  33. #define pr_fmt(fmt) "ACPI CPPC: " fmt
  34. #include <linux/cpufreq.h>
  35. #include <linux/delay.h>
  36. #include <linux/iopoll.h>
  37. #include <linux/ktime.h>
  38. #include <linux/rwsem.h>
  39. #include <linux/wait.h>
  40. #include <acpi/cppc_acpi.h>
  41. struct cppc_pcc_data {
  42. struct mbox_chan *pcc_channel;
  43. void __iomem *pcc_comm_addr;
  44. bool pcc_channel_acquired;
  45. unsigned int deadline_us;
  46. unsigned int pcc_mpar, pcc_mrtt, pcc_nominal;
  47. bool pending_pcc_write_cmd; /* Any pending/batched PCC write cmds? */
  48. bool platform_owns_pcc; /* Ownership of PCC subspace */
  49. unsigned int pcc_write_cnt; /* Running count of PCC write commands */
  50. /*
  51. * Lock to provide controlled access to the PCC channel.
  52. *
  53. * For performance critical usecases(currently cppc_set_perf)
  54. * We need to take read_lock and check if channel belongs to OSPM
  55. * before reading or writing to PCC subspace
  56. * We need to take write_lock before transferring the channel
  57. * ownership to the platform via a Doorbell
  58. * This allows us to batch a number of CPPC requests if they happen
  59. * to originate in about the same time
  60. *
  61. * For non-performance critical usecases(init)
  62. * Take write_lock for all purposes which gives exclusive access
  63. */
  64. struct rw_semaphore pcc_lock;
  65. /* Wait queue for CPUs whose requests were batched */
  66. wait_queue_head_t pcc_write_wait_q;
  67. ktime_t last_cmd_cmpl_time;
  68. ktime_t last_mpar_reset;
  69. int mpar_count;
  70. int refcount;
  71. };
  72. /* Array to represent the PCC channel per subspace ID */
  73. static struct cppc_pcc_data *pcc_data[MAX_PCC_SUBSPACES];
  74. /* The cpu_pcc_subspace_idx contains per CPU subspace ID */
  75. static DEFINE_PER_CPU(int, cpu_pcc_subspace_idx);
  76. /*
  77. * The cpc_desc structure contains the ACPI register details
  78. * as described in the per CPU _CPC tables. The details
  79. * include the type of register (e.g. PCC, System IO, FFH etc.)
  80. * and destination addresses which lets us READ/WRITE CPU performance
  81. * information using the appropriate I/O methods.
  82. */
  83. static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr);
  84. /* pcc mapped address + header size + offset within PCC subspace */
  85. #define GET_PCC_VADDR(offs, pcc_ss_id) (pcc_data[pcc_ss_id]->pcc_comm_addr + \
  86. 0x8 + (offs))
  87. /* Check if a CPC register is in PCC */
  88. #define CPC_IN_PCC(cpc) ((cpc)->type == ACPI_TYPE_BUFFER && \
  89. (cpc)->cpc_entry.reg.space_id == \
  90. ACPI_ADR_SPACE_PLATFORM_COMM)
  91. /* Evalutes to True if reg is a NULL register descriptor */
  92. #define IS_NULL_REG(reg) ((reg)->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY && \
  93. (reg)->address == 0 && \
  94. (reg)->bit_width == 0 && \
  95. (reg)->bit_offset == 0 && \
  96. (reg)->access_width == 0)
  97. /* Evalutes to True if an optional cpc field is supported */
  98. #define CPC_SUPPORTED(cpc) ((cpc)->type == ACPI_TYPE_INTEGER ? \
  99. !!(cpc)->cpc_entry.int_value : \
  100. !IS_NULL_REG(&(cpc)->cpc_entry.reg))
  101. /*
  102. * Arbitrary Retries in case the remote processor is slow to respond
  103. * to PCC commands. Keeping it high enough to cover emulators where
  104. * the processors run painfully slow.
  105. */
  106. #define NUM_RETRIES 500ULL
  107. #define define_one_cppc_ro(_name) \
  108. static struct kobj_attribute _name = \
  109. __ATTR(_name, 0444, show_##_name, NULL)
  110. #define to_cpc_desc(a) container_of(a, struct cpc_desc, kobj)
  111. #define show_cppc_data(access_fn, struct_name, member_name) \
  112. static ssize_t show_##member_name(struct kobject *kobj, \
  113. struct kobj_attribute *attr, char *buf) \
  114. { \
  115. struct cpc_desc *cpc_ptr = to_cpc_desc(kobj); \
  116. struct struct_name st_name = {0}; \
  117. int ret; \
  118. \
  119. ret = access_fn(cpc_ptr->cpu_id, &st_name); \
  120. if (ret) \
  121. return ret; \
  122. \
  123. return scnprintf(buf, PAGE_SIZE, "%llu\n", \
  124. (u64)st_name.member_name); \
  125. } \
  126. define_one_cppc_ro(member_name)
  127. show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, highest_perf);
  128. show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_perf);
  129. show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_perf);
  130. show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_nonlinear_perf);
  131. show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_freq);
  132. show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_freq);
  133. show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, reference_perf);
  134. show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, wraparound_time);
  135. static ssize_t show_feedback_ctrs(struct kobject *kobj,
  136. struct kobj_attribute *attr, char *buf)
  137. {
  138. struct cpc_desc *cpc_ptr = to_cpc_desc(kobj);
  139. struct cppc_perf_fb_ctrs fb_ctrs = {0};
  140. int ret;
  141. ret = cppc_get_perf_ctrs(cpc_ptr->cpu_id, &fb_ctrs);
  142. if (ret)
  143. return ret;
  144. return scnprintf(buf, PAGE_SIZE, "ref:%llu del:%llu\n",
  145. fb_ctrs.reference, fb_ctrs.delivered);
  146. }
  147. define_one_cppc_ro(feedback_ctrs);
  148. static struct attribute *cppc_attrs[] = {
  149. &feedback_ctrs.attr,
  150. &reference_perf.attr,
  151. &wraparound_time.attr,
  152. &highest_perf.attr,
  153. &lowest_perf.attr,
  154. &lowest_nonlinear_perf.attr,
  155. &nominal_perf.attr,
  156. &nominal_freq.attr,
  157. &lowest_freq.attr,
  158. NULL
  159. };
  160. static struct kobj_type cppc_ktype = {
  161. .sysfs_ops = &kobj_sysfs_ops,
  162. .default_attrs = cppc_attrs,
  163. };
  164. static int check_pcc_chan(int pcc_ss_id, bool chk_err_bit)
  165. {
  166. int ret, status;
  167. struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id];
  168. struct acpi_pcct_shared_memory __iomem *generic_comm_base =
  169. pcc_ss_data->pcc_comm_addr;
  170. if (!pcc_ss_data->platform_owns_pcc)
  171. return 0;
  172. /*
  173. * Poll PCC status register every 3us(delay_us) for maximum of
  174. * deadline_us(timeout_us) until PCC command complete bit is set(cond)
  175. */
  176. ret = readw_relaxed_poll_timeout(&generic_comm_base->status, status,
  177. status & PCC_CMD_COMPLETE_MASK, 3,
  178. pcc_ss_data->deadline_us);
  179. if (likely(!ret)) {
  180. pcc_ss_data->platform_owns_pcc = false;
  181. if (chk_err_bit && (status & PCC_ERROR_MASK))
  182. ret = -EIO;
  183. }
  184. if (unlikely(ret))
  185. pr_err("PCC check channel failed for ss: %d. ret=%d\n",
  186. pcc_ss_id, ret);
  187. return ret;
  188. }
  189. /*
  190. * This function transfers the ownership of the PCC to the platform
  191. * So it must be called while holding write_lock(pcc_lock)
  192. */
  193. static int send_pcc_cmd(int pcc_ss_id, u16 cmd)
  194. {
  195. int ret = -EIO, i;
  196. struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id];
  197. struct acpi_pcct_shared_memory *generic_comm_base =
  198. (struct acpi_pcct_shared_memory *)pcc_ss_data->pcc_comm_addr;
  199. unsigned int time_delta;
  200. /*
  201. * For CMD_WRITE we know for a fact the caller should have checked
  202. * the channel before writing to PCC space
  203. */
  204. if (cmd == CMD_READ) {
  205. /*
  206. * If there are pending cpc_writes, then we stole the channel
  207. * before write completion, so first send a WRITE command to
  208. * platform
  209. */
  210. if (pcc_ss_data->pending_pcc_write_cmd)
  211. send_pcc_cmd(pcc_ss_id, CMD_WRITE);
  212. ret = check_pcc_chan(pcc_ss_id, false);
  213. if (ret)
  214. goto end;
  215. } else /* CMD_WRITE */
  216. pcc_ss_data->pending_pcc_write_cmd = FALSE;
  217. /*
  218. * Handle the Minimum Request Turnaround Time(MRTT)
  219. * "The minimum amount of time that OSPM must wait after the completion
  220. * of a command before issuing the next command, in microseconds"
  221. */
  222. if (pcc_ss_data->pcc_mrtt) {
  223. time_delta = ktime_us_delta(ktime_get(),
  224. pcc_ss_data->last_cmd_cmpl_time);
  225. if (pcc_ss_data->pcc_mrtt > time_delta)
  226. udelay(pcc_ss_data->pcc_mrtt - time_delta);
  227. }
  228. /*
  229. * Handle the non-zero Maximum Periodic Access Rate(MPAR)
  230. * "The maximum number of periodic requests that the subspace channel can
  231. * support, reported in commands per minute. 0 indicates no limitation."
  232. *
  233. * This parameter should be ideally zero or large enough so that it can
  234. * handle maximum number of requests that all the cores in the system can
  235. * collectively generate. If it is not, we will follow the spec and just
  236. * not send the request to the platform after hitting the MPAR limit in
  237. * any 60s window
  238. */
  239. if (pcc_ss_data->pcc_mpar) {
  240. if (pcc_ss_data->mpar_count == 0) {
  241. time_delta = ktime_ms_delta(ktime_get(),
  242. pcc_ss_data->last_mpar_reset);
  243. if ((time_delta < 60 * MSEC_PER_SEC) && pcc_ss_data->last_mpar_reset) {
  244. pr_debug("PCC cmd for subspace %d not sent due to MPAR limit",
  245. pcc_ss_id);
  246. ret = -EIO;
  247. goto end;
  248. }
  249. pcc_ss_data->last_mpar_reset = ktime_get();
  250. pcc_ss_data->mpar_count = pcc_ss_data->pcc_mpar;
  251. }
  252. pcc_ss_data->mpar_count--;
  253. }
  254. /* Write to the shared comm region. */
  255. writew_relaxed(cmd, &generic_comm_base->command);
  256. /* Flip CMD COMPLETE bit */
  257. writew_relaxed(0, &generic_comm_base->status);
  258. pcc_ss_data->platform_owns_pcc = true;
  259. /* Ring doorbell */
  260. ret = mbox_send_message(pcc_ss_data->pcc_channel, &cmd);
  261. if (ret < 0) {
  262. pr_err("Err sending PCC mbox message. ss: %d cmd:%d, ret:%d\n",
  263. pcc_ss_id, cmd, ret);
  264. goto end;
  265. }
  266. /* wait for completion and check for PCC errro bit */
  267. ret = check_pcc_chan(pcc_ss_id, true);
  268. if (pcc_ss_data->pcc_mrtt)
  269. pcc_ss_data->last_cmd_cmpl_time = ktime_get();
  270. if (pcc_ss_data->pcc_channel->mbox->txdone_irq)
  271. mbox_chan_txdone(pcc_ss_data->pcc_channel, ret);
  272. else
  273. mbox_client_txdone(pcc_ss_data->pcc_channel, ret);
  274. end:
  275. if (cmd == CMD_WRITE) {
  276. if (unlikely(ret)) {
  277. for_each_possible_cpu(i) {
  278. struct cpc_desc *desc = per_cpu(cpc_desc_ptr, i);
  279. if (!desc)
  280. continue;
  281. if (desc->write_cmd_id == pcc_ss_data->pcc_write_cnt)
  282. desc->write_cmd_status = ret;
  283. }
  284. }
  285. pcc_ss_data->pcc_write_cnt++;
  286. wake_up_all(&pcc_ss_data->pcc_write_wait_q);
  287. }
  288. return ret;
  289. }
  290. static void cppc_chan_tx_done(struct mbox_client *cl, void *msg, int ret)
  291. {
  292. if (ret < 0)
  293. pr_debug("TX did not complete: CMD sent:%x, ret:%d\n",
  294. *(u16 *)msg, ret);
  295. else
  296. pr_debug("TX completed. CMD sent:%x, ret:%d\n",
  297. *(u16 *)msg, ret);
  298. }
  299. static struct mbox_client cppc_mbox_cl = {
  300. .tx_done = cppc_chan_tx_done,
  301. .knows_txdone = true,
  302. };
  303. static int acpi_get_psd(struct cpc_desc *cpc_ptr, acpi_handle handle)
  304. {
  305. int result = -EFAULT;
  306. acpi_status status = AE_OK;
  307. struct acpi_buffer buffer = {ACPI_ALLOCATE_BUFFER, NULL};
  308. struct acpi_buffer format = {sizeof("NNNNN"), "NNNNN"};
  309. struct acpi_buffer state = {0, NULL};
  310. union acpi_object *psd = NULL;
  311. struct acpi_psd_package *pdomain;
  312. status = acpi_evaluate_object_typed(handle, "_PSD", NULL,
  313. &buffer, ACPI_TYPE_PACKAGE);
  314. if (status == AE_NOT_FOUND) /* _PSD is optional */
  315. return 0;
  316. if (ACPI_FAILURE(status))
  317. return -ENODEV;
  318. psd = buffer.pointer;
  319. if (!psd || psd->package.count != 1) {
  320. pr_debug("Invalid _PSD data\n");
  321. goto end;
  322. }
  323. pdomain = &(cpc_ptr->domain_info);
  324. state.length = sizeof(struct acpi_psd_package);
  325. state.pointer = pdomain;
  326. status = acpi_extract_package(&(psd->package.elements[0]),
  327. &format, &state);
  328. if (ACPI_FAILURE(status)) {
  329. pr_debug("Invalid _PSD data for CPU:%d\n", cpc_ptr->cpu_id);
  330. goto end;
  331. }
  332. if (pdomain->num_entries != ACPI_PSD_REV0_ENTRIES) {
  333. pr_debug("Unknown _PSD:num_entries for CPU:%d\n", cpc_ptr->cpu_id);
  334. goto end;
  335. }
  336. if (pdomain->revision != ACPI_PSD_REV0_REVISION) {
  337. pr_debug("Unknown _PSD:revision for CPU: %d\n", cpc_ptr->cpu_id);
  338. goto end;
  339. }
  340. if (pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ALL &&
  341. pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ANY &&
  342. pdomain->coord_type != DOMAIN_COORD_TYPE_HW_ALL) {
  343. pr_debug("Invalid _PSD:coord_type for CPU:%d\n", cpc_ptr->cpu_id);
  344. goto end;
  345. }
  346. result = 0;
  347. end:
  348. kfree(buffer.pointer);
  349. return result;
  350. }
  351. /**
  352. * acpi_get_psd_map - Map the CPUs in a common freq domain.
  353. * @all_cpu_data: Ptrs to CPU specific CPPC data including PSD info.
  354. *
  355. * Return: 0 for success or negative value for err.
  356. */
  357. int acpi_get_psd_map(struct cppc_cpudata **all_cpu_data)
  358. {
  359. int count_target;
  360. int retval = 0;
  361. unsigned int i, j;
  362. cpumask_var_t covered_cpus;
  363. struct cppc_cpudata *pr, *match_pr;
  364. struct acpi_psd_package *pdomain;
  365. struct acpi_psd_package *match_pdomain;
  366. struct cpc_desc *cpc_ptr, *match_cpc_ptr;
  367. if (!zalloc_cpumask_var(&covered_cpus, GFP_KERNEL))
  368. return -ENOMEM;
  369. /*
  370. * Now that we have _PSD data from all CPUs, let's setup P-state
  371. * domain info.
  372. */
  373. for_each_possible_cpu(i) {
  374. if (cpumask_test_cpu(i, covered_cpus))
  375. continue;
  376. pr = all_cpu_data[i];
  377. cpc_ptr = per_cpu(cpc_desc_ptr, i);
  378. if (!cpc_ptr) {
  379. retval = -EFAULT;
  380. goto err_ret;
  381. }
  382. pdomain = &(cpc_ptr->domain_info);
  383. cpumask_set_cpu(i, pr->shared_cpu_map);
  384. cpumask_set_cpu(i, covered_cpus);
  385. if (pdomain->num_processors <= 1)
  386. continue;
  387. /* Validate the Domain info */
  388. count_target = pdomain->num_processors;
  389. if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ALL)
  390. pr->shared_type = CPUFREQ_SHARED_TYPE_ALL;
  391. else if (pdomain->coord_type == DOMAIN_COORD_TYPE_HW_ALL)
  392. pr->shared_type = CPUFREQ_SHARED_TYPE_HW;
  393. else if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ANY)
  394. pr->shared_type = CPUFREQ_SHARED_TYPE_ANY;
  395. for_each_possible_cpu(j) {
  396. if (i == j)
  397. continue;
  398. match_cpc_ptr = per_cpu(cpc_desc_ptr, j);
  399. if (!match_cpc_ptr) {
  400. retval = -EFAULT;
  401. goto err_ret;
  402. }
  403. match_pdomain = &(match_cpc_ptr->domain_info);
  404. if (match_pdomain->domain != pdomain->domain)
  405. continue;
  406. /* Here i and j are in the same domain */
  407. if (match_pdomain->num_processors != count_target) {
  408. retval = -EFAULT;
  409. goto err_ret;
  410. }
  411. if (pdomain->coord_type != match_pdomain->coord_type) {
  412. retval = -EFAULT;
  413. goto err_ret;
  414. }
  415. cpumask_set_cpu(j, covered_cpus);
  416. cpumask_set_cpu(j, pr->shared_cpu_map);
  417. }
  418. for_each_cpu(j, pr->shared_cpu_map) {
  419. if (i == j)
  420. continue;
  421. match_pr = all_cpu_data[j];
  422. match_pr->shared_type = pr->shared_type;
  423. cpumask_copy(match_pr->shared_cpu_map,
  424. pr->shared_cpu_map);
  425. }
  426. }
  427. goto out;
  428. err_ret:
  429. for_each_possible_cpu(i) {
  430. pr = all_cpu_data[i];
  431. /* Assume no coordination on any error parsing domain info */
  432. cpumask_clear(pr->shared_cpu_map);
  433. cpumask_set_cpu(i, pr->shared_cpu_map);
  434. pr->shared_type = CPUFREQ_SHARED_TYPE_ALL;
  435. }
  436. out:
  437. free_cpumask_var(covered_cpus);
  438. return retval;
  439. }
  440. EXPORT_SYMBOL_GPL(acpi_get_psd_map);
  441. static int register_pcc_channel(int pcc_ss_idx)
  442. {
  443. struct acpi_pcct_hw_reduced *cppc_ss;
  444. u64 usecs_lat;
  445. if (pcc_ss_idx >= 0) {
  446. pcc_data[pcc_ss_idx]->pcc_channel =
  447. pcc_mbox_request_channel(&cppc_mbox_cl, pcc_ss_idx);
  448. if (IS_ERR(pcc_data[pcc_ss_idx]->pcc_channel)) {
  449. pr_err("Failed to find PCC channel for subspace %d\n",
  450. pcc_ss_idx);
  451. return -ENODEV;
  452. }
  453. /*
  454. * The PCC mailbox controller driver should
  455. * have parsed the PCCT (global table of all
  456. * PCC channels) and stored pointers to the
  457. * subspace communication region in con_priv.
  458. */
  459. cppc_ss = (pcc_data[pcc_ss_idx]->pcc_channel)->con_priv;
  460. if (!cppc_ss) {
  461. pr_err("No PCC subspace found for %d CPPC\n",
  462. pcc_ss_idx);
  463. return -ENODEV;
  464. }
  465. /*
  466. * cppc_ss->latency is just a Nominal value. In reality
  467. * the remote processor could be much slower to reply.
  468. * So add an arbitrary amount of wait on top of Nominal.
  469. */
  470. usecs_lat = NUM_RETRIES * cppc_ss->latency;
  471. pcc_data[pcc_ss_idx]->deadline_us = usecs_lat;
  472. pcc_data[pcc_ss_idx]->pcc_mrtt = cppc_ss->min_turnaround_time;
  473. pcc_data[pcc_ss_idx]->pcc_mpar = cppc_ss->max_access_rate;
  474. pcc_data[pcc_ss_idx]->pcc_nominal = cppc_ss->latency;
  475. pcc_data[pcc_ss_idx]->pcc_comm_addr =
  476. acpi_os_ioremap(cppc_ss->base_address, cppc_ss->length);
  477. if (!pcc_data[pcc_ss_idx]->pcc_comm_addr) {
  478. pr_err("Failed to ioremap PCC comm region mem for %d\n",
  479. pcc_ss_idx);
  480. return -ENOMEM;
  481. }
  482. /* Set flag so that we don't come here for each CPU. */
  483. pcc_data[pcc_ss_idx]->pcc_channel_acquired = true;
  484. }
  485. return 0;
  486. }
  487. /**
  488. * cpc_ffh_supported() - check if FFH reading supported
  489. *
  490. * Check if the architecture has support for functional fixed hardware
  491. * read/write capability.
  492. *
  493. * Return: true for supported, false for not supported
  494. */
  495. bool __weak cpc_ffh_supported(void)
  496. {
  497. return false;
  498. }
  499. /**
  500. * pcc_data_alloc() - Allocate the pcc_data memory for pcc subspace
  501. *
  502. * Check and allocate the cppc_pcc_data memory.
  503. * In some processor configurations it is possible that same subspace
  504. * is shared between multiple CPUs. This is seen especially in CPUs
  505. * with hardware multi-threading support.
  506. *
  507. * Return: 0 for success, errno for failure
  508. */
  509. static int pcc_data_alloc(int pcc_ss_id)
  510. {
  511. if (pcc_ss_id < 0 || pcc_ss_id >= MAX_PCC_SUBSPACES)
  512. return -EINVAL;
  513. if (pcc_data[pcc_ss_id]) {
  514. pcc_data[pcc_ss_id]->refcount++;
  515. } else {
  516. pcc_data[pcc_ss_id] = kzalloc(sizeof(struct cppc_pcc_data),
  517. GFP_KERNEL);
  518. if (!pcc_data[pcc_ss_id])
  519. return -ENOMEM;
  520. pcc_data[pcc_ss_id]->refcount++;
  521. }
  522. return 0;
  523. }
  524. /* Check if CPPC revision + num_ent combination is supported */
  525. static bool is_cppc_supported(int revision, int num_ent)
  526. {
  527. int expected_num_ent;
  528. switch (revision) {
  529. case CPPC_V2_REV:
  530. expected_num_ent = CPPC_V2_NUM_ENT;
  531. break;
  532. case CPPC_V3_REV:
  533. expected_num_ent = CPPC_V3_NUM_ENT;
  534. break;
  535. default:
  536. pr_debug("Firmware exports unsupported CPPC revision: %d\n",
  537. revision);
  538. return false;
  539. }
  540. if (expected_num_ent != num_ent) {
  541. pr_debug("Firmware exports %d entries. Expected: %d for CPPC rev:%d\n",
  542. num_ent, expected_num_ent, revision);
  543. return false;
  544. }
  545. return true;
  546. }
  547. /*
  548. * An example CPC table looks like the following.
  549. *
  550. * Name(_CPC, Package()
  551. * {
  552. * 17,
  553. * NumEntries
  554. * 1,
  555. * // Revision
  556. * ResourceTemplate(){Register(PCC, 32, 0, 0x120, 2)},
  557. * // Highest Performance
  558. * ResourceTemplate(){Register(PCC, 32, 0, 0x124, 2)},
  559. * // Nominal Performance
  560. * ResourceTemplate(){Register(PCC, 32, 0, 0x128, 2)},
  561. * // Lowest Nonlinear Performance
  562. * ResourceTemplate(){Register(PCC, 32, 0, 0x12C, 2)},
  563. * // Lowest Performance
  564. * ResourceTemplate(){Register(PCC, 32, 0, 0x130, 2)},
  565. * // Guaranteed Performance Register
  566. * ResourceTemplate(){Register(PCC, 32, 0, 0x110, 2)},
  567. * // Desired Performance Register
  568. * ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)},
  569. * ..
  570. * ..
  571. * ..
  572. *
  573. * }
  574. * Each Register() encodes how to access that specific register.
  575. * e.g. a sample PCC entry has the following encoding:
  576. *
  577. * Register (
  578. * PCC,
  579. * AddressSpaceKeyword
  580. * 8,
  581. * //RegisterBitWidth
  582. * 8,
  583. * //RegisterBitOffset
  584. * 0x30,
  585. * //RegisterAddress
  586. * 9
  587. * //AccessSize (subspace ID)
  588. * 0
  589. * )
  590. * }
  591. */
  592. /**
  593. * acpi_cppc_processor_probe - Search for per CPU _CPC objects.
  594. * @pr: Ptr to acpi_processor containing this CPU's logical ID.
  595. *
  596. * Return: 0 for success or negative value for err.
  597. */
  598. int acpi_cppc_processor_probe(struct acpi_processor *pr)
  599. {
  600. struct acpi_buffer output = {ACPI_ALLOCATE_BUFFER, NULL};
  601. union acpi_object *out_obj, *cpc_obj;
  602. struct cpc_desc *cpc_ptr;
  603. struct cpc_reg *gas_t;
  604. struct device *cpu_dev;
  605. acpi_handle handle = pr->handle;
  606. unsigned int num_ent, i, cpc_rev;
  607. int pcc_subspace_id = -1;
  608. acpi_status status;
  609. int ret = -EFAULT;
  610. /* Parse the ACPI _CPC table for this CPU. */
  611. status = acpi_evaluate_object_typed(handle, "_CPC", NULL, &output,
  612. ACPI_TYPE_PACKAGE);
  613. if (ACPI_FAILURE(status)) {
  614. ret = -ENODEV;
  615. goto out_buf_free;
  616. }
  617. out_obj = (union acpi_object *) output.pointer;
  618. cpc_ptr = kzalloc(sizeof(struct cpc_desc), GFP_KERNEL);
  619. if (!cpc_ptr) {
  620. ret = -ENOMEM;
  621. goto out_buf_free;
  622. }
  623. /* First entry is NumEntries. */
  624. cpc_obj = &out_obj->package.elements[0];
  625. if (cpc_obj->type == ACPI_TYPE_INTEGER) {
  626. num_ent = cpc_obj->integer.value;
  627. if (num_ent <= 1) {
  628. pr_debug("Unexpected _CPC NumEntries value (%d) for CPU:%d\n",
  629. num_ent, pr->id);
  630. goto out_free;
  631. }
  632. } else {
  633. pr_debug("Unexpected entry type(%d) for NumEntries\n",
  634. cpc_obj->type);
  635. goto out_free;
  636. }
  637. cpc_ptr->num_entries = num_ent;
  638. /* Second entry should be revision. */
  639. cpc_obj = &out_obj->package.elements[1];
  640. if (cpc_obj->type == ACPI_TYPE_INTEGER) {
  641. cpc_rev = cpc_obj->integer.value;
  642. } else {
  643. pr_debug("Unexpected entry type(%d) for Revision\n",
  644. cpc_obj->type);
  645. goto out_free;
  646. }
  647. cpc_ptr->version = cpc_rev;
  648. if (!is_cppc_supported(cpc_rev, num_ent))
  649. goto out_free;
  650. /* Iterate through remaining entries in _CPC */
  651. for (i = 2; i < num_ent; i++) {
  652. cpc_obj = &out_obj->package.elements[i];
  653. if (cpc_obj->type == ACPI_TYPE_INTEGER) {
  654. cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_INTEGER;
  655. cpc_ptr->cpc_regs[i-2].cpc_entry.int_value = cpc_obj->integer.value;
  656. } else if (cpc_obj->type == ACPI_TYPE_BUFFER) {
  657. gas_t = (struct cpc_reg *)
  658. cpc_obj->buffer.pointer;
  659. /*
  660. * The PCC Subspace index is encoded inside
  661. * the CPC table entries. The same PCC index
  662. * will be used for all the PCC entries,
  663. * so extract it only once.
  664. */
  665. if (gas_t->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
  666. if (pcc_subspace_id < 0) {
  667. pcc_subspace_id = gas_t->access_width;
  668. if (pcc_data_alloc(pcc_subspace_id))
  669. goto out_free;
  670. } else if (pcc_subspace_id != gas_t->access_width) {
  671. pr_debug("Mismatched PCC ids.\n");
  672. goto out_free;
  673. }
  674. } else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
  675. if (gas_t->address) {
  676. void __iomem *addr;
  677. addr = ioremap(gas_t->address, gas_t->bit_width/8);
  678. if (!addr)
  679. goto out_free;
  680. cpc_ptr->cpc_regs[i-2].sys_mem_vaddr = addr;
  681. }
  682. } else {
  683. if (gas_t->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE || !cpc_ffh_supported()) {
  684. /* Support only PCC ,SYS MEM and FFH type regs */
  685. pr_debug("Unsupported register type: %d\n", gas_t->space_id);
  686. goto out_free;
  687. }
  688. }
  689. cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_BUFFER;
  690. memcpy(&cpc_ptr->cpc_regs[i-2].cpc_entry.reg, gas_t, sizeof(*gas_t));
  691. } else {
  692. pr_debug("Err in entry:%d in CPC table of CPU:%d \n", i, pr->id);
  693. goto out_free;
  694. }
  695. }
  696. per_cpu(cpu_pcc_subspace_idx, pr->id) = pcc_subspace_id;
  697. /*
  698. * Initialize the remaining cpc_regs as unsupported.
  699. * Example: In case FW exposes CPPC v2, the below loop will initialize
  700. * LOWEST_FREQ and NOMINAL_FREQ regs as unsupported
  701. */
  702. for (i = num_ent - 2; i < MAX_CPC_REG_ENT; i++) {
  703. cpc_ptr->cpc_regs[i].type = ACPI_TYPE_INTEGER;
  704. cpc_ptr->cpc_regs[i].cpc_entry.int_value = 0;
  705. }
  706. /* Store CPU Logical ID */
  707. cpc_ptr->cpu_id = pr->id;
  708. /* Parse PSD data for this CPU */
  709. ret = acpi_get_psd(cpc_ptr, handle);
  710. if (ret)
  711. goto out_free;
  712. /* Register PCC channel once for all PCC subspace ID. */
  713. if (pcc_subspace_id >= 0 && !pcc_data[pcc_subspace_id]->pcc_channel_acquired) {
  714. ret = register_pcc_channel(pcc_subspace_id);
  715. if (ret)
  716. goto out_free;
  717. init_rwsem(&pcc_data[pcc_subspace_id]->pcc_lock);
  718. init_waitqueue_head(&pcc_data[pcc_subspace_id]->pcc_write_wait_q);
  719. }
  720. /* Everything looks okay */
  721. pr_debug("Parsed CPC struct for CPU: %d\n", pr->id);
  722. /* Add per logical CPU nodes for reading its feedback counters. */
  723. cpu_dev = get_cpu_device(pr->id);
  724. if (!cpu_dev) {
  725. ret = -EINVAL;
  726. goto out_free;
  727. }
  728. /* Plug PSD data into this CPU's CPC descriptor. */
  729. per_cpu(cpc_desc_ptr, pr->id) = cpc_ptr;
  730. ret = kobject_init_and_add(&cpc_ptr->kobj, &cppc_ktype, &cpu_dev->kobj,
  731. "acpi_cppc");
  732. if (ret) {
  733. per_cpu(cpc_desc_ptr, pr->id) = NULL;
  734. kobject_put(&cpc_ptr->kobj);
  735. goto out_free;
  736. }
  737. kfree(output.pointer);
  738. return 0;
  739. out_free:
  740. /* Free all the mapped sys mem areas for this CPU */
  741. for (i = 2; i < cpc_ptr->num_entries; i++) {
  742. void __iomem *addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr;
  743. if (addr)
  744. iounmap(addr);
  745. }
  746. kfree(cpc_ptr);
  747. out_buf_free:
  748. kfree(output.pointer);
  749. return ret;
  750. }
  751. EXPORT_SYMBOL_GPL(acpi_cppc_processor_probe);
  752. /**
  753. * acpi_cppc_processor_exit - Cleanup CPC structs.
  754. * @pr: Ptr to acpi_processor containing this CPU's logical ID.
  755. *
  756. * Return: Void
  757. */
  758. void acpi_cppc_processor_exit(struct acpi_processor *pr)
  759. {
  760. struct cpc_desc *cpc_ptr;
  761. unsigned int i;
  762. void __iomem *addr;
  763. int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, pr->id);
  764. if (pcc_ss_id >=0 && pcc_data[pcc_ss_id]) {
  765. if (pcc_data[pcc_ss_id]->pcc_channel_acquired) {
  766. pcc_data[pcc_ss_id]->refcount--;
  767. if (!pcc_data[pcc_ss_id]->refcount) {
  768. pcc_mbox_free_channel(pcc_data[pcc_ss_id]->pcc_channel);
  769. kfree(pcc_data[pcc_ss_id]);
  770. pcc_data[pcc_ss_id] = NULL;
  771. }
  772. }
  773. }
  774. cpc_ptr = per_cpu(cpc_desc_ptr, pr->id);
  775. if (!cpc_ptr)
  776. return;
  777. /* Free all the mapped sys mem areas for this CPU */
  778. for (i = 2; i < cpc_ptr->num_entries; i++) {
  779. addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr;
  780. if (addr)
  781. iounmap(addr);
  782. }
  783. kobject_put(&cpc_ptr->kobj);
  784. kfree(cpc_ptr);
  785. }
  786. EXPORT_SYMBOL_GPL(acpi_cppc_processor_exit);
  787. /**
  788. * cpc_read_ffh() - Read FFH register
  789. * @cpunum: CPU number to read
  790. * @reg: cppc register information
  791. * @val: place holder for return value
  792. *
  793. * Read bit_width bits from a specified address and bit_offset
  794. *
  795. * Return: 0 for success and error code
  796. */
  797. int __weak cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val)
  798. {
  799. return -ENOTSUPP;
  800. }
  801. /**
  802. * cpc_write_ffh() - Write FFH register
  803. * @cpunum: CPU number to write
  804. * @reg: cppc register information
  805. * @val: value to write
  806. *
  807. * Write value of bit_width bits to a specified address and bit_offset
  808. *
  809. * Return: 0 for success and error code
  810. */
  811. int __weak cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val)
  812. {
  813. return -ENOTSUPP;
  814. }
  815. /*
  816. * Since cpc_read and cpc_write are called while holding pcc_lock, it should be
  817. * as fast as possible. We have already mapped the PCC subspace during init, so
  818. * we can directly write to it.
  819. */
  820. static int cpc_read(int cpu, struct cpc_register_resource *reg_res, u64 *val)
  821. {
  822. int ret_val = 0;
  823. void __iomem *vaddr = 0;
  824. int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
  825. struct cpc_reg *reg = &reg_res->cpc_entry.reg;
  826. if (reg_res->type == ACPI_TYPE_INTEGER) {
  827. *val = reg_res->cpc_entry.int_value;
  828. return ret_val;
  829. }
  830. *val = 0;
  831. if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0)
  832. vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id);
  833. else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
  834. vaddr = reg_res->sys_mem_vaddr;
  835. else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE)
  836. return cpc_read_ffh(cpu, reg, val);
  837. else
  838. return acpi_os_read_memory((acpi_physical_address)reg->address,
  839. val, reg->bit_width);
  840. switch (reg->bit_width) {
  841. case 8:
  842. *val = readb_relaxed(vaddr);
  843. break;
  844. case 16:
  845. *val = readw_relaxed(vaddr);
  846. break;
  847. case 32:
  848. *val = readl_relaxed(vaddr);
  849. break;
  850. case 64:
  851. *val = readq_relaxed(vaddr);
  852. break;
  853. default:
  854. pr_debug("Error: Cannot read %u bit width from PCC for ss: %d\n",
  855. reg->bit_width, pcc_ss_id);
  856. ret_val = -EFAULT;
  857. }
  858. return ret_val;
  859. }
  860. static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val)
  861. {
  862. int ret_val = 0;
  863. void __iomem *vaddr = 0;
  864. int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
  865. struct cpc_reg *reg = &reg_res->cpc_entry.reg;
  866. if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0)
  867. vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id);
  868. else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
  869. vaddr = reg_res->sys_mem_vaddr;
  870. else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE)
  871. return cpc_write_ffh(cpu, reg, val);
  872. else
  873. return acpi_os_write_memory((acpi_physical_address)reg->address,
  874. val, reg->bit_width);
  875. switch (reg->bit_width) {
  876. case 8:
  877. writeb_relaxed(val, vaddr);
  878. break;
  879. case 16:
  880. writew_relaxed(val, vaddr);
  881. break;
  882. case 32:
  883. writel_relaxed(val, vaddr);
  884. break;
  885. case 64:
  886. writeq_relaxed(val, vaddr);
  887. break;
  888. default:
  889. pr_debug("Error: Cannot write %u bit width to PCC for ss: %d\n",
  890. reg->bit_width, pcc_ss_id);
  891. ret_val = -EFAULT;
  892. break;
  893. }
  894. return ret_val;
  895. }
  896. /**
  897. * cppc_get_desired_perf - Get the value of desired performance register.
  898. * @cpunum: CPU from which to get desired performance.
  899. * @desired_perf: address of a variable to store the returned desired performance
  900. *
  901. * Return: 0 for success, -EIO otherwise.
  902. */
  903. int cppc_get_desired_perf(int cpunum, u64 *desired_perf)
  904. {
  905. struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
  906. int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
  907. struct cpc_register_resource *desired_reg;
  908. struct cppc_pcc_data *pcc_ss_data = NULL;
  909. desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF];
  910. if (CPC_IN_PCC(desired_reg)) {
  911. int ret = 0;
  912. if (pcc_ss_id < 0)
  913. return -EIO;
  914. pcc_ss_data = pcc_data[pcc_ss_id];
  915. down_write(&pcc_ss_data->pcc_lock);
  916. if (send_pcc_cmd(pcc_ss_id, CMD_READ) >= 0)
  917. cpc_read(cpunum, desired_reg, desired_perf);
  918. else
  919. ret = -EIO;
  920. up_write(&pcc_ss_data->pcc_lock);
  921. return ret;
  922. }
  923. cpc_read(cpunum, desired_reg, desired_perf);
  924. return 0;
  925. }
  926. EXPORT_SYMBOL_GPL(cppc_get_desired_perf);
  927. /**
  928. * cppc_get_perf_caps - Get a CPU's performance capabilities.
  929. * @cpunum: CPU from which to get capabilities info.
  930. * @perf_caps: ptr to cppc_perf_caps. See cppc_acpi.h
  931. *
  932. * Return: 0 for success with perf_caps populated else -ERRNO.
  933. */
  934. int cppc_get_perf_caps(int cpunum, struct cppc_perf_caps *perf_caps)
  935. {
  936. struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
  937. struct cpc_register_resource *highest_reg, *lowest_reg,
  938. *lowest_non_linear_reg, *nominal_reg, *guaranteed_reg,
  939. *low_freq_reg = NULL, *nom_freq_reg = NULL;
  940. u64 high, low, guaranteed, nom, min_nonlinear, low_f = 0, nom_f = 0;
  941. int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
  942. struct cppc_pcc_data *pcc_ss_data = NULL;
  943. int ret = 0, regs_in_pcc = 0;
  944. if (!cpc_desc) {
  945. pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
  946. return -ENODEV;
  947. }
  948. highest_reg = &cpc_desc->cpc_regs[HIGHEST_PERF];
  949. lowest_reg = &cpc_desc->cpc_regs[LOWEST_PERF];
  950. lowest_non_linear_reg = &cpc_desc->cpc_regs[LOW_NON_LINEAR_PERF];
  951. nominal_reg = &cpc_desc->cpc_regs[NOMINAL_PERF];
  952. low_freq_reg = &cpc_desc->cpc_regs[LOWEST_FREQ];
  953. nom_freq_reg = &cpc_desc->cpc_regs[NOMINAL_FREQ];
  954. guaranteed_reg = &cpc_desc->cpc_regs[GUARANTEED_PERF];
  955. /* Are any of the regs PCC ?*/
  956. if (CPC_IN_PCC(highest_reg) || CPC_IN_PCC(lowest_reg) ||
  957. CPC_IN_PCC(lowest_non_linear_reg) || CPC_IN_PCC(nominal_reg) ||
  958. CPC_IN_PCC(low_freq_reg) || CPC_IN_PCC(nom_freq_reg)) {
  959. if (pcc_ss_id < 0) {
  960. pr_debug("Invalid pcc_ss_id\n");
  961. return -ENODEV;
  962. }
  963. pcc_ss_data = pcc_data[pcc_ss_id];
  964. regs_in_pcc = 1;
  965. down_write(&pcc_ss_data->pcc_lock);
  966. /* Ring doorbell once to update PCC subspace */
  967. if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) {
  968. ret = -EIO;
  969. goto out_err;
  970. }
  971. }
  972. cpc_read(cpunum, highest_reg, &high);
  973. perf_caps->highest_perf = high;
  974. cpc_read(cpunum, lowest_reg, &low);
  975. perf_caps->lowest_perf = low;
  976. cpc_read(cpunum, nominal_reg, &nom);
  977. perf_caps->nominal_perf = nom;
  978. if (guaranteed_reg->type != ACPI_TYPE_BUFFER ||
  979. IS_NULL_REG(&guaranteed_reg->cpc_entry.reg)) {
  980. perf_caps->guaranteed_perf = 0;
  981. } else {
  982. cpc_read(cpunum, guaranteed_reg, &guaranteed);
  983. perf_caps->guaranteed_perf = guaranteed;
  984. }
  985. cpc_read(cpunum, lowest_non_linear_reg, &min_nonlinear);
  986. perf_caps->lowest_nonlinear_perf = min_nonlinear;
  987. if (!high || !low || !nom || !min_nonlinear)
  988. ret = -EFAULT;
  989. /* Read optional lowest and nominal frequencies if present */
  990. if (CPC_SUPPORTED(low_freq_reg))
  991. cpc_read(cpunum, low_freq_reg, &low_f);
  992. if (CPC_SUPPORTED(nom_freq_reg))
  993. cpc_read(cpunum, nom_freq_reg, &nom_f);
  994. perf_caps->lowest_freq = low_f;
  995. perf_caps->nominal_freq = nom_f;
  996. out_err:
  997. if (regs_in_pcc)
  998. up_write(&pcc_ss_data->pcc_lock);
  999. return ret;
  1000. }
  1001. EXPORT_SYMBOL_GPL(cppc_get_perf_caps);
  1002. /**
  1003. * cppc_get_perf_ctrs - Read a CPU's performance feedback counters.
  1004. * @cpunum: CPU from which to read counters.
  1005. * @perf_fb_ctrs: ptr to cppc_perf_fb_ctrs. See cppc_acpi.h
  1006. *
  1007. * Return: 0 for success with perf_fb_ctrs populated else -ERRNO.
  1008. */
  1009. int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs)
  1010. {
  1011. struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
  1012. struct cpc_register_resource *delivered_reg, *reference_reg,
  1013. *ref_perf_reg, *ctr_wrap_reg;
  1014. int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
  1015. struct cppc_pcc_data *pcc_ss_data = NULL;
  1016. u64 delivered, reference, ref_perf, ctr_wrap_time;
  1017. int ret = 0, regs_in_pcc = 0;
  1018. if (!cpc_desc) {
  1019. pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
  1020. return -ENODEV;
  1021. }
  1022. delivered_reg = &cpc_desc->cpc_regs[DELIVERED_CTR];
  1023. reference_reg = &cpc_desc->cpc_regs[REFERENCE_CTR];
  1024. ref_perf_reg = &cpc_desc->cpc_regs[REFERENCE_PERF];
  1025. ctr_wrap_reg = &cpc_desc->cpc_regs[CTR_WRAP_TIME];
  1026. /*
  1027. * If reference perf register is not supported then we should
  1028. * use the nominal perf value
  1029. */
  1030. if (!CPC_SUPPORTED(ref_perf_reg))
  1031. ref_perf_reg = &cpc_desc->cpc_regs[NOMINAL_PERF];
  1032. /* Are any of the regs PCC ?*/
  1033. if (CPC_IN_PCC(delivered_reg) || CPC_IN_PCC(reference_reg) ||
  1034. CPC_IN_PCC(ctr_wrap_reg) || CPC_IN_PCC(ref_perf_reg)) {
  1035. if (pcc_ss_id < 0) {
  1036. pr_debug("Invalid pcc_ss_id\n");
  1037. return -ENODEV;
  1038. }
  1039. pcc_ss_data = pcc_data[pcc_ss_id];
  1040. down_write(&pcc_ss_data->pcc_lock);
  1041. regs_in_pcc = 1;
  1042. /* Ring doorbell once to update PCC subspace */
  1043. if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) {
  1044. ret = -EIO;
  1045. goto out_err;
  1046. }
  1047. }
  1048. cpc_read(cpunum, delivered_reg, &delivered);
  1049. cpc_read(cpunum, reference_reg, &reference);
  1050. cpc_read(cpunum, ref_perf_reg, &ref_perf);
  1051. /*
  1052. * Per spec, if ctr_wrap_time optional register is unsupported, then the
  1053. * performance counters are assumed to never wrap during the lifetime of
  1054. * platform
  1055. */
  1056. ctr_wrap_time = (u64)(~((u64)0));
  1057. if (CPC_SUPPORTED(ctr_wrap_reg))
  1058. cpc_read(cpunum, ctr_wrap_reg, &ctr_wrap_time);
  1059. if (!delivered || !reference || !ref_perf) {
  1060. ret = -EFAULT;
  1061. goto out_err;
  1062. }
  1063. perf_fb_ctrs->delivered = delivered;
  1064. perf_fb_ctrs->reference = reference;
  1065. perf_fb_ctrs->reference_perf = ref_perf;
  1066. perf_fb_ctrs->wraparound_time = ctr_wrap_time;
  1067. out_err:
  1068. if (regs_in_pcc)
  1069. up_write(&pcc_ss_data->pcc_lock);
  1070. return ret;
  1071. }
  1072. EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs);
  1073. /**
  1074. * cppc_set_perf - Set a CPU's performance controls.
  1075. * @cpu: CPU for which to set performance controls.
  1076. * @perf_ctrls: ptr to cppc_perf_ctrls. See cppc_acpi.h
  1077. *
  1078. * Return: 0 for success, -ERRNO otherwise.
  1079. */
  1080. int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
  1081. {
  1082. struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
  1083. struct cpc_register_resource *desired_reg;
  1084. int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
  1085. struct cppc_pcc_data *pcc_ss_data = NULL;
  1086. int ret = 0;
  1087. if (!cpc_desc) {
  1088. pr_debug("No CPC descriptor for CPU:%d\n", cpu);
  1089. return -ENODEV;
  1090. }
  1091. desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF];
  1092. /*
  1093. * This is Phase-I where we want to write to CPC registers
  1094. * -> We want all CPUs to be able to execute this phase in parallel
  1095. *
  1096. * Since read_lock can be acquired by multiple CPUs simultaneously we
  1097. * achieve that goal here
  1098. */
  1099. if (CPC_IN_PCC(desired_reg)) {
  1100. if (pcc_ss_id < 0) {
  1101. pr_debug("Invalid pcc_ss_id\n");
  1102. return -ENODEV;
  1103. }
  1104. pcc_ss_data = pcc_data[pcc_ss_id];
  1105. down_read(&pcc_ss_data->pcc_lock); /* BEGIN Phase-I */
  1106. if (pcc_ss_data->platform_owns_pcc) {
  1107. ret = check_pcc_chan(pcc_ss_id, false);
  1108. if (ret) {
  1109. up_read(&pcc_ss_data->pcc_lock);
  1110. return ret;
  1111. }
  1112. }
  1113. /*
  1114. * Update the pending_write to make sure a PCC CMD_READ will not
  1115. * arrive and steal the channel during the switch to write lock
  1116. */
  1117. pcc_ss_data->pending_pcc_write_cmd = true;
  1118. cpc_desc->write_cmd_id = pcc_ss_data->pcc_write_cnt;
  1119. cpc_desc->write_cmd_status = 0;
  1120. }
  1121. /*
  1122. * Skip writing MIN/MAX until Linux knows how to come up with
  1123. * useful values.
  1124. */
  1125. cpc_write(cpu, desired_reg, perf_ctrls->desired_perf);
  1126. if (CPC_IN_PCC(desired_reg))
  1127. up_read(&pcc_ss_data->pcc_lock); /* END Phase-I */
  1128. /*
  1129. * This is Phase-II where we transfer the ownership of PCC to Platform
  1130. *
  1131. * Short Summary: Basically if we think of a group of cppc_set_perf
  1132. * requests that happened in short overlapping interval. The last CPU to
  1133. * come out of Phase-I will enter Phase-II and ring the doorbell.
  1134. *
  1135. * We have the following requirements for Phase-II:
  1136. * 1. We want to execute Phase-II only when there are no CPUs
  1137. * currently executing in Phase-I
  1138. * 2. Once we start Phase-II we want to avoid all other CPUs from
  1139. * entering Phase-I.
  1140. * 3. We want only one CPU among all those who went through Phase-I
  1141. * to run phase-II
  1142. *
  1143. * If write_trylock fails to get the lock and doesn't transfer the
  1144. * PCC ownership to the platform, then one of the following will be TRUE
  1145. * 1. There is at-least one CPU in Phase-I which will later execute
  1146. * write_trylock, so the CPUs in Phase-I will be responsible for
  1147. * executing the Phase-II.
  1148. * 2. Some other CPU has beaten this CPU to successfully execute the
  1149. * write_trylock and has already acquired the write_lock. We know for a
  1150. * fact it (other CPU acquiring the write_lock) couldn't have happened
  1151. * before this CPU's Phase-I as we held the read_lock.
  1152. * 3. Some other CPU executing pcc CMD_READ has stolen the
  1153. * down_write, in which case, send_pcc_cmd will check for pending
  1154. * CMD_WRITE commands by checking the pending_pcc_write_cmd.
  1155. * So this CPU can be certain that its request will be delivered
  1156. * So in all cases, this CPU knows that its request will be delivered
  1157. * by another CPU and can return
  1158. *
  1159. * After getting the down_write we still need to check for
  1160. * pending_pcc_write_cmd to take care of the following scenario
  1161. * The thread running this code could be scheduled out between
  1162. * Phase-I and Phase-II. Before it is scheduled back on, another CPU
  1163. * could have delivered the request to Platform by triggering the
  1164. * doorbell and transferred the ownership of PCC to platform. So this
  1165. * avoids triggering an unnecessary doorbell and more importantly before
  1166. * triggering the doorbell it makes sure that the PCC channel ownership
  1167. * is still with OSPM.
  1168. * pending_pcc_write_cmd can also be cleared by a different CPU, if
  1169. * there was a pcc CMD_READ waiting on down_write and it steals the lock
  1170. * before the pcc CMD_WRITE is completed. pcc_send_cmd checks for this
  1171. * case during a CMD_READ and if there are pending writes it delivers
  1172. * the write command before servicing the read command
  1173. */
  1174. if (CPC_IN_PCC(desired_reg)) {
  1175. if (down_write_trylock(&pcc_ss_data->pcc_lock)) {/* BEGIN Phase-II */
  1176. /* Update only if there are pending write commands */
  1177. if (pcc_ss_data->pending_pcc_write_cmd)
  1178. send_pcc_cmd(pcc_ss_id, CMD_WRITE);
  1179. up_write(&pcc_ss_data->pcc_lock); /* END Phase-II */
  1180. } else
  1181. /* Wait until pcc_write_cnt is updated by send_pcc_cmd */
  1182. wait_event(pcc_ss_data->pcc_write_wait_q,
  1183. cpc_desc->write_cmd_id != pcc_ss_data->pcc_write_cnt);
  1184. /* send_pcc_cmd updates the status in case of failure */
  1185. ret = cpc_desc->write_cmd_status;
  1186. }
  1187. return ret;
  1188. }
  1189. EXPORT_SYMBOL_GPL(cppc_set_perf);
  1190. /**
  1191. * cppc_get_transition_latency - returns frequency transition latency in ns
  1192. *
  1193. * ACPI CPPC does not explicitly specifiy how a platform can specify the
  1194. * transition latency for perfromance change requests. The closest we have
  1195. * is the timing information from the PCCT tables which provides the info
  1196. * on the number and frequency of PCC commands the platform can handle.
  1197. */
  1198. unsigned int cppc_get_transition_latency(int cpu_num)
  1199. {
  1200. /*
  1201. * Expected transition latency is based on the PCCT timing values
  1202. * Below are definition from ACPI spec:
  1203. * pcc_nominal- Expected latency to process a command, in microseconds
  1204. * pcc_mpar - The maximum number of periodic requests that the subspace
  1205. * channel can support, reported in commands per minute. 0
  1206. * indicates no limitation.
  1207. * pcc_mrtt - The minimum amount of time that OSPM must wait after the
  1208. * completion of a command before issuing the next command,
  1209. * in microseconds.
  1210. */
  1211. unsigned int latency_ns = 0;
  1212. struct cpc_desc *cpc_desc;
  1213. struct cpc_register_resource *desired_reg;
  1214. int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu_num);
  1215. struct cppc_pcc_data *pcc_ss_data;
  1216. cpc_desc = per_cpu(cpc_desc_ptr, cpu_num);
  1217. if (!cpc_desc)
  1218. return CPUFREQ_ETERNAL;
  1219. desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF];
  1220. if (!CPC_IN_PCC(desired_reg))
  1221. return CPUFREQ_ETERNAL;
  1222. if (pcc_ss_id < 0)
  1223. return CPUFREQ_ETERNAL;
  1224. pcc_ss_data = pcc_data[pcc_ss_id];
  1225. if (pcc_ss_data->pcc_mpar)
  1226. latency_ns = 60 * (1000 * 1000 * 1000 / pcc_ss_data->pcc_mpar);
  1227. latency_ns = max(latency_ns, pcc_ss_data->pcc_nominal * 1000);
  1228. latency_ns = max(latency_ns, pcc_ss_data->pcc_mrtt * 1000);
  1229. return latency_ns;
  1230. }
  1231. EXPORT_SYMBOL_GPL(cppc_get_transition_latency);