memset.S 2.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (C) 2013 Regents of the University of California
  4. */
  5. #include <linux/linkage.h>
  6. #include <asm/asm.h>
  7. /* void *memset(void *, int, size_t) */
  8. ENTRY(__memset)
  9. WEAK(memset)
  10. move t0, a0 /* Preserve return value */
  11. /* Defer to byte-oriented fill for small sizes */
  12. sltiu a3, a2, 16
  13. bnez a3, 4f
  14. /*
  15. * Round to nearest XLEN-aligned address
  16. * greater than or equal to start address
  17. */
  18. addi a3, t0, SZREG-1
  19. andi a3, a3, ~(SZREG-1)
  20. beq a3, t0, 2f /* Skip if already aligned */
  21. /* Handle initial misalignment */
  22. sub a4, a3, t0
  23. 1:
  24. sb a1, 0(t0)
  25. addi t0, t0, 1
  26. bltu t0, a3, 1b
  27. sub a2, a2, a4 /* Update count */
  28. 2: /* Duff's device with 32 XLEN stores per iteration */
  29. /* Broadcast value into all bytes */
  30. andi a1, a1, 0xff
  31. slli a3, a1, 8
  32. or a1, a3, a1
  33. slli a3, a1, 16
  34. or a1, a3, a1
  35. #ifdef CONFIG_64BIT
  36. slli a3, a1, 32
  37. or a1, a3, a1
  38. #endif
  39. /* Calculate end address */
  40. andi a4, a2, ~(SZREG-1)
  41. add a3, t0, a4
  42. andi a4, a4, 31*SZREG /* Calculate remainder */
  43. beqz a4, 3f /* Shortcut if no remainder */
  44. neg a4, a4
  45. addi a4, a4, 32*SZREG /* Calculate initial offset */
  46. /* Adjust start address with offset */
  47. sub t0, t0, a4
  48. /* Jump into loop body */
  49. /* Assumes 32-bit instruction lengths */
  50. la a5, 3f
  51. #ifdef CONFIG_64BIT
  52. srli a4, a4, 1
  53. #endif
  54. add a5, a5, a4
  55. jr a5
  56. 3:
  57. REG_S a1, 0(t0)
  58. REG_S a1, SZREG(t0)
  59. REG_S a1, 2*SZREG(t0)
  60. REG_S a1, 3*SZREG(t0)
  61. REG_S a1, 4*SZREG(t0)
  62. REG_S a1, 5*SZREG(t0)
  63. REG_S a1, 6*SZREG(t0)
  64. REG_S a1, 7*SZREG(t0)
  65. REG_S a1, 8*SZREG(t0)
  66. REG_S a1, 9*SZREG(t0)
  67. REG_S a1, 10*SZREG(t0)
  68. REG_S a1, 11*SZREG(t0)
  69. REG_S a1, 12*SZREG(t0)
  70. REG_S a1, 13*SZREG(t0)
  71. REG_S a1, 14*SZREG(t0)
  72. REG_S a1, 15*SZREG(t0)
  73. REG_S a1, 16*SZREG(t0)
  74. REG_S a1, 17*SZREG(t0)
  75. REG_S a1, 18*SZREG(t0)
  76. REG_S a1, 19*SZREG(t0)
  77. REG_S a1, 20*SZREG(t0)
  78. REG_S a1, 21*SZREG(t0)
  79. REG_S a1, 22*SZREG(t0)
  80. REG_S a1, 23*SZREG(t0)
  81. REG_S a1, 24*SZREG(t0)
  82. REG_S a1, 25*SZREG(t0)
  83. REG_S a1, 26*SZREG(t0)
  84. REG_S a1, 27*SZREG(t0)
  85. REG_S a1, 28*SZREG(t0)
  86. REG_S a1, 29*SZREG(t0)
  87. REG_S a1, 30*SZREG(t0)
  88. REG_S a1, 31*SZREG(t0)
  89. addi t0, t0, 32*SZREG
  90. bltu t0, a3, 3b
  91. andi a2, a2, SZREG-1 /* Update count */
  92. 4:
  93. /* Handle trailing misalignment */
  94. beqz a2, 6f
  95. add a3, t0, a2
  96. 5:
  97. sb a1, 0(t0)
  98. addi t0, t0, 1
  99. bltu t0, a3, 5b
  100. 6:
  101. ret
  102. END(__memset)