sys_riscv.c 2.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2012 Regents of the University of California
  4. * Copyright (C) 2014 Darius Rad <darius@bluespec.com>
  5. * Copyright (C) 2017 SiFive
  6. */
  7. #include <linux/syscalls.h>
  8. #include <asm/unistd.h>
  9. #include <asm/cacheflush.h>
  10. #include <asm-generic/mman-common.h>
  11. static long riscv_sys_mmap(unsigned long addr, unsigned long len,
  12. unsigned long prot, unsigned long flags,
  13. unsigned long fd, off_t offset,
  14. unsigned long page_shift_offset)
  15. {
  16. if (unlikely(offset & (~PAGE_MASK >> page_shift_offset)))
  17. return -EINVAL;
  18. if ((prot & PROT_WRITE) && (prot & PROT_EXEC))
  19. if (unlikely(!(prot & PROT_READ)))
  20. return -EINVAL;
  21. return ksys_mmap_pgoff(addr, len, prot, flags, fd,
  22. offset >> (PAGE_SHIFT - page_shift_offset));
  23. }
  24. #ifdef CONFIG_64BIT
  25. SYSCALL_DEFINE6(mmap, unsigned long, addr, unsigned long, len,
  26. unsigned long, prot, unsigned long, flags,
  27. unsigned long, fd, off_t, offset)
  28. {
  29. return riscv_sys_mmap(addr, len, prot, flags, fd, offset, 0);
  30. }
  31. #else
  32. SYSCALL_DEFINE6(mmap2, unsigned long, addr, unsigned long, len,
  33. unsigned long, prot, unsigned long, flags,
  34. unsigned long, fd, off_t, offset)
  35. {
  36. /*
  37. * Note that the shift for mmap2 is constant (12),
  38. * regardless of PAGE_SIZE
  39. */
  40. return riscv_sys_mmap(addr, len, prot, flags, fd, offset, 12);
  41. }
  42. #endif /* !CONFIG_64BIT */
  43. /*
  44. * Allows the instruction cache to be flushed from userspace. Despite RISC-V
  45. * having a direct 'fence.i' instruction available to userspace (which we
  46. * can't trap!), that's not actually viable when running on Linux because the
  47. * kernel might schedule a process on another hart. There is no way for
  48. * userspace to handle this without invoking the kernel (as it doesn't know the
  49. * thread->hart mappings), so we've defined a RISC-V specific system call to
  50. * flush the instruction cache.
  51. *
  52. * sys_riscv_flush_icache() is defined to flush the instruction cache over an
  53. * address range, with the flush applying to either all threads or just the
  54. * caller. We don't currently do anything with the address range, that's just
  55. * in there for forwards compatibility.
  56. */
  57. SYSCALL_DEFINE3(riscv_flush_icache, uintptr_t, start, uintptr_t, end,
  58. uintptr_t, flags)
  59. {
  60. /* Check the reserved flags. */
  61. if (unlikely(flags & ~SYS_RISCV_FLUSH_ICACHE_ALL))
  62. return -EINVAL;
  63. flush_icache_mm(current->mm, flags & SYS_RISCV_FLUSH_ICACHE_LOCAL);
  64. return 0;
  65. }