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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (C) 2012 Regents of the University of California
  4. */
  5. #include <asm/asm-offsets.h>
  6. #include <asm/asm.h>
  7. #include <linux/init.h>
  8. #include <linux/linkage.h>
  9. #include <asm/thread_info.h>
  10. #include <asm/page.h>
  11. #include <asm/csr.h>
  12. #include <asm/hwcap.h>
  13. #include <asm/image.h>
  14. #include "efi-header.S"
  15. __HEAD
  16. ENTRY(_start)
  17. /*
  18. * Image header expected by Linux boot-loaders. The image header data
  19. * structure is described in asm/image.h.
  20. * Do not modify it without modifying the structure and all bootloaders
  21. * that expects this header format!!
  22. */
  23. #ifdef CONFIG_EFI
  24. /*
  25. * This instruction decodes to "MZ" ASCII required by UEFI.
  26. */
  27. c.li s4,-13
  28. j _start_kernel
  29. #else
  30. /* jump to start kernel */
  31. j _start_kernel
  32. /* reserved */
  33. .word 0
  34. #endif
  35. .balign 8
  36. #ifdef CONFIG_RISCV_M_MODE
  37. /* Image load offset (0MB) from start of RAM for M-mode */
  38. .dword 0
  39. #else
  40. #if __riscv_xlen == 64
  41. /* Image load offset(2MB) from start of RAM */
  42. .dword 0x200000
  43. #else
  44. /* Image load offset(4MB) from start of RAM */
  45. .dword 0x400000
  46. #endif
  47. #endif
  48. /* Effective size of kernel image */
  49. .dword _end - _start
  50. .dword __HEAD_FLAGS
  51. .word RISCV_HEADER_VERSION
  52. .word 0
  53. .dword 0
  54. .ascii RISCV_IMAGE_MAGIC
  55. .balign 4
  56. .ascii RISCV_IMAGE_MAGIC2
  57. #ifdef CONFIG_EFI
  58. .word pe_head_start - _start
  59. pe_head_start:
  60. __EFI_PE_HEADER
  61. #else
  62. .word 0
  63. #endif
  64. .align 2
  65. #ifdef CONFIG_MMU
  66. relocate:
  67. /* Relocate return address */
  68. li a1, PAGE_OFFSET
  69. la a2, _start
  70. sub a1, a1, a2
  71. add ra, ra, a1
  72. /* Point stvec to virtual address of intruction after satp write */
  73. la a2, 1f
  74. add a2, a2, a1
  75. csrw CSR_TVEC, a2
  76. /* Compute satp for kernel page tables, but don't load it yet */
  77. srl a2, a0, PAGE_SHIFT
  78. li a1, SATP_MODE
  79. or a2, a2, a1
  80. /*
  81. * Load trampoline page directory, which will cause us to trap to
  82. * stvec if VA != PA, or simply fall through if VA == PA. We need a
  83. * full fence here because setup_vm() just wrote these PTEs and we need
  84. * to ensure the new translations are in use.
  85. */
  86. la a0, trampoline_pg_dir
  87. srl a0, a0, PAGE_SHIFT
  88. or a0, a0, a1
  89. sfence.vma
  90. csrw CSR_SATP, a0
  91. .align 2
  92. 1:
  93. /* Set trap vector to spin forever to help debug */
  94. la a0, .Lsecondary_park
  95. csrw CSR_TVEC, a0
  96. /* Reload the global pointer */
  97. .option push
  98. .option norelax
  99. la gp, __global_pointer$
  100. .option pop
  101. /*
  102. * Switch to kernel page tables. A full fence is necessary in order to
  103. * avoid using the trampoline translations, which are only correct for
  104. * the first superpage. Fetching the fence is guarnteed to work
  105. * because that first superpage is translated the same way.
  106. */
  107. csrw CSR_SATP, a2
  108. sfence.vma
  109. ret
  110. #endif /* CONFIG_MMU */
  111. #ifdef CONFIG_SMP
  112. .global secondary_start_sbi
  113. secondary_start_sbi:
  114. /* Mask all interrupts */
  115. csrw CSR_IE, zero
  116. csrw CSR_IP, zero
  117. /* Load the global pointer */
  118. .option push
  119. .option norelax
  120. la gp, __global_pointer$
  121. .option pop
  122. /*
  123. * Disable FPU to detect illegal usage of
  124. * floating point in kernel space
  125. */
  126. li t0, SR_FS
  127. csrc CSR_STATUS, t0
  128. /* Set trap vector to spin forever to help debug */
  129. la a3, .Lsecondary_park
  130. csrw CSR_TVEC, a3
  131. slli a3, a0, LGREG
  132. la a4, __cpu_up_stack_pointer
  133. la a5, __cpu_up_task_pointer
  134. add a4, a3, a4
  135. add a5, a3, a5
  136. REG_L sp, (a4)
  137. REG_L tp, (a5)
  138. .global secondary_start_common
  139. secondary_start_common:
  140. #ifdef CONFIG_MMU
  141. /* Enable virtual memory and relocate to virtual address */
  142. la a0, swapper_pg_dir
  143. call relocate
  144. #endif
  145. call setup_trap_vector
  146. tail smp_callin
  147. #endif /* CONFIG_SMP */
  148. .align 2
  149. setup_trap_vector:
  150. /* Set trap vector to exception handler */
  151. la a0, handle_exception
  152. csrw CSR_TVEC, a0
  153. /*
  154. * Set sup0 scratch register to 0, indicating to exception vector that
  155. * we are presently executing in kernel.
  156. */
  157. csrw CSR_SCRATCH, zero
  158. ret
  159. .align 2
  160. .Lsecondary_park:
  161. /* We lack SMP support or have too many harts, so park this hart */
  162. wfi
  163. j .Lsecondary_park
  164. END(_start)
  165. __INIT
  166. ENTRY(_start_kernel)
  167. /* Mask all interrupts */
  168. csrw CSR_IE, zero
  169. csrw CSR_IP, zero
  170. #ifdef CONFIG_RISCV_M_MODE
  171. /* flush the instruction cache */
  172. fence.i
  173. /* Reset all registers except ra, a0, a1 */
  174. call reset_regs
  175. /*
  176. * Setup a PMP to permit access to all of memory. Some machines may
  177. * not implement PMPs, so we set up a quick trap handler to just skip
  178. * touching the PMPs on any trap.
  179. */
  180. la a0, pmp_done
  181. csrw CSR_TVEC, a0
  182. li a0, -1
  183. csrw CSR_PMPADDR0, a0
  184. li a0, (PMP_A_NAPOT | PMP_R | PMP_W | PMP_X)
  185. csrw CSR_PMPCFG0, a0
  186. .align 2
  187. pmp_done:
  188. /*
  189. * The hartid in a0 is expected later on, and we have no firmware
  190. * to hand it to us.
  191. */
  192. csrr a0, CSR_MHARTID
  193. #endif /* CONFIG_RISCV_M_MODE */
  194. /* Load the global pointer */
  195. .option push
  196. .option norelax
  197. la gp, __global_pointer$
  198. .option pop
  199. /*
  200. * Disable FPU to detect illegal usage of
  201. * floating point in kernel space
  202. */
  203. li t0, SR_FS | SR_VS
  204. csrc CSR_STATUS, t0
  205. #ifdef CONFIG_SMP
  206. li t0, CONFIG_NR_CPUS
  207. blt a0, t0, .Lgood_cores
  208. tail .Lsecondary_park
  209. .Lgood_cores:
  210. #endif
  211. /* Pick one hart to run the main boot sequence */
  212. la a3, hart_lottery
  213. li a2, 1
  214. amoadd.w a3, a2, (a3)
  215. bnez a3, .Lsecondary_start
  216. /* Clear BSS for flat non-ELF images */
  217. la a3, __bss_start
  218. la a4, __bss_stop
  219. ble a4, a3, clear_bss_done
  220. clear_bss:
  221. REG_S zero, (a3)
  222. add a3, a3, RISCV_SZPTR
  223. blt a3, a4, clear_bss
  224. clear_bss_done:
  225. /* Save hart ID and DTB physical address */
  226. mv s0, a0
  227. mv s1, a1
  228. la a2, boot_cpu_hartid
  229. REG_S a0, (a2)
  230. /* Initialize page tables and relocate to virtual addresses */
  231. la sp, init_thread_union + THREAD_SIZE
  232. mv a0, s1
  233. call setup_vm
  234. #ifdef CONFIG_MMU
  235. la a0, early_pg_dir
  236. call relocate
  237. #endif /* CONFIG_MMU */
  238. call setup_trap_vector
  239. /* Restore C environment */
  240. la tp, init_task
  241. sw zero, TASK_TI_CPU(tp)
  242. la sp, init_thread_union + THREAD_SIZE
  243. #ifdef CONFIG_KASAN
  244. call kasan_early_init
  245. #endif
  246. /* Start the kernel */
  247. call soc_early_init
  248. tail start_kernel
  249. .Lsecondary_start:
  250. #ifdef CONFIG_SMP
  251. /* Set trap vector to spin forever to help debug */
  252. la a3, .Lsecondary_park
  253. csrw CSR_TVEC, a3
  254. slli a3, a0, LGREG
  255. la a1, __cpu_up_stack_pointer
  256. la a2, __cpu_up_task_pointer
  257. add a1, a3, a1
  258. add a2, a3, a2
  259. /*
  260. * This hart didn't win the lottery, so we wait for the winning hart to
  261. * get far enough along the boot process that it should continue.
  262. */
  263. .Lwait_for_cpu_up:
  264. /* FIXME: We should WFI to save some energy here. */
  265. REG_L sp, (a1)
  266. REG_L tp, (a2)
  267. beqz sp, .Lwait_for_cpu_up
  268. beqz tp, .Lwait_for_cpu_up
  269. fence
  270. tail secondary_start_common
  271. #endif
  272. END(_start_kernel)
  273. #ifdef CONFIG_RISCV_M_MODE
  274. ENTRY(reset_regs)
  275. li sp, 0
  276. li gp, 0
  277. li tp, 0
  278. li t0, 0
  279. li t1, 0
  280. li t2, 0
  281. li s0, 0
  282. li s1, 0
  283. li a2, 0
  284. li a3, 0
  285. li a4, 0
  286. li a5, 0
  287. li a6, 0
  288. li a7, 0
  289. li s2, 0
  290. li s3, 0
  291. li s4, 0
  292. li s5, 0
  293. li s6, 0
  294. li s7, 0
  295. li s8, 0
  296. li s9, 0
  297. li s10, 0
  298. li s11, 0
  299. li t3, 0
  300. li t4, 0
  301. li t5, 0
  302. li t6, 0
  303. csrw CSR_SCRATCH, 0
  304. #ifdef CONFIG_FPU
  305. csrr t0, CSR_MISA
  306. andi t0, t0, (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D)
  307. beqz t0, .Lreset_regs_done
  308. li t1, SR_FS
  309. csrs CSR_STATUS, t1
  310. fmv.s.x f0, zero
  311. fmv.s.x f1, zero
  312. fmv.s.x f2, zero
  313. fmv.s.x f3, zero
  314. fmv.s.x f4, zero
  315. fmv.s.x f5, zero
  316. fmv.s.x f6, zero
  317. fmv.s.x f7, zero
  318. fmv.s.x f8, zero
  319. fmv.s.x f9, zero
  320. fmv.s.x f10, zero
  321. fmv.s.x f11, zero
  322. fmv.s.x f12, zero
  323. fmv.s.x f13, zero
  324. fmv.s.x f14, zero
  325. fmv.s.x f15, zero
  326. fmv.s.x f16, zero
  327. fmv.s.x f17, zero
  328. fmv.s.x f18, zero
  329. fmv.s.x f19, zero
  330. fmv.s.x f20, zero
  331. fmv.s.x f21, zero
  332. fmv.s.x f22, zero
  333. fmv.s.x f23, zero
  334. fmv.s.x f24, zero
  335. fmv.s.x f25, zero
  336. fmv.s.x f26, zero
  337. fmv.s.x f27, zero
  338. fmv.s.x f28, zero
  339. fmv.s.x f29, zero
  340. fmv.s.x f30, zero
  341. fmv.s.x f31, zero
  342. csrw fcsr, 0
  343. /* note that the caller must clear SR_FS */
  344. #endif /* CONFIG_FPU */
  345. .Lreset_regs_done:
  346. ret
  347. END(reset_regs)
  348. #endif /* CONFIG_RISCV_M_MODE */
  349. __PAGE_ALIGNED_BSS
  350. /* Empty zero page */
  351. .balign PAGE_SIZE