cpufeature.c 4.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copied from arch/arm64/kernel/cpufeature.c
  4. *
  5. * Copyright (C) 2015 ARM Ltd.
  6. * Copyright (C) 2017 SiFive
  7. */
  8. #include <linux/bitmap.h>
  9. #include <linux/of.h>
  10. #include <asm/processor.h>
  11. #include <asm/hwcap.h>
  12. #include <asm/smp.h>
  13. #include <asm/switch_to.h>
  14. unsigned long elf_hwcap __read_mostly;
  15. /* Host ISA bitmap */
  16. static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;
  17. #ifdef CONFIG_FPU
  18. bool has_fpu __read_mostly;
  19. #endif
  20. /**
  21. * riscv_isa_extension_base() - Get base extension word
  22. *
  23. * @isa_bitmap: ISA bitmap to use
  24. * Return: base extension word as unsigned long value
  25. *
  26. * NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used.
  27. */
  28. unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap)
  29. {
  30. if (!isa_bitmap)
  31. return riscv_isa[0];
  32. return isa_bitmap[0];
  33. }
  34. EXPORT_SYMBOL_GPL(riscv_isa_extension_base);
  35. /**
  36. * __riscv_isa_extension_available() - Check whether given extension
  37. * is available or not
  38. *
  39. * @isa_bitmap: ISA bitmap to use
  40. * @bit: bit position of the desired extension
  41. * Return: true or false
  42. *
  43. * NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used.
  44. */
  45. bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit)
  46. {
  47. const unsigned long *bmap = (isa_bitmap) ? isa_bitmap : riscv_isa;
  48. if (bit >= RISCV_ISA_EXT_MAX)
  49. return false;
  50. return test_bit(bit, bmap) ? true : false;
  51. }
  52. EXPORT_SYMBOL_GPL(__riscv_isa_extension_available);
  53. #ifdef CONFIG_VECTOR
  54. bool has_vector __read_mostly;
  55. #endif
  56. void riscv_fill_hwcap(void)
  57. {
  58. struct device_node *node;
  59. const char *isa;
  60. char print_str[BITS_PER_LONG + 1];
  61. size_t i, j, isa_len;
  62. static unsigned long isa2hwcap[256] = {0};
  63. isa2hwcap['i'] = isa2hwcap['I'] = COMPAT_HWCAP_ISA_I;
  64. isa2hwcap['m'] = isa2hwcap['M'] = COMPAT_HWCAP_ISA_M;
  65. isa2hwcap['a'] = isa2hwcap['A'] = COMPAT_HWCAP_ISA_A;
  66. isa2hwcap['f'] = isa2hwcap['F'] = COMPAT_HWCAP_ISA_F;
  67. isa2hwcap['d'] = isa2hwcap['D'] = COMPAT_HWCAP_ISA_D;
  68. isa2hwcap['c'] = isa2hwcap['C'] = COMPAT_HWCAP_ISA_C;
  69. isa2hwcap['v'] = isa2hwcap['V'] = COMPAT_HWCAP_ISA_V;
  70. elf_hwcap = 0;
  71. bitmap_zero(riscv_isa, RISCV_ISA_EXT_MAX);
  72. for_each_of_cpu_node(node) {
  73. unsigned long this_hwcap = 0;
  74. unsigned long this_isa = 0;
  75. if (riscv_of_processor_hartid(node) < 0)
  76. continue;
  77. if (of_property_read_string(node, "riscv,isa", &isa)) {
  78. pr_warn("Unable to find \"riscv,isa\" devicetree entry\n");
  79. continue;
  80. }
  81. i = 0;
  82. isa_len = strlen(isa);
  83. #if IS_ENABLED(CONFIG_32BIT)
  84. if (!strncmp(isa, "rv32", 4))
  85. i += 4;
  86. #elif IS_ENABLED(CONFIG_64BIT)
  87. if (!strncmp(isa, "rv64", 4))
  88. i += 4;
  89. #endif
  90. for (; i < isa_len; ++i) {
  91. this_hwcap |= isa2hwcap[(unsigned char)(isa[i])];
  92. /*
  93. * TODO: X, Y and Z extension parsing for Host ISA
  94. * bitmap will be added in-future.
  95. */
  96. if ('a' <= isa[i] && isa[i] < 'x')
  97. this_isa |= (1UL << (isa[i] - 'a'));
  98. }
  99. /*
  100. * All "okay" hart should have same isa. Set HWCAP based on
  101. * common capabilities of every "okay" hart, in case they don't
  102. * have.
  103. */
  104. if (elf_hwcap)
  105. elf_hwcap &= this_hwcap;
  106. else
  107. elf_hwcap = this_hwcap;
  108. if (riscv_isa[0])
  109. riscv_isa[0] &= this_isa;
  110. else
  111. riscv_isa[0] = this_isa;
  112. }
  113. /* We don't support systems with F but without D, so mask those out
  114. * here. */
  115. if ((elf_hwcap & COMPAT_HWCAP_ISA_F) && !(elf_hwcap & COMPAT_HWCAP_ISA_D)) {
  116. pr_info("This kernel does not support systems with F but not D\n");
  117. elf_hwcap &= ~COMPAT_HWCAP_ISA_F;
  118. }
  119. memset(print_str, 0, sizeof(print_str));
  120. for (i = 0, j = 0; i < BITS_PER_LONG; i++)
  121. if (riscv_isa[0] & BIT_MASK(i))
  122. print_str[j++] = (char)('a' + i);
  123. pr_info("riscv: ISA extensions %s\n", print_str);
  124. memset(print_str, 0, sizeof(print_str));
  125. for (i = 0, j = 0; i < BITS_PER_LONG; i++)
  126. if (elf_hwcap & BIT_MASK(i))
  127. print_str[j++] = (char)('a' + i);
  128. pr_info("riscv: ELF capabilities %s\n", print_str);
  129. #ifdef CONFIG_FPU
  130. if (elf_hwcap & (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D))
  131. has_fpu = true;
  132. #endif
  133. #ifdef CONFIG_VECTOR
  134. if (elf_hwcap & COMPAT_HWCAP_ISA_V)
  135. has_vector = true;
  136. #endif
  137. }