perf_event.h 2.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2018 SiFive
  4. * Copyright (C) 2018 Andes Technology Corporation
  5. *
  6. */
  7. #ifndef _ASM_RISCV_PERF_EVENT_H
  8. #define _ASM_RISCV_PERF_EVENT_H
  9. #include <linux/perf_event.h>
  10. #include <linux/ptrace.h>
  11. #include <linux/interrupt.h>
  12. #ifdef CONFIG_RISCV_BASE_PMU
  13. #define RISCV_BASE_COUNTERS 2
  14. /*
  15. * The RISCV_MAX_COUNTERS parameter should be specified.
  16. */
  17. #define RISCV_MAX_COUNTERS 2
  18. /*
  19. * These are the indexes of bits in counteren register *minus* 1,
  20. * except for cycle. It would be coherent if it can directly mapped
  21. * to counteren bit definition, but there is a *time* register at
  22. * counteren[1]. Per-cpu structure is scarce resource here.
  23. *
  24. * According to the spec, an implementation can support counter up to
  25. * mhpmcounter31, but many high-end processors has at most 6 general
  26. * PMCs, we give the definition to MHPMCOUNTER8 here.
  27. */
  28. #define RISCV_PMU_CYCLE 0
  29. #define RISCV_PMU_INSTRET 1
  30. #define RISCV_PMU_MHPMCOUNTER3 2
  31. #define RISCV_PMU_MHPMCOUNTER4 3
  32. #define RISCV_PMU_MHPMCOUNTER5 4
  33. #define RISCV_PMU_MHPMCOUNTER6 5
  34. #define RISCV_PMU_MHPMCOUNTER7 6
  35. #define RISCV_PMU_MHPMCOUNTER8 7
  36. #define RISCV_OP_UNSUPP (-EOPNOTSUPP)
  37. struct cpu_hw_events {
  38. /* # currently enabled events*/
  39. int n_events;
  40. /* currently enabled events */
  41. struct perf_event *events[RISCV_MAX_COUNTERS];
  42. /* vendor-defined PMU data */
  43. void *platform;
  44. };
  45. struct riscv_pmu {
  46. struct pmu *pmu;
  47. /* generic hw/cache events table */
  48. const int *hw_events;
  49. const int (*cache_events)[PERF_COUNT_HW_CACHE_MAX]
  50. [PERF_COUNT_HW_CACHE_OP_MAX]
  51. [PERF_COUNT_HW_CACHE_RESULT_MAX];
  52. /* method used to map hw/cache events */
  53. int (*map_hw_event)(u64 config);
  54. int (*map_cache_event)(u64 config);
  55. /* max generic hw events in map */
  56. int max_events;
  57. /* number total counters, 2(base) + x(general) */
  58. int num_counters;
  59. /* the width of the counter */
  60. int counter_width;
  61. /* vendor-defined PMU features */
  62. void *platform;
  63. irqreturn_t (*handle_irq)(int irq_num, void *dev);
  64. int irq;
  65. };
  66. #endif
  67. #ifdef CONFIG_PERF_EVENTS
  68. #define perf_arch_bpf_user_pt_regs(regs) (struct user_regs_struct *)regs
  69. #endif
  70. #endif /* _ASM_RISCV_PERF_EVENT_H */