parse_asm.h 7.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (C) 2020 SiFive
  4. */
  5. #include <linux/bits.h>
  6. /* The bit field of immediate value in I-type instruction */
  7. #define I_IMM_SIGN_OPOFF 31
  8. #define I_IMM_11_0_OPOFF 20
  9. #define I_IMM_SIGN_OFF 12
  10. #define I_IMM_11_0_OFF 0
  11. #define I_IMM_11_0_MASK GENMASK(11, 0)
  12. /* The bit field of immediate value in J-type instruction */
  13. #define J_IMM_SIGN_OPOFF 31
  14. #define J_IMM_10_1_OPOFF 21
  15. #define J_IMM_11_OPOFF 20
  16. #define J_IMM_19_12_OPOFF 12
  17. #define J_IMM_SIGN_OFF 20
  18. #define J_IMM_10_1_OFF 1
  19. #define J_IMM_11_OFF 11
  20. #define J_IMM_19_12_OFF 12
  21. #define J_IMM_10_1_MASK GENMASK(9, 0)
  22. #define J_IMM_11_MASK GENMASK(0, 0)
  23. #define J_IMM_19_12_MASK GENMASK(7, 0)
  24. /* The bit field of immediate value in B-type instruction */
  25. #define B_IMM_SIGN_OPOFF 31
  26. #define B_IMM_10_5_OPOFF 25
  27. #define B_IMM_4_1_OPOFF 8
  28. #define B_IMM_11_OPOFF 7
  29. #define B_IMM_SIGN_OFF 12
  30. #define B_IMM_10_5_OFF 5
  31. #define B_IMM_4_1_OFF 1
  32. #define B_IMM_11_OFF 11
  33. #define B_IMM_10_5_MASK GENMASK(5, 0)
  34. #define B_IMM_4_1_MASK GENMASK(3, 0)
  35. #define B_IMM_11_MASK GENMASK(0, 0)
  36. /* The register offset in RVG instruction */
  37. #define RVG_RS1_OPOFF 15
  38. #define RVG_RS2_OPOFF 20
  39. #define RVG_RD_OPOFF 7
  40. /* The bit field of immediate value in RVC J instruction */
  41. #define RVC_J_IMM_SIGN_OPOFF 12
  42. #define RVC_J_IMM_4_OPOFF 11
  43. #define RVC_J_IMM_9_8_OPOFF 9
  44. #define RVC_J_IMM_10_OPOFF 8
  45. #define RVC_J_IMM_6_OPOFF 7
  46. #define RVC_J_IMM_7_OPOFF 6
  47. #define RVC_J_IMM_3_1_OPOFF 3
  48. #define RVC_J_IMM_5_OPOFF 2
  49. #define RVC_J_IMM_SIGN_OFF 11
  50. #define RVC_J_IMM_4_OFF 4
  51. #define RVC_J_IMM_9_8_OFF 8
  52. #define RVC_J_IMM_10_OFF 10
  53. #define RVC_J_IMM_6_OFF 6
  54. #define RVC_J_IMM_7_OFF 7
  55. #define RVC_J_IMM_3_1_OFF 1
  56. #define RVC_J_IMM_5_OFF 5
  57. #define RVC_J_IMM_4_MASK GENMASK(0, 0)
  58. #define RVC_J_IMM_9_8_MASK GENMASK(1, 0)
  59. #define RVC_J_IMM_10_MASK GENMASK(0, 0)
  60. #define RVC_J_IMM_6_MASK GENMASK(0, 0)
  61. #define RVC_J_IMM_7_MASK GENMASK(0, 0)
  62. #define RVC_J_IMM_3_1_MASK GENMASK(2, 0)
  63. #define RVC_J_IMM_5_MASK GENMASK(0, 0)
  64. /* The bit field of immediate value in RVC B instruction */
  65. #define RVC_B_IMM_SIGN_OPOFF 12
  66. #define RVC_B_IMM_4_3_OPOFF 10
  67. #define RVC_B_IMM_7_6_OPOFF 5
  68. #define RVC_B_IMM_2_1_OPOFF 3
  69. #define RVC_B_IMM_5_OPOFF 2
  70. #define RVC_B_IMM_SIGN_OFF 8
  71. #define RVC_B_IMM_4_3_OFF 3
  72. #define RVC_B_IMM_7_6_OFF 6
  73. #define RVC_B_IMM_2_1_OFF 1
  74. #define RVC_B_IMM_5_OFF 5
  75. #define RVC_B_IMM_4_3_MASK GENMASK(1, 0)
  76. #define RVC_B_IMM_7_6_MASK GENMASK(1, 0)
  77. #define RVC_B_IMM_2_1_MASK GENMASK(1, 0)
  78. #define RVC_B_IMM_5_MASK GENMASK(0, 0)
  79. /* The register offset in RVC op=C0 instruction */
  80. #define RVC_C0_RS1_OPOFF 7
  81. #define RVC_C0_RS2_OPOFF 2
  82. #define RVC_C0_RD_OPOFF 2
  83. /* The register offset in RVC op=C1 instruction */
  84. #define RVC_C1_RS1_OPOFF 7
  85. #define RVC_C1_RS2_OPOFF 2
  86. #define RVC_C1_RD_OPOFF 7
  87. /* The register offset in RVC op=C2 instruction */
  88. #define RVC_C2_RS1_OPOFF 7
  89. #define RVC_C2_RS2_OPOFF 2
  90. #define RVC_C2_RD_OPOFF 7
  91. /* parts of opcode for RVG*/
  92. #define OPCODE_BRANCH 0x63
  93. #define OPCODE_JALR 0x67
  94. #define OPCODE_JAL 0x6f
  95. #define OPCODE_SYSTEM 0x73
  96. /* parts of opcode for RVC*/
  97. #define OPCODE_C_0 0x0
  98. #define OPCODE_C_1 0x1
  99. #define OPCODE_C_2 0x2
  100. /* parts of funct3 code for I, M, A extension*/
  101. #define FUNCT3_JALR 0x0
  102. #define FUNCT3_BEQ 0x0
  103. #define FUNCT3_BNE 0x1000
  104. #define FUNCT3_BLT 0x4000
  105. #define FUNCT3_BGE 0x5000
  106. #define FUNCT3_BLTU 0x6000
  107. #define FUNCT3_BGEU 0x7000
  108. /* parts of funct3 code for C extension*/
  109. #define FUNCT3_C_BEQZ 0xc000
  110. #define FUNCT3_C_BNEZ 0xe000
  111. #define FUNCT3_C_J 0xa000
  112. #define FUNCT3_C_JAL 0x2000
  113. #define FUNCT4_C_JR 0x8000
  114. #define FUNCT4_C_JALR 0xf000
  115. #define FUNCT12_SRET 0x10200000
  116. #define MATCH_JALR (FUNCT3_JALR | OPCODE_JALR)
  117. #define MATCH_JAL (OPCODE_JAL)
  118. #define MATCH_BEQ (FUNCT3_BEQ | OPCODE_BRANCH)
  119. #define MATCH_BNE (FUNCT3_BNE | OPCODE_BRANCH)
  120. #define MATCH_BLT (FUNCT3_BLT | OPCODE_BRANCH)
  121. #define MATCH_BGE (FUNCT3_BGE | OPCODE_BRANCH)
  122. #define MATCH_BLTU (FUNCT3_BLTU | OPCODE_BRANCH)
  123. #define MATCH_BGEU (FUNCT3_BGEU | OPCODE_BRANCH)
  124. #define MATCH_SRET (FUNCT12_SRET | OPCODE_SYSTEM)
  125. #define MATCH_C_BEQZ (FUNCT3_C_BEQZ | OPCODE_C_1)
  126. #define MATCH_C_BNEZ (FUNCT3_C_BNEZ | OPCODE_C_1)
  127. #define MATCH_C_J (FUNCT3_C_J | OPCODE_C_1)
  128. #define MATCH_C_JAL (FUNCT3_C_JAL | OPCODE_C_1)
  129. #define MATCH_C_JR (FUNCT4_C_JR | OPCODE_C_2)
  130. #define MATCH_C_JALR (FUNCT4_C_JALR | OPCODE_C_2)
  131. #define MASK_JALR 0x707f
  132. #define MASK_JAL 0x7f
  133. #define MASK_C_JALR 0xf07f
  134. #define MASK_C_JR 0xf07f
  135. #define MASK_C_JAL 0xe003
  136. #define MASK_C_J 0xe003
  137. #define MASK_BEQ 0x707f
  138. #define MASK_BNE 0x707f
  139. #define MASK_BLT 0x707f
  140. #define MASK_BGE 0x707f
  141. #define MASK_BLTU 0x707f
  142. #define MASK_BGEU 0x707f
  143. #define MASK_C_BEQZ 0xe003
  144. #define MASK_C_BNEZ 0xe003
  145. #define MASK_SRET 0xffffffff
  146. #define __INSN_LENGTH_MASK _UL(0x3)
  147. #define __INSN_LENGTH_GE_32 _UL(0x3)
  148. #define __INSN_OPCODE_MASK _UL(0x7F)
  149. #define __INSN_BRANCH_OPCODE _UL(OPCODE_BRANCH)
  150. /* Define a series of is_XXX_insn functions to check if the value INSN
  151. * is an instance of instruction XXX.
  152. */
  153. #define DECLARE_INSN(INSN_NAME, INSN_MATCH, INSN_MASK) \
  154. static inline bool is_ ## INSN_NAME ## _insn(long insn) \
  155. { \
  156. return (insn & (INSN_MASK)) == (INSN_MATCH); \
  157. }
  158. #define RV_IMM_SIGN(x) (-(((x) >> 31) & 1))
  159. #define RVC_IMM_SIGN(x) (-(((x) >> 12) & 1))
  160. #define RV_X(X, s, mask) (((X) >> (s)) & (mask))
  161. #define RVC_X(X, s, mask) RV_X(X, s, mask)
  162. #define EXTRACT_JTYPE_IMM(x) \
  163. ({typeof(x) x_ = (x); \
  164. (RV_X(x_, J_IMM_10_1_OPOFF, J_IMM_10_1_MASK) << J_IMM_10_1_OFF) | \
  165. (RV_X(x_, J_IMM_11_OPOFF, J_IMM_11_MASK) << J_IMM_11_OFF) | \
  166. (RV_X(x_, J_IMM_19_12_OPOFF, J_IMM_19_12_MASK) << J_IMM_19_12_OFF) | \
  167. (RV_IMM_SIGN(x_) << J_IMM_SIGN_OFF); })
  168. #define EXTRACT_ITYPE_IMM(x) \
  169. ({typeof(x) x_ = (x); \
  170. (RV_X(x_, I_IMM_11_0_OPOFF, I_IMM_11_0_MASK)) | \
  171. (RV_IMM_SIGN(x_) << I_IMM_SIGN_OFF); })
  172. #define EXTRACT_BTYPE_IMM(x) \
  173. ({typeof(x) x_ = (x); \
  174. (RV_X(x_, B_IMM_4_1_OPOFF, B_IMM_4_1_MASK) << B_IMM_4_1_OFF) | \
  175. (RV_X(x_, B_IMM_10_5_OPOFF, B_IMM_10_5_MASK) << B_IMM_10_5_OFF) | \
  176. (RV_X(x_, B_IMM_11_OPOFF, B_IMM_11_MASK) << B_IMM_11_OFF) | \
  177. (RV_IMM_SIGN(x_) << B_IMM_SIGN_OFF); })
  178. #define EXTRACT_RVC_J_IMM(x) \
  179. ({typeof(x) x_ = (x); \
  180. (RVC_X(x_, RVC_J_IMM_3_1_OPOFF, RVC_J_IMM_3_1_MASK) << RVC_J_IMM_3_1_OFF) | \
  181. (RVC_X(x_, RVC_J_IMM_4_OPOFF, RVC_J_IMM_4_MASK) << RVC_J_IMM_4_OFF) | \
  182. (RVC_X(x_, RVC_J_IMM_5_OPOFF, RVC_J_IMM_5_MASK) << RVC_J_IMM_5_OFF) | \
  183. (RVC_X(x_, RVC_J_IMM_6_OPOFF, RVC_J_IMM_6_MASK) << RVC_J_IMM_6_OFF) | \
  184. (RVC_X(x_, RVC_J_IMM_7_OPOFF, RVC_J_IMM_7_MASK) << RVC_J_IMM_7_OFF) | \
  185. (RVC_X(x_, RVC_J_IMM_9_8_OPOFF, RVC_J_IMM_9_8_MASK) << RVC_J_IMM_9_8_OFF) | \
  186. (RVC_X(x_, RVC_J_IMM_10_OPOFF, RVC_J_IMM_10_MASK) << RVC_J_IMM_10_OFF) | \
  187. (RVC_IMM_SIGN(x_) << RVC_J_IMM_SIGN_OFF); })
  188. #define EXTRACT_RVC_B_IMM(x) \
  189. ({typeof(x) x_ = (x); \
  190. (RVC_X(x_, RVC_B_IMM_2_1_OPOFF, RVC_B_IMM_2_1_MASK) << RVC_B_IMM_2_1_OFF) | \
  191. (RVC_X(x_, RVC_B_IMM_4_3_OPOFF, RVC_B_IMM_4_3_MASK) << RVC_B_IMM_4_3_OFF) | \
  192. (RVC_X(x_, RVC_B_IMM_5_OPOFF, RVC_B_IMM_5_MASK) << RVC_B_IMM_5_OFF) | \
  193. (RVC_X(x_, RVC_B_IMM_7_6_OPOFF, RVC_B_IMM_7_6_MASK) << RVC_B_IMM_7_6_OFF) | \
  194. (RVC_IMM_SIGN(x_) << RVC_B_IMM_SIGN_OFF); })