mmio.h 5.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * {read,write}{b,w,l,q} based on arch/arm64/include/asm/io.h
  4. * which was based on arch/arm/include/io.h
  5. *
  6. * Copyright (C) 1996-2000 Russell King
  7. * Copyright (C) 2012 ARM Ltd.
  8. * Copyright (C) 2014 Regents of the University of California
  9. */
  10. #ifndef _ASM_RISCV_MMIO_H
  11. #define _ASM_RISCV_MMIO_H
  12. #include <linux/types.h>
  13. #include <asm/mmiowb.h>
  14. /* Generic IO read/write. These perform native-endian accesses. */
  15. #define __raw_writeb __raw_writeb
  16. static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
  17. {
  18. asm volatile("sb %0, 0(%1)" : : "r" (val), "r" (addr));
  19. }
  20. #define __raw_writew __raw_writew
  21. static inline void __raw_writew(u16 val, volatile void __iomem *addr)
  22. {
  23. asm volatile("sh %0, 0(%1)" : : "r" (val), "r" (addr));
  24. }
  25. #define __raw_writel __raw_writel
  26. static inline void __raw_writel(u32 val, volatile void __iomem *addr)
  27. {
  28. asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr));
  29. }
  30. #ifdef CONFIG_64BIT
  31. #define __raw_writeq __raw_writeq
  32. static inline void __raw_writeq(u64 val, volatile void __iomem *addr)
  33. {
  34. asm volatile("sd %0, 0(%1)" : : "r" (val), "r" (addr));
  35. }
  36. #endif
  37. #define __raw_readb __raw_readb
  38. static inline u8 __raw_readb(const volatile void __iomem *addr)
  39. {
  40. u8 val;
  41. asm volatile("lb %0, 0(%1)" : "=r" (val) : "r" (addr));
  42. return val;
  43. }
  44. #define __raw_readw __raw_readw
  45. static inline u16 __raw_readw(const volatile void __iomem *addr)
  46. {
  47. u16 val;
  48. asm volatile("lh %0, 0(%1)" : "=r" (val) : "r" (addr));
  49. return val;
  50. }
  51. #define __raw_readl __raw_readl
  52. static inline u32 __raw_readl(const volatile void __iomem *addr)
  53. {
  54. u32 val;
  55. asm volatile("lw %0, 0(%1)" : "=r" (val) : "r" (addr));
  56. return val;
  57. }
  58. #ifdef CONFIG_64BIT
  59. #define __raw_readq __raw_readq
  60. static inline u64 __raw_readq(const volatile void __iomem *addr)
  61. {
  62. u64 val;
  63. asm volatile("ld %0, 0(%1)" : "=r" (val) : "r" (addr));
  64. return val;
  65. }
  66. #endif
  67. /*
  68. * Unordered I/O memory access primitives. These are even more relaxed than
  69. * the relaxed versions, as they don't even order accesses between successive
  70. * operations to the I/O regions.
  71. */
  72. #define readb_cpu(c) ({ u8 __r = __raw_readb(c); __r; })
  73. #define readw_cpu(c) ({ u16 __r = le16_to_cpu((__force __le16)__raw_readw(c)); __r; })
  74. #define readl_cpu(c) ({ u32 __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; })
  75. #define writeb_cpu(v, c) ((void)__raw_writeb((v), (c)))
  76. #define writew_cpu(v, c) ((void)__raw_writew((__force u16)cpu_to_le16(v), (c)))
  77. #define writel_cpu(v, c) ((void)__raw_writel((__force u32)cpu_to_le32(v), (c)))
  78. #ifdef CONFIG_64BIT
  79. #define readq_cpu(c) ({ u64 __r = le64_to_cpu((__force __le64)__raw_readq(c)); __r; })
  80. #define writeq_cpu(v, c) ((void)__raw_writeq((__force u64)cpu_to_le64(v), (c)))
  81. #endif
  82. /*
  83. * Relaxed I/O memory access primitives. These follow the Device memory
  84. * ordering rules but do not guarantee any ordering relative to Normal memory
  85. * accesses. These are defined to order the indicated access (either a read or
  86. * write) with all other I/O memory accesses. Since the platform specification
  87. * defines that all I/O regions are strongly ordered on channel 2, no explicit
  88. * fences are required to enforce this ordering.
  89. */
  90. /* FIXME: These are now the same as asm-generic */
  91. #define __io_rbr() do {} while (0)
  92. #define __io_rar() do {} while (0)
  93. #define __io_rbw() do {} while (0)
  94. #define __io_raw() do {} while (0)
  95. #define readb_relaxed(c) ({ u8 __v; __io_rbr(); __v = readb_cpu(c); __io_rar(); __v; })
  96. #define readw_relaxed(c) ({ u16 __v; __io_rbr(); __v = readw_cpu(c); __io_rar(); __v; })
  97. #define readl_relaxed(c) ({ u32 __v; __io_rbr(); __v = readl_cpu(c); __io_rar(); __v; })
  98. #define writeb_relaxed(v, c) ({ __io_rbw(); writeb_cpu((v), (c)); __io_raw(); })
  99. #define writew_relaxed(v, c) ({ __io_rbw(); writew_cpu((v), (c)); __io_raw(); })
  100. #define writel_relaxed(v, c) ({ __io_rbw(); writel_cpu((v), (c)); __io_raw(); })
  101. #ifdef CONFIG_64BIT
  102. #define readq_relaxed(c) ({ u64 __v; __io_rbr(); __v = readq_cpu(c); __io_rar(); __v; })
  103. #define writeq_relaxed(v, c) ({ __io_rbw(); writeq_cpu((v), (c)); __io_raw(); })
  104. #endif
  105. /*
  106. * I/O memory access primitives. Reads are ordered relative to any
  107. * following Normal memory access. Writes are ordered relative to any prior
  108. * Normal memory access. The memory barriers here are necessary as RISC-V
  109. * doesn't define any ordering between the memory space and the I/O space.
  110. */
  111. #define __io_br() do {} while (0)
  112. #define __io_ar(v) __asm__ __volatile__ ("fence i,r" : : : "memory")
  113. #define __io_bw() __asm__ __volatile__ ("fence w,o" : : : "memory")
  114. #define __io_aw() mmiowb_set_pending()
  115. #define readb(c) ({ u8 __v; __io_br(); __v = readb_cpu(c); __io_ar(__v); __v; })
  116. #define readw(c) ({ u16 __v; __io_br(); __v = readw_cpu(c); __io_ar(__v); __v; })
  117. #define readl(c) ({ u32 __v; __io_br(); __v = readl_cpu(c); __io_ar(__v); __v; })
  118. #define writeb(v, c) ({ __io_bw(); writeb_cpu((v), (c)); __io_aw(); })
  119. #define writew(v, c) ({ __io_bw(); writew_cpu((v), (c)); __io_aw(); })
  120. #define writel(v, c) ({ __io_bw(); writel_cpu((v), (c)); __io_aw(); })
  121. #ifdef CONFIG_64BIT
  122. #define readq(c) ({ u64 __v; __io_br(); __v = readq_cpu(c); __io_ar(__v); __v; })
  123. #define writeq(v, c) ({ __io_bw(); writeq_cpu((v), (c)); __io_aw(); })
  124. #endif
  125. #endif /* _ASM_RISCV_MMIO_H */