io.h 6.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * {read,write}{b,w,l,q} based on arch/arm64/include/asm/io.h
  4. * which was based on arch/arm/include/io.h
  5. *
  6. * Copyright (C) 1996-2000 Russell King
  7. * Copyright (C) 2012 ARM Ltd.
  8. * Copyright (C) 2014 Regents of the University of California
  9. */
  10. #ifndef _ASM_RISCV_IO_H
  11. #define _ASM_RISCV_IO_H
  12. #include <linux/types.h>
  13. #include <linux/pgtable.h>
  14. #include <asm/mmiowb.h>
  15. #include <asm/early_ioremap.h>
  16. /*
  17. * MMIO access functions are separated out to break dependency cycles
  18. * when using {read,write}* fns in low-level headers
  19. */
  20. #include <asm/mmio.h>
  21. /*
  22. * I/O port access constants.
  23. */
  24. #ifdef CONFIG_MMU
  25. #define IO_SPACE_LIMIT (PCI_IO_SIZE - 1)
  26. #define PCI_IOBASE ((void __iomem *)PCI_IO_START)
  27. #endif /* CONFIG_MMU */
  28. /*
  29. * Emulation routines for the port-mapped IO space used by some PCI drivers.
  30. * These are defined as being "fully synchronous", but also "not guaranteed to
  31. * be fully ordered with respect to other memory and I/O operations". We're
  32. * going to be on the safe side here and just make them:
  33. * - Fully ordered WRT each other, by bracketing them with two fences. The
  34. * outer set contains both I/O so inX is ordered with outX, while the inner just
  35. * needs the type of the access (I for inX and O for outX).
  36. * - Ordered in the same manner as readX/writeX WRT memory by subsuming their
  37. * fences.
  38. * - Ordered WRT timer reads, so udelay and friends don't get elided by the
  39. * implementation.
  40. * Note that there is no way to actually enforce that outX is a non-posted
  41. * operation on RISC-V, but hopefully the timer ordering constraint is
  42. * sufficient to ensure this works sanely on controllers that support I/O
  43. * writes.
  44. */
  45. #define __io_pbr() __asm__ __volatile__ ("fence io,i" : : : "memory");
  46. #define __io_par(v) __asm__ __volatile__ ("fence i,ior" : : : "memory");
  47. #define __io_pbw() __asm__ __volatile__ ("fence iow,o" : : : "memory");
  48. #define __io_paw() __asm__ __volatile__ ("fence o,io" : : : "memory");
  49. #define inb(c) ({ u8 __v; __io_pbr(); __v = readb_cpu((void*)(PCI_IOBASE + (c))); __io_par(__v); __v; })
  50. #define inw(c) ({ u16 __v; __io_pbr(); __v = readw_cpu((void*)(PCI_IOBASE + (c))); __io_par(__v); __v; })
  51. #define inl(c) ({ u32 __v; __io_pbr(); __v = readl_cpu((void*)(PCI_IOBASE + (c))); __io_par(__v); __v; })
  52. #define outb(v,c) ({ __io_pbw(); writeb_cpu((v),(void*)(PCI_IOBASE + (c))); __io_paw(); })
  53. #define outw(v,c) ({ __io_pbw(); writew_cpu((v),(void*)(PCI_IOBASE + (c))); __io_paw(); })
  54. #define outl(v,c) ({ __io_pbw(); writel_cpu((v),(void*)(PCI_IOBASE + (c))); __io_paw(); })
  55. #ifdef CONFIG_64BIT
  56. #define inq(c) ({ u64 __v; __io_pbr(); __v = readq_cpu((void*)(c)); __io_par(__v); __v; })
  57. #define outq(v,c) ({ __io_pbw(); writeq_cpu((v),(void*)(c)); __io_paw(); })
  58. #endif
  59. /*
  60. * Accesses from a single hart to a single I/O address must be ordered. This
  61. * allows us to use the raw read macros, but we still need to fence before and
  62. * after the block to ensure ordering WRT other macros. These are defined to
  63. * perform host-endian accesses so we use __raw instead of __cpu.
  64. */
  65. #define __io_reads_ins(port, ctype, len, bfence, afence) \
  66. static inline void __ ## port ## len(const volatile void __iomem *addr, \
  67. void *buffer, \
  68. unsigned int count) \
  69. { \
  70. bfence; \
  71. if (count) { \
  72. ctype *buf = buffer; \
  73. \
  74. do { \
  75. ctype x = __raw_read ## len(addr); \
  76. *buf++ = x; \
  77. } while (--count); \
  78. } \
  79. afence; \
  80. }
  81. #define __io_writes_outs(port, ctype, len, bfence, afence) \
  82. static inline void __ ## port ## len(volatile void __iomem *addr, \
  83. const void *buffer, \
  84. unsigned int count) \
  85. { \
  86. bfence; \
  87. if (count) { \
  88. const ctype *buf = buffer; \
  89. \
  90. do { \
  91. __raw_write ## len(*buf++, addr); \
  92. } while (--count); \
  93. } \
  94. afence; \
  95. }
  96. __io_reads_ins(reads, u8, b, __io_br(), __io_ar(addr))
  97. __io_reads_ins(reads, u16, w, __io_br(), __io_ar(addr))
  98. __io_reads_ins(reads, u32, l, __io_br(), __io_ar(addr))
  99. #define readsb(addr, buffer, count) __readsb(addr, buffer, count)
  100. #define readsw(addr, buffer, count) __readsw(addr, buffer, count)
  101. #define readsl(addr, buffer, count) __readsl(addr, buffer, count)
  102. __io_reads_ins(ins, u8, b, __io_pbr(), __io_par(addr))
  103. __io_reads_ins(ins, u16, w, __io_pbr(), __io_par(addr))
  104. __io_reads_ins(ins, u32, l, __io_pbr(), __io_par(addr))
  105. #define insb(addr, buffer, count) __insb((void __iomem *)(long)addr, buffer, count)
  106. #define insw(addr, buffer, count) __insw((void __iomem *)(long)addr, buffer, count)
  107. #define insl(addr, buffer, count) __insl((void __iomem *)(long)addr, buffer, count)
  108. __io_writes_outs(writes, u8, b, __io_bw(), __io_aw())
  109. __io_writes_outs(writes, u16, w, __io_bw(), __io_aw())
  110. __io_writes_outs(writes, u32, l, __io_bw(), __io_aw())
  111. #define writesb(addr, buffer, count) __writesb(addr, buffer, count)
  112. #define writesw(addr, buffer, count) __writesw(addr, buffer, count)
  113. #define writesl(addr, buffer, count) __writesl(addr, buffer, count)
  114. __io_writes_outs(outs, u8, b, __io_pbw(), __io_paw())
  115. __io_writes_outs(outs, u16, w, __io_pbw(), __io_paw())
  116. __io_writes_outs(outs, u32, l, __io_pbw(), __io_paw())
  117. #define outsb(addr, buffer, count) __outsb((void __iomem *)(long)addr, buffer, count)
  118. #define outsw(addr, buffer, count) __outsw((void __iomem *)(long)addr, buffer, count)
  119. #define outsl(addr, buffer, count) __outsl((void __iomem *)(long)addr, buffer, count)
  120. #ifdef CONFIG_64BIT
  121. __io_reads_ins(reads, u64, q, __io_br(), __io_ar(addr))
  122. #define readsq(addr, buffer, count) __readsq(addr, buffer, count)
  123. __io_reads_ins(ins, u64, q, __io_pbr(), __io_par(addr))
  124. #define insq(addr, buffer, count) __insq((void __iomem *)addr, buffer, count)
  125. __io_writes_outs(writes, u64, q, __io_bw(), __io_aw())
  126. #define writesq(addr, buffer, count) __writesq(addr, buffer, count)
  127. __io_writes_outs(outs, u64, q, __io_pbr(), __io_paw())
  128. #define outsq(addr, buffer, count) __outsq((void __iomem *)addr, buffer, count)
  129. #endif
  130. #include <asm-generic/io.h>
  131. #endif /* _ASM_RISCV_IO_H */