image.h 1.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. #ifndef _ASM_RISCV_IMAGE_H
  3. #define _ASM_RISCV_IMAGE_H
  4. #define RISCV_IMAGE_MAGIC "RISCV\0\0\0"
  5. #define RISCV_IMAGE_MAGIC2 "RSC\x05"
  6. #define RISCV_IMAGE_FLAG_BE_SHIFT 0
  7. #define RISCV_IMAGE_FLAG_BE_MASK 0x1
  8. #define RISCV_IMAGE_FLAG_LE 0
  9. #define RISCV_IMAGE_FLAG_BE 1
  10. #ifdef CONFIG_CPU_BIG_ENDIAN
  11. #error conversion of header fields to LE not yet implemented
  12. #else
  13. #define __HEAD_FLAG_BE RISCV_IMAGE_FLAG_LE
  14. #endif
  15. #define __HEAD_FLAG(field) (__HEAD_FLAG_##field << \
  16. RISCV_IMAGE_FLAG_##field##_SHIFT)
  17. #define __HEAD_FLAGS (__HEAD_FLAG(BE))
  18. #define RISCV_HEADER_VERSION_MAJOR 0
  19. #define RISCV_HEADER_VERSION_MINOR 2
  20. #define RISCV_HEADER_VERSION (RISCV_HEADER_VERSION_MAJOR << 16 | \
  21. RISCV_HEADER_VERSION_MINOR)
  22. #ifndef __ASSEMBLY__
  23. /**
  24. * struct riscv_image_header - riscv kernel image header
  25. * @code0: Executable code
  26. * @code1: Executable code
  27. * @text_offset: Image load offset (little endian)
  28. * @image_size: Effective Image size (little endian)
  29. * @flags: kernel flags (little endian)
  30. * @version: version
  31. * @res1: reserved
  32. * @res2: reserved
  33. * @magic: Magic number (RISC-V specific; deprecated)
  34. * @magic2: Magic number 2 (to match the ARM64 'magic' field pos)
  35. * @res3: reserved (will be used for PE COFF offset)
  36. *
  37. * The intention is for this header format to be shared between multiple
  38. * architectures to avoid a proliferation of image header formats.
  39. */
  40. struct riscv_image_header {
  41. u32 code0;
  42. u32 code1;
  43. u64 text_offset;
  44. u64 image_size;
  45. u64 flags;
  46. u32 version;
  47. u32 res1;
  48. u64 res2;
  49. u64 magic;
  50. u32 magic2;
  51. u32 res3;
  52. };
  53. #endif /* __ASSEMBLY__ */
  54. #endif /* _ASM_RISCV_IMAGE_H */