hwcap.h 1.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copied from arch/arm64/include/asm/hwcap.h
  4. *
  5. * Copyright (C) 2012 ARM Ltd.
  6. * Copyright (C) 2017 SiFive
  7. */
  8. #ifndef _ASM_RISCV_HWCAP_H
  9. #define _ASM_RISCV_HWCAP_H
  10. #include <linux/bits.h>
  11. #include <uapi/asm/hwcap.h>
  12. #ifndef __ASSEMBLY__
  13. /*
  14. * This yields a mask that user programs can use to figure out what
  15. * instruction set this cpu supports.
  16. */
  17. #define ELF_HWCAP (elf_hwcap)
  18. enum {
  19. CAP_HWCAP = 1,
  20. };
  21. extern unsigned long elf_hwcap;
  22. #define RISCV_ISA_EXT_a ('a' - 'a')
  23. #define RISCV_ISA_EXT_c ('c' - 'a')
  24. #define RISCV_ISA_EXT_d ('d' - 'a')
  25. #define RISCV_ISA_EXT_f ('f' - 'a')
  26. #define RISCV_ISA_EXT_h ('h' - 'a')
  27. #define RISCV_ISA_EXT_i ('i' - 'a')
  28. #define RISCV_ISA_EXT_m ('m' - 'a')
  29. #define RISCV_ISA_EXT_s ('s' - 'a')
  30. #define RISCV_ISA_EXT_u ('u' - 'a')
  31. #define RISCV_ISA_EXT_MAX 64
  32. unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap);
  33. #define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext)
  34. bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit);
  35. #define riscv_isa_extension_available(isa_bitmap, ext) \
  36. __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_##ext)
  37. #endif
  38. #endif /* _ASM_RISCV_HWCAP_H */