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- /* SPDX-License-Identifier: GPL-2.0-only */
- /*
- * Copied from arch/arm64/include/asm/hwcap.h
- *
- * Copyright (C) 2012 ARM Ltd.
- * Copyright (C) 2017 SiFive
- */
- #ifndef _ASM_RISCV_HWCAP_H
- #define _ASM_RISCV_HWCAP_H
- #include <linux/bits.h>
- #include <uapi/asm/hwcap.h>
- #ifndef __ASSEMBLY__
- /*
- * This yields a mask that user programs can use to figure out what
- * instruction set this cpu supports.
- */
- #define ELF_HWCAP (elf_hwcap)
- enum {
- CAP_HWCAP = 1,
- };
- extern unsigned long elf_hwcap;
- #define RISCV_ISA_EXT_a ('a' - 'a')
- #define RISCV_ISA_EXT_c ('c' - 'a')
- #define RISCV_ISA_EXT_d ('d' - 'a')
- #define RISCV_ISA_EXT_f ('f' - 'a')
- #define RISCV_ISA_EXT_h ('h' - 'a')
- #define RISCV_ISA_EXT_i ('i' - 'a')
- #define RISCV_ISA_EXT_m ('m' - 'a')
- #define RISCV_ISA_EXT_s ('s' - 'a')
- #define RISCV_ISA_EXT_u ('u' - 'a')
- #define RISCV_ISA_EXT_MAX 64
- unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap);
- #define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext)
- bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit);
- #define riscv_isa_extension_available(isa_bitmap, ext) \
- __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_##ext)
- #endif
- #endif /* _ASM_RISCV_HWCAP_H */
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