csr.h 6.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (C) 2015 Regents of the University of California
  4. */
  5. #ifndef _ASM_RISCV_CSR_H
  6. #define _ASM_RISCV_CSR_H
  7. #include <asm/asm.h>
  8. #include <linux/const.h>
  9. /* Status register flags */
  10. #define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */
  11. #define SR_MIE _AC(0x00000008, UL) /* Machine Interrupt Enable */
  12. #define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */
  13. #define SR_MPIE _AC(0x00000080, UL) /* Previous Machine IE */
  14. #define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */
  15. #define SR_MPP _AC(0x00001800, UL) /* Previously Machine */
  16. #define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */
  17. #define SR_FS _AC(0x00006000, UL) /* Floating-point Status */
  18. #define SR_FS_OFF _AC(0x00000000, UL)
  19. #define SR_FS_INITIAL _AC(0x00002000, UL)
  20. #define SR_FS_CLEAN _AC(0x00004000, UL)
  21. #define SR_FS_DIRTY _AC(0x00006000, UL)
  22. #define SR_VS_OFF _AC(0x00000000, UL)
  23. #if (defined(CONFIG_VECTOR_1_0) && defined(__THEAD_VERSION__))
  24. #define SR_VS _AC(0x00000600, UL) /* Vector Status */
  25. #define SR_VS_INITIAL _AC(0x00000200, UL)
  26. #define SR_VS_CLEAN _AC(0x00000400, UL)
  27. #define SR_VS_DIRTY _AC(0x00000600, UL)
  28. #else
  29. #define SR_VS _AC(0x01800000, UL) /* Vector Status */
  30. #define SR_VS_INITIAL _AC(0x00800000, UL)
  31. #define SR_VS_CLEAN _AC(0x01000000, UL)
  32. #define SR_VS_DIRTY _AC(0x01800000, UL)
  33. #endif
  34. #define SR_XS _AC(0x00018000, UL) /* Extension Status */
  35. #define SR_XS_OFF _AC(0x00000000, UL)
  36. #define SR_XS_INITIAL _AC(0x00008000, UL)
  37. #define SR_XS_CLEAN _AC(0x00010000, UL)
  38. #define SR_XS_DIRTY _AC(0x00018000, UL)
  39. #ifndef CONFIG_64BIT
  40. #define SR_SD _AC(0x80000000, UL) /* FS/XS dirty */
  41. #else
  42. #define SR_SD _AC(0x8000000000000000, UL) /* FS/XS dirty */
  43. #endif
  44. #ifdef CONFIG_COMPAT
  45. #define SR_UXL _AC(0x300000000, UL) /* XLEN mask for U-mode */
  46. #define SR_UXL_32 _AC(0x100000000, UL) /* XLEN = 32 for U-mode */
  47. #define SR_UXL_64 _AC(0x200000000, UL) /* XLEN = 64 for U-mode */
  48. #define SR_UXL_SHIFT 32
  49. #endif
  50. /* SATP flags */
  51. #ifndef CONFIG_64BIT
  52. #define SATP_PPN _AC(0x003FFFFF, UL)
  53. #define SATP_MODE_32 _AC(0x80000000, UL)
  54. #define SATP_MODE SATP_MODE_32
  55. #else
  56. #define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL)
  57. #define SATP_MODE_39 _AC(0x8000000000000000, UL)
  58. #define SATP_MODE SATP_MODE_39
  59. #define SATP_ASID_BITS 16
  60. #define SATP_ASID_SHIFT 44
  61. #define SATP_ASID_MASK _AC(0xFFFF, UL)
  62. #endif
  63. /* Exception cause high bit - is an interrupt if set */
  64. #define CAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1))
  65. /* Interrupt causes (minus the high bit) */
  66. #define IRQ_S_SOFT 1
  67. #define IRQ_M_SOFT 3
  68. #define IRQ_S_TIMER 5
  69. #define IRQ_M_TIMER 7
  70. #define IRQ_S_EXT 9
  71. #define IRQ_M_EXT 11
  72. /* Exception causes */
  73. #define EXC_INST_MISALIGNED 0
  74. #define EXC_INST_ACCESS 1
  75. #define EXC_BREAKPOINT 3
  76. #define EXC_LOAD_ACCESS 5
  77. #define EXC_STORE_ACCESS 7
  78. #define EXC_SYSCALL 8
  79. #define EXC_INST_PAGE_FAULT 12
  80. #define EXC_LOAD_PAGE_FAULT 13
  81. #define EXC_STORE_PAGE_FAULT 15
  82. /* PMP configuration */
  83. #define PMP_R 0x01
  84. #define PMP_W 0x02
  85. #define PMP_X 0x04
  86. #define PMP_A 0x18
  87. #define PMP_A_TOR 0x08
  88. #define PMP_A_NA4 0x10
  89. #define PMP_A_NAPOT 0x18
  90. #define PMP_L 0x80
  91. /* symbolic CSR names: */
  92. #define CSR_CYCLE 0xc00
  93. #define CSR_TIME 0xc01
  94. #define CSR_INSTRET 0xc02
  95. #define CSR_CYCLEH 0xc80
  96. #define CSR_TIMEH 0xc81
  97. #define CSR_INSTRETH 0xc82
  98. #define CSR_SSTATUS 0x100
  99. #define CSR_SIE 0x104
  100. #define CSR_STVEC 0x105
  101. #define CSR_SCOUNTEREN 0x106
  102. #define CSR_SSCRATCH 0x140
  103. #define CSR_SEPC 0x141
  104. #define CSR_SCAUSE 0x142
  105. #define CSR_STVAL 0x143
  106. #define CSR_SIP 0x144
  107. #define CSR_SATP 0x180
  108. #define CSR_MSTATUS 0x300
  109. #define CSR_MISA 0x301
  110. #define CSR_MIE 0x304
  111. #define CSR_MTVEC 0x305
  112. #define CSR_MSCRATCH 0x340
  113. #define CSR_MEPC 0x341
  114. #define CSR_MCAUSE 0x342
  115. #define CSR_MTVAL 0x343
  116. #define CSR_MIP 0x344
  117. #define CSR_PMPCFG0 0x3a0
  118. #define CSR_PMPADDR0 0x3b0
  119. #define CSR_MHARTID 0xf14
  120. #define CSR_VSTART 0x8
  121. #define CSR_VXSAT 0x9
  122. #define CSR_VXRM 0xa
  123. #define CSR_VL 0xc20
  124. #define CSR_VTYPE 0xc21
  125. #define CSR_VLENB 0xc22
  126. #define CSR_SMIR 0x9c0
  127. #define CSR_SMEL 0x9c1
  128. #define CSR_SMEH 0x9c2
  129. #define CSR_SMCIR 0x9c3
  130. #ifdef CONFIG_RISCV_M_MODE
  131. # define CSR_STATUS CSR_MSTATUS
  132. # define CSR_IE CSR_MIE
  133. # define CSR_TVEC CSR_MTVEC
  134. # define CSR_SCRATCH CSR_MSCRATCH
  135. # define CSR_EPC CSR_MEPC
  136. # define CSR_CAUSE CSR_MCAUSE
  137. # define CSR_TVAL CSR_MTVAL
  138. # define CSR_IP CSR_MIP
  139. # define SR_IE SR_MIE
  140. # define SR_PIE SR_MPIE
  141. # define SR_PP SR_MPP
  142. # define RV_IRQ_SOFT IRQ_M_SOFT
  143. # define RV_IRQ_TIMER IRQ_M_TIMER
  144. # define RV_IRQ_EXT IRQ_M_EXT
  145. #else /* CONFIG_RISCV_M_MODE */
  146. # define CSR_STATUS CSR_SSTATUS
  147. # define CSR_IE CSR_SIE
  148. # define CSR_TVEC CSR_STVEC
  149. # define CSR_SCRATCH CSR_SSCRATCH
  150. # define CSR_EPC CSR_SEPC
  151. # define CSR_CAUSE CSR_SCAUSE
  152. # define CSR_TVAL CSR_STVAL
  153. # define CSR_IP CSR_SIP
  154. # define SR_IE SR_SIE
  155. # define SR_PIE SR_SPIE
  156. # define SR_PP SR_SPP
  157. # define RV_IRQ_SOFT IRQ_S_SOFT
  158. # define RV_IRQ_TIMER IRQ_S_TIMER
  159. # define RV_IRQ_EXT IRQ_S_EXT
  160. #endif /* CONFIG_RISCV_M_MODE */
  161. /* IE/IP (Supervisor/Machine Interrupt Enable/Pending) flags */
  162. #define IE_SIE (_AC(0x1, UL) << RV_IRQ_SOFT)
  163. #define IE_TIE (_AC(0x1, UL) << RV_IRQ_TIMER)
  164. #define IE_EIE (_AC(0x1, UL) << RV_IRQ_EXT)
  165. #ifndef __ASSEMBLY__
  166. #define csr_swap(csr, val) \
  167. ({ \
  168. unsigned long __v = (unsigned long)(val); \
  169. __asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\
  170. : "=r" (__v) : "rK" (__v) \
  171. : "memory"); \
  172. __v; \
  173. })
  174. #define csr_read(csr) \
  175. ({ \
  176. register unsigned long __v; \
  177. __asm__ __volatile__ ("csrr %0, " __ASM_STR(csr) \
  178. : "=r" (__v) : \
  179. : "memory"); \
  180. __v; \
  181. })
  182. #define csr_write(csr, val) \
  183. ({ \
  184. unsigned long __v = (unsigned long)(val); \
  185. __asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0" \
  186. : : "rK" (__v) \
  187. : "memory"); \
  188. })
  189. #define csr_read_set(csr, val) \
  190. ({ \
  191. unsigned long __v = (unsigned long)(val); \
  192. __asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\
  193. : "=r" (__v) : "rK" (__v) \
  194. : "memory"); \
  195. __v; \
  196. })
  197. #define csr_set(csr, val) \
  198. ({ \
  199. unsigned long __v = (unsigned long)(val); \
  200. __asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0" \
  201. : : "rK" (__v) \
  202. : "memory"); \
  203. })
  204. #define csr_read_clear(csr, val) \
  205. ({ \
  206. unsigned long __v = (unsigned long)(val); \
  207. __asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\
  208. : "=r" (__v) : "rK" (__v) \
  209. : "memory"); \
  210. __v; \
  211. })
  212. #define csr_clear(csr, val) \
  213. ({ \
  214. unsigned long __v = (unsigned long)(val); \
  215. __asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0" \
  216. : : "rK" (__v) \
  217. : "memory"); \
  218. })
  219. #endif /* __ASSEMBLY__ */
  220. #endif /* _ASM_RISCV_CSR_H */