cacheflush.h 1.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (C) 2015 Regents of the University of California
  4. */
  5. #ifndef _ASM_RISCV_CACHEFLUSH_H
  6. #define _ASM_RISCV_CACHEFLUSH_H
  7. #include <linux/mm.h>
  8. static inline void local_flush_icache_all(void)
  9. {
  10. asm volatile ("fence.i" ::: "memory");
  11. }
  12. #define PG_dcache_clean PG_arch_1
  13. static inline void flush_dcache_page(struct page *page)
  14. {
  15. if (test_bit(PG_dcache_clean, &page->flags))
  16. clear_bit(PG_dcache_clean, &page->flags);
  17. }
  18. #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
  19. /*
  20. * RISC-V doesn't have an instruction to flush parts of the instruction cache,
  21. * so instead we just flush the whole thing.
  22. */
  23. #define flush_icache_range(start, end) flush_icache_all()
  24. #define flush_icache_user_page(vma, pg, addr, len) \
  25. flush_icache_mm(vma->vm_mm, 0)
  26. #ifndef CONFIG_SMP
  27. #define flush_icache_all() local_flush_icache_all()
  28. #define flush_icache_mm(mm, local) flush_icache_all()
  29. #else /* CONFIG_SMP */
  30. void flush_icache_all(void);
  31. void flush_icache_mm(struct mm_struct *mm, bool local);
  32. #endif /* CONFIG_SMP */
  33. void dma_wbinv_range(unsigned long start, unsigned long end);
  34. void dma_wb_range(unsigned long start, unsigned long end);
  35. /*
  36. * Bits in sys_riscv_flush_icache()'s flags argument.
  37. */
  38. #define SYS_RISCV_FLUSH_ICACHE_LOCAL 1UL
  39. #define SYS_RISCV_FLUSH_ICACHE_ALL (SYS_RISCV_FLUSH_ICACHE_LOCAL)
  40. #include <asm-generic/cacheflush.h>
  41. #endif /* _ASM_RISCV_CACHEFLUSH_H */