light_mpw.dts 6.0 KB

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  1. /dts-v1/;
  2. / {
  3. model = "T-HEAD c910 light mpw";
  4. compatible = "thead,c910_light_mpw";
  5. #address-cells = <2>;
  6. #size-cells = <2>;
  7. memory@0 {
  8. device_type = "memory";
  9. reg = <0x0 0x00200000 0x0 0xf0000000>;
  10. };
  11. cpus {
  12. #address-cells = <1>;
  13. #size-cells = <0>;
  14. timebase-frequency = <0x2dc6c0>;
  15. cpu@0 {
  16. device_type = "cpu";
  17. reg = <0>;
  18. status = "okay";
  19. compatible = "riscv";
  20. riscv,isa = "rv64imafdcvsu";
  21. mmu-type = "riscv,sv39";
  22. cpu-freq = "1.5Ghz";
  23. cpu-icache = "64KB";
  24. cpu-dcache = "64KB";
  25. cpu-l2cache = "2MB";
  26. cpu-tlb = "1024 4-ways";
  27. cpu-cacheline = "64Bytes";
  28. cpu-vector = "0.7.1";
  29. cpu0_intc: interrupt-controller {
  30. #interrupt-cells = <1>;
  31. compatible = "riscv,cpu-intc";
  32. interrupt-controller;
  33. };
  34. };
  35. cpu@1 {
  36. device_type = "cpu";
  37. reg = <1>;
  38. status = "okay";
  39. compatible = "riscv";
  40. riscv,isa = "rv64imafdcvsu";
  41. mmu-type = "riscv,sv39";
  42. cpu-freq = "1.5Ghz";
  43. cpu-icache = "64KB";
  44. cpu-dcache = "64KB";
  45. cpu-l2cache = "2MB";
  46. cpu-tlb = "1024 4-ways";
  47. cpu-cacheline = "64Bytes";
  48. cpu-vector = "0.7.1";
  49. cpu1_intc: interrupt-controller {
  50. #interrupt-cells = <1>;
  51. compatible = "riscv,cpu-intc";
  52. interrupt-controller;
  53. };
  54. };
  55. cpu@2 {
  56. device_type = "cpu";
  57. reg = <2>;
  58. status = "okay";
  59. compatible = "riscv";
  60. riscv,isa = "rv64imafdcvsu";
  61. mmu-type = "riscv,sv39";
  62. cpu-freq = "1.5Ghz";
  63. cpu-icache = "64KB";
  64. cpu-dcache = "64KB";
  65. cpu-l2cache = "2MB";
  66. cpu-tlb = "1024 4-ways";
  67. cpu-cacheline = "64Bytes";
  68. cpu-vector = "0.7.1";
  69. cpu2_intc: interrupt-controller {
  70. #interrupt-cells = <1>;
  71. compatible = "riscv,cpu-intc";
  72. interrupt-controller;
  73. };
  74. };
  75. cpu@3 {
  76. device_type = "cpu";
  77. reg = <3>;
  78. status = "okay";
  79. compatible = "riscv";
  80. riscv,isa = "rv64imafdcvsu";
  81. mmu-type = "riscv,sv39";
  82. cpu-freq = "1.5Ghz";
  83. cpu-icache = "64KB";
  84. cpu-dcache = "64KB";
  85. cpu-l2cache = "2MB";
  86. cpu-tlb = "1024 4-ways";
  87. cpu-cacheline = "64Bytes";
  88. cpu-vector = "0.7.1";
  89. cpu3_intc: interrupt-controller {
  90. #interrupt-cells = <1>;
  91. compatible = "riscv,cpu-intc";
  92. interrupt-controller;
  93. };
  94. };
  95. };
  96. soc {
  97. #address-cells = <2>;
  98. #size-cells = <2>;
  99. compatible = "simple-bus";
  100. ranges;
  101. reset: reset-sample {
  102. compatible = "thead,reset-sample";
  103. plic-delegate = <0xff 0xd81ffffc>;
  104. using-csr-reset;
  105. csr-copy = <
  106. 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc
  107. 0x3b0 0x3b1 0x3b2 0x3b3
  108. 0x3b4 0x3b5 0x3b6 0x3b7
  109. 0x3a0
  110. >;
  111. };
  112. clint0: clint@ffdc000000 {
  113. compatible = "riscv,clint0";
  114. interrupts-extended = <
  115. &cpu0_intc 3 &cpu0_intc 7
  116. &cpu1_intc 3 &cpu1_intc 7
  117. &cpu2_intc 3 &cpu2_intc 7
  118. &cpu3_intc 3 &cpu3_intc 7
  119. >;
  120. reg = <0xff 0xdc000000 0x0 0x04000000>;
  121. clint,has-no-64bit-mmio;
  122. };
  123. intc: interrupt-controller@ffd8000000 {
  124. #interrupt-cells = <1>;
  125. compatible = "riscv,plic0";
  126. interrupt-controller;
  127. interrupts-extended = <
  128. &cpu0_intc 0xffffffff &cpu0_intc 9
  129. &cpu1_intc 0xffffffff &cpu1_intc 9
  130. &cpu2_intc 0xffffffff &cpu2_intc 9
  131. &cpu3_intc 0xffffffff &cpu3_intc 9
  132. >;
  133. reg = <0xff 0xd8000000 0x0 0x08000000>;
  134. reg-names = "control";
  135. riscv,max-priority = <7>;
  136. riscv,ndev = <80>;
  137. };
  138. clocks {
  139. compatible = "simple-bus";
  140. #address-cells = <1>;
  141. #size-cells = <0>;
  142. dummy_apb: apb-clock {
  143. compatible = "fixed-clock";
  144. clock-frequency = <62500000>;
  145. clock-output-names = "dummy_apb";
  146. #clock-cells = <0>;
  147. };
  148. dummy_clock_sdhci: sdhci-clock {
  149. compatible = "fixed-clock";
  150. reg = <4>; /* Not address, just for index */
  151. clock-frequency = <198000000>;
  152. clock-output-names = "dummy_clock_sdhci";
  153. #clock-cells = <0>;
  154. };
  155. dummy_clock_gmac: gmac-clock {
  156. compatible = "fixed-clock";
  157. clock-frequency = <1000000000>;
  158. clock-output-names = "dummy_clock_gmac";
  159. #clock-cells = <0>;
  160. };
  161. };
  162. serial@ffe7014000 {
  163. compatible = "snps,dw-apb-uart";
  164. reg = <0xff 0xe7014000 0x0 0x4000>;
  165. interrupt-parent = <&intc>;
  166. interrupts = <36>;
  167. clocks = <&dummy_apb>;
  168. clock-names = "baudclk";
  169. reg-shift = <2>;
  170. reg-io-width = <4>;
  171. };
  172. stmmac_axi_setup: stmmac-axi-config {
  173. snps,wr_osr_lmt = <3>;
  174. snps,rd_osr_lmt = <3>;
  175. snps,blen = <16 8 4 0 0 0 0>;
  176. };
  177. gmac: ethernet@ffe7070000 {
  178. compatible = "snps,dwmac";
  179. reg = <0xff 0xe7070000 0x0 0x2000>;
  180. interrupt-parent = <&intc>;
  181. interrupts = <66>;
  182. interrupt-names = "macirq";
  183. clocks = <&dummy_clock_gmac>;
  184. clock-names = "stmmaceth";
  185. snps,pbl = <32>;
  186. snps,fixed-burst;
  187. snps,axi-config = <&stmmac_axi_setup>;
  188. phy-mode = "rgmii-txid";
  189. phy-handle = <&phy_88E1111>;
  190. mdio0 {
  191. #address-cells = <1>;
  192. #size-cells = <0>;
  193. compatible = "snps,dwmac-mdio";
  194. phy_88E1111: ethernet-phy@0 {
  195. reg = <0x1>;
  196. };
  197. };
  198. };
  199. emmc: sdhci@ffe7080000 {
  200. compatible = "snps,dwcmshc-sdhci-light-mpw";
  201. reg = <0xff 0xe7080000 0x0 0x10000
  202. 0xff 0xEF014060 0x0 0x4>;
  203. interrupt-parent = <&intc>;
  204. interrupts = <62>;
  205. interrupt-names = "sdhciirq";
  206. clocks = <&dummy_clock_sdhci>;
  207. clock-names = "core";
  208. max-frequency = <198000000>;
  209. non-removable;
  210. is_emmc;
  211. no-sdio;
  212. no-sd;
  213. no-1-8-v;
  214. bus-width = <8>;
  215. status = "okay";
  216. };
  217. sdcard: sd@ffe7090000 {
  218. compatible = "snps,dwcmshc-sdhci-light-mpw";
  219. reg = <0xff 0xe7090000 0x0 0x10000
  220. 0xff 0xEF014064 0x0 0x4>;
  221. interrupt-parent = <&intc>;
  222. interrupts = <64>;
  223. interrupt-names = "sdhci0irq";
  224. clocks = <&dummy_clock_sdhci>;
  225. clock-names = "core";
  226. max-frequency = <198000000>;
  227. bus-width = <4>;
  228. status = "okay";
  229. };
  230. pmu: pmu {
  231. interrupt-parent = <&cpu0_intc>;
  232. interrupts = <17>;
  233. compatible = "riscv,c910_pmu";
  234. };
  235. };
  236. chosen {
  237. bootargs = "console=ttyS0,115200 root=PARTUUID=80a5a8e9-c744-491a-93c1-4f4194fd690b rootfstype=ext4 rdinit=/sbin/init rootwait rw earlyprintk clk_ignore_unused loglevel=7 eth=00:a0:a0:a0:a0:a1";
  238. stdout-path = "/soc/serial@ffe7014000:115200";
  239. };
  240. };